CXD1257AR

CXD1257AR CCD Camera Timing Generator Description The CXD1257AR generates the timing pulses required by the CCD image sensors as well as signal processing circuits. Features • NTSC and PAL compatible • Electronic shutter function • H-driver • Compatible with digital and analog camera systems • Standby function Applications CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX026CKA, ICX027CKA ICX054AK, ICX055AK ICX056AK Block Diagram 62 64 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD Vss – 0.5 to +7.0 V • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage VO Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.25 • Operating temperature Topr –20 to +75 V °C VSS 8 21 28 40 VDD 24 25 56 15 16 17 18 19 20 60 VD INITIALIZE MODE SET 11 12 13 14 SYNC GEN 59 57 63 64 1 HD INITIALIZE ADR . COUNT 1/2 H – ROM LATCH ADR . COUNT V – ROM LATCH ADR . COUNT 23 ROG – ROM LATCH GATE 36 2 41 42 43 44 45 46 22 37 38 39 26 27 3 10 47 48 49 50 51 52 53 54 29 30 31 32 33 34 35 58 55 4 GATE GATE CONTROLLER 61 HTSG HIGH-SPEED PULSE GENERATION CIRCUIT DRIVER DECODER GATE COUNTER SHUT ROM DECODER 5 6 7 9 MICROCOMPUTER Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E91817B4X-PK CXD1257AR Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol OSCO OSCI EF ED0 ED1 ED2 SMD1 Vss SMD2 XVCT D1 D2 D3 D4 A5 A4 A3 A0 A1 A2 Vss RG NC VDD VDD H1 H2 Vss XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 I/O O I I I I I I — I O I I I I O O O O O O — O — — — O O — O O O O O O O Power supply. Power supply for H1 and H2. Clock output for CCD horizontal register drive. Clock output for CCD horizontal register drive. GND for H1 and H2. CCD discharge pulse output. Clock output for CCD vertical register drive. Clock output for CCD vertical register drive. CCD sensor charge readout pulse output. Clock output for CCD vertical register drive. CCD sensor charge readout pulse output. Clock output for CCD vertical register drive. Inverter output for oscillation. Inverter input for oscillation. Not used. (With pull-up resistor) Shutter speed setting. Strobe input for serial mode. (With pull-up resister) Shutter speed setting. Clock input for serial mode. (With pull-up resister) Shutter speed setting. Data input for serial mode. (With pull-up resister) Shutter mode setting. (With pull-up resister) GND Shutter mode setting. (With pull-up resister) Not used. (Open) Fix at Low in normal operation. (With pull-down resister) Fix at Low in normal operation. (With pull-down resister) Fix at Low in normal operation. (With pull-down resister) Low: NTSC, High: PAL. (With pull-down resister) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) GND Reset gate pulse output. Description –2– CXD1257AR Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol TEST2 MCK XSHP XSHD Vss XSP1 XSP2 XSH1 XSH2 XDL1 XDL2 BFG CLP1 CLP2 CLP3 CLP4 PBLK ID WEN GM VDD CL PS HD VD HTSG TEST XCK CK I/O I O O O — O O O O O O O O I/O I/O O O O O I — O I I I I I O I Description Test input. Set at Low in normal operation. NTSC: 1820fH/3, PAL: 1816fH/3. Output. Precharge level sample-and-hold pulse. Data sample-and-hold pulse. GND Color separation sample-and-hold pulse. Color separation sample-and-hold pulse. Switching sample-and-hold pulse. Switching sample-and-hold pulse. Delay line clock output. Delay line clock output. Pulse output for chroma modulator in encoder. Clamp pulse output. Clamp pulse output. When GM is set at High, standby mode switching input. Clamp pulse output. When GM is set at High, standby mode switching input. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Write enable output for low-speed shutter operation. Low: Analog signal processing, High: Digital signal processing. (With pull-down resister) Power supply. NTSC: 910fH, PAL: 908fH. Clock output. Switching for electronic shutter speed input method. (With pull-up resister) Low: Serial input, High: Parallel input. Horizontal synchronizing signal input. Vertical synchronizing signal input. (During Low, 9H for NTSC and 7.5H for PAL) Control input for XSG1 and XSG2. (With pull-up resistor) Low: XSG1, XSG2 halted, High: XSG1, XSG2 generated. Test input. Set at Low in normal operation. (With pull-down resister) NTSC: 1820fH, PAL: 1816fH. Clock output. NTSC: 1820fH, PAL: 1816fH. Clock input. –3– CXD1257AR Electrical Characteristics DC Characteristics Item Supply voltage Symbol VDD Conditions (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Min. 4.75 0.7VDD 0.3VDD 2.2 0.8 IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –8mA IOL = 8mA IOH = –1mA IOL = 1mA VIN = Vss or VDD VIL = 0V VIH = VDD 500k 40k 40k 2M 100k 100k VDD/2 VDD/2 5M 250k 250k VDD – 0.5 0.4 VDD – 0.5 0.4 VDD – 0.5 0.4 Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V V V Ω Ω Ω VIH1 Input voltage 1 (Input pins other than those below) VIL1 Input voltage 2 (Pins 59 and 60) Output voltage 1 (Output pins other than those below) Output voltage 2 (Pins 22, 37, 38, 39, 57, and 63) Output voltage 3 (Pins 26 and 27) Output voltage 4 (Pin 1) Feedback resister Pull-up resister Pull-down resister VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RFB RPU RPD I/O Pin Capacitances Item Input pin capacitance Output pin capacitance I/O pin capacitance Symbol CIN COUT CI/O Min. (VDD = VI = 0V, fM = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF –4– CXD1257AR Description of Operation 1. Mode Control Symbol GM PS EF HTSG D1 D2 D3 D4 Pin No. 55 58 3 61 11 12 13 14 L Analog signal processing Serial shutter speed setting H Digital signal processing Parallel shutter speed setting Fix at High in normal operation XSG1, 2 OFF XSG1, 2 ON Fix at Low in normal operation Fix at Low in normal operation Fix at Low in normal operation NTSC PAL –5– CXD1257AR 2. Changes in I/O Signals in Each Mode Symbol GM D2 TEST2 XSP1 Pin No. 55 12 36 41 Analog color L L L Color separation sample-and-hold pulse output Color separation sample-and-hold pulse output Switching sampleand-hold pulse output Switching sampleand-hold pulse output Delay line clock Delay line clock Burst flag gate pulse output Digital color 1 H L L Halted at High Digital color 2 H L H Color separation sample-and-hold pulse output Color separation sample-and-hold pulse output Switching sampleand-hold pulse output Switching sampleand-hold pulse output Halted at High Halted at Low Burst flag gate pulse output (normally not used) Standby control input Low: Standby High: Normal operation Standby control∗ Low: All circuits halted for standby mode High: Only CL output for standby mode Line identification output XSP2 42 Halted at High XSH1 43 Halted at Low XSH2 XDL1 XDL2 BFG 44 45 46 47 Halted at Low Halted at High Halted at Low Burst flag gate pulse output (normally not used) Standby control input Low: Standby High: Normal operation Standby control∗ Low: All circuits halted for standby mode High: Only CL output for standby mode Line identification output CLP2 49 Clamp pulse output CLP3 50 Clamp pulse output ID 53 Line identification output ∗ When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low. (Mode combinations other than those shown above cannot be used.) Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG, XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4, PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before standby. –6– CXD1257AR 3. Electronic Shutter The operation of the electronic shutter is controlled by the output of XSUB pulse during particular intervals. SMD1 SMD2 L L L H H L H H Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/60 (NTSC), 1/50 (PAL) Low-speed shutter: Shutter speed slower than 1/60 (NTSC), 1/50 (PAL) No shutter operation. PS = High: Parallel input; set by ED0 to ED2, SMD1, and SMD2. PS = Low: Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin. 3-1. Parallel input (PS = H) Shutter Speed Compatibility Chart Mode OFF Flickerless NTSC/PAL X NTSC PAL NTSC PAL X X High-speed shutter X X X X X X X X Low-speed shutter X X X X X SMD1 H L L L L L L L L L L L H H H H H H H H SMD2 H L L H H H H H H H H H L L L L L L L L ED0 X X X H H L H L H L H L H L H L H L H L ED1 X X X H H H L L H H L L H H L L H H L L ED2 X X X H H H H H L L L L H H H H L L L L Shutter speed Shutter off 1/100 (s) 1/120 (s) 1/60 (s) 1/50 (s) 1/125 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) 2FLD 4FLD 6FLD 8FLD 10FLD 12FLD 14FLD 16FLD –7– CXD1257AR 3-2. serial input (PS = L) For serial input (PS = L), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within during the Low period of ED0. –8– CXD1257AR AC Characteristics ED2 ts2 th2 ED1 tW1 tW1 ts1 ts0 ED0 tw0 Symbol Min. ED2 set-up time, activated by the rising edge of ED1 ED2 hold time, activated by the rising edge of ED1 ED1 rising set-up time, activated by the rising edge of ED0 ED0 pulse width ED0 rising set-up time, activated by the rising edge of ED1 ED1 pulse width (serial input) 20ns 20ns 20ns 20ns 20ns 20ns Max. — — — 50µs — — tS2 th2 tS1 tW0 tS0 tW1 3-4. Low-speed shutter timing chart (ED2 : ED1 : ED0 = H : H : H) O VD E O E O E O E O E O E O E XSG1, 2 WEN (ED2 : ED1 : ED0 = H : H : L) XSG1, 2 WEN –9– CXD1257AR 3-5. Shutter speed calculation formula High-speed shutter • NTSC T = [26210 – (1FF16 – L16)] × 63.56 + 32.37µs • PAL T = [31210 – (1FF16 – L16)] × 64 + 32.14µs NTSC Load value 0FA16 0FC16 10016 10816 11816 13716 17616 19616 Shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 Calculated value 1/10424 1/4483 1/2095 1/1014 1/499 1/252 1/125 1/100 Load value 0C816 0CA16 0CE16 0D616 0E616 10516 14316 14916 (L16 = Load value) PAL Shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/120 Calculated value 1/10401 1/4461 1/2083 1/1008 1/496 1/250 1/125 1/120 Low-speed shutter Shutter speed calculation formula N = 2 × (1FF16 – L16) FLD However, "1FF" cannot be used as the load value. Load value 1FE16 1FD16 : : 10116 10016 Shutter speed (FLD) 2 4 : : 508 510 – 10 – Timing Chart (1) NTSC vertical direction FLD BLK/VD HD XSG1 XSG2 ID XV1 – 11 – 490 492 246 1357 491 XV2 XV3 XV4 2 468 1357 492 CCD 491 PBLK CLP1 CLP2 CLP3 CLP4 BFG CXD1257AR Timing Chart (2) PAL vertical direction FLD BLK/VD HD XSG1 XSG2 ID XV1 XV2 – 12 – 582 2 468 13 579 XV3 XV4 2 4 6 8 10 13579 582 CCD 581 PBLK CLP1 CLP2 CLP3 CLP4 BFG CXD1257AR Timing Chart (3) NTSC horizontal direction (63) HD BLK 102 BLK/HD CL MCK H1 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 – 13 – 27 39 21 51 33 50 18 24 29 18 64 56 45 75 63 67 57 45 XDL1 XDL2 XV1 XV2 XV3 XV4 XSUB CLP1 2 94 CLP2 8 CLP3 CLP4 89 94 PBLK ID BFG 94 CXD1257AR Black painted portions of H1 clock indicate the optical black. Timing Chart (4) PAL horizontal direction (64) HD 112 BLK BLK/HD CL MCK H1 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 XDL1 – 14 – 32 44 26 56 38 55 18 24 34 68 72 62 50 23 69 61 XDL2 XV1 XV2 XV3 XV4 XSUB CLP1 2 103 CLP2 8 CLP3 CLP4 80 94 103 PBLK ID BFG 103 CXD1257AR Black painted portions of H1 clock indicate the optical black. Timing Chart of Readout (NTSC/PAL) 1 2 3 4 289 290 [285] [286] Numerals in brackets are for PAL. 1clock:104.76ns (NTSC) 105.73ns (PAL) H1 HD XV1 FIELD ODD XV2 XV3 3 24 24 19 XV4 – 15 – 10 14 XV1 XV2 EVEN XV3 XV4 XSG1 XSG2 Unit: Number of clocks (Common to NTSC and PAL) CXD1257AR Timing Specifications of Resetting Phase and H1/2 Start — High-speed Waveform (NTSC) HD H1/2 start Resetting phase XCK MCK 3 112 93 1 2 CL H1 H2 RG – 16 – XSHP XSHD XSP1 XSP2 XDL1 XDL2 XSH1 XSH2 CXD1257AR Timing Specifications of Resetting Phase and H1/2 Start — High-speed Waveform (PAL) HD H1/2 start Resetting phase XCK MCK 3 100 118 1 2 CL H1 H2 RG – 17 – XSHP XSHD XSP1 XSP2 XDL1 XDL2 XSH1 XSH2 CXD1257AR CXD1257AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 48 49 10.0 ± 0.1 33 32 A 64 1 0.5 ± 0.08 16 + 0.2 1.5 – 0.1 17 (0.22) + 0.08 0.18 – 0.03 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g – 18 – 0.5 ± 0.2 (11.0)