CXD1265R

CXD1265R CCD Camera Timing Generator Description The CXD1265R generates the timing pulses required by the CCD image sensors as well as signal processing circuits. Features • NTSC and PAL compatible • Compatible with digital and analog camera systems • Black-and-white mode compatible (EIA/CCIR compatible) • Electronic shutter function • H-driver • Standby function • Compatible with field/frame accumulation modes∗1, ∗2 ∗1 Characteristics of CCD image sensor are guaranteed by field accumulation. ∗2 Low speed shutter can not be used during frame accumulation mode. Applications CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX038BNA, ICX038BNB, ICX038BLA ICX039BNA, ICX039BNB, ICX039BLA ICX058AK, ICX058AKB, ICX058AL ICX059AK, ICX059AKB, ICX059AL Block Diagram VSS 8 62 28 40 64 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD Vss – 0.5 to +7.0 V • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage VO Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C • Supply voltage VEE –5 to Vss V • Allowable power dissipation PD 500 mW Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.25 • Operating temperature Topr –20 to +75 V °C VDD 24 25 56 VEE 21 15 16 17 18 19 20 60 VD INITIALIZE MODE SET 11 12 13 14 SYNC GEN 59 57 63 64 1 HD INITIALIZE ADR . COUNT 1/2 H – ROM LATCH ADR . COUNT V – ROM LATCH ADR . COUNT 23 ROG – ROM LATCH GATE 36 2 41 42 43 44 45 46 22 37 38 39 23 26 27 3 10 47 48 49 50 51 52 53 54 29 30 31 32 33 34 35 58 55 4 GATE GATE CONTROLLER 61 HTSG HIGH-SPEED PULSE GENERATION CIRCUIT DRIVER DECODER GATE COUNTER SHUT ROM DECODER 5 6 7 9 MICROCOMPUTER Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92611C52-ST CXD1265R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol OSCO OSCI EF ED0 ED1 ED2 SMD1 Vss SMD2 XVCT D1 D2 D3 D4 A5 A4 A3 A0 A1 A2 VEE RG NC VDD VDD H1 H2 Vss XSUB XV2 XV1 XSG1 XV3 XSG2 I/O O I I I I I I — I O I I I I O O O O O O — O — — — O O — O O O O O O Inverter output for oscillation. Inverter input for oscillation. Not used. (With pull-up resistor) Shutter speed setting. Strobe input for serial mode. (With pull-up resistor) Shutter speed setting. Clock input for serial mode. (With pull-up resistor) Shutter speed setting. Data input for serial mode. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) GND Shutter mode setting. (With pull-up resistor) Not used. (Open) Fix at Low in normal operation. (With pull-down resistor) Low: Color, High: Black-and-white. (With pull-down resistor) Low: Field readout, High: Frame readout∗. (With pull-down resistor) Low: NTSC/EIA, High: PAL/CCIR. (With pull-down resistor) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) Not used. (Open) GND Reset gate pulse output. Not used. (Open) Power supply. Power supply for H1 and H2. Clock output for CCD horizontal register drive. Clock output for CCD horizontal register drive. GND for H1 and H2. CCD discharge pulse output. Clock output for CCD vertical register drive. Clock output for CCD vertical register drive. CCD sensor charge readout pulse output. Clock output for CCD vertical register drive. CCD sensor charge readout pulse output. Description 35 Clock output for CCD vertical register drive. XV4 O ∗ Characteristics of CCD image sensor are guaranteed by field accumulation. –2– CXD1265R Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol TEST2 MCK XSHP XSHD Vss XSP1 XSP2 XSH1/ SHP XSH2/ SHD XDL1 XDL2 BFG CLP1 CLP2 CLP3 CLP4 PBLK ID WEN GM VDD CL PS HD VD HTSG TEST XCK CK I/O I O O O — O O O O O O O O I/O I/O O O O O I — O I I I I I O I Description Test input. Set at Low in normal operation. NTSC: 910fH, PAL: 908fH. Clock output. Precharge level sample-and-hold pulse. Data sample-and-hold pulse. GND Color separation sample-and-hold pulse. Halted for black-and-white mode. Color separation sample-and-hold pulse. Halted for black-and-white mode. Switching sample-and-hold pulse/precharge level sample-and-hold pulse (black-and-white mode). Switching sample-and-hold pulse/data sample-and-hold pulse (black-and-white mode). Delay line clock output. Halted for black-and-white mode. Delay line clock output. Halted for black-and-white mode. Pulse output for chroma modulator in encoder. Halted for black-and-white mode. Clamp pulse output. Clamp pulse output. When GM is set at High, standby mode switching input. Clamp pulse output. When GM is set at High, standby mode switching input. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Halted for black-and-white mode. Write enable output for low-speed shutter operation. Low: Analog signal processing, High: Digital signal processing. (With pull-down resistor) Power supply. NTSC/EIA: 910fH, PAL/CCIR: 908fH. Clock output. Switching for electronic shutter speed input method. (With pull-up resistor) Low: Serial input, High: Parallel input. Horizontal synchronizing signal input. Vertical synchronizing signal input. (During Low, 9H for NTSC and 7.5H for PAL) Control input for XSG1 and XSG2. (With pull-up resistor) Low: XSG1, XSG2 halted, High: XSG1, XSG2 generated. Test input. Set at Low in normal operation. (With pull-down resistor) NTSC/EIA: 1820fH, PAL/CCIR: 1816fH. Clock output. NTSC/EIA: 1820fH, PAL/CCIR: 1816fH. Clock input. –3– CXD1265R Electrical Characteristics DC Characteristics Item Supply voltage Input voltage 1 Symbol VDD VIH1 Conditions (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Min. 4.75 0.7VDD 0.3VDD 2.2 0.8 IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –8mA IOL = 8mA IOH = –1mA IOL = 1mA VIN = Vss or VDD VIL = 0V VIH = VDD VDD = 5V ICX058AK in normal operating state 500k 40k 40k 2M 100k 100k 74 VDD/2 VDD/2 5M 250k 250k VDD – 0.5 0.4 VDD – 0.5 0.4 VDD – 0.5 0.4 Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V V V Ω Ω Ω mA (Input pins other than those below) VIL1 Input voltage 2 (Pins 59 and 60) Output voltage 1 VIH2 VIL2 VOH1 (Output pins other than those below) VOL1 Output voltage 2 (Pins 22, 37, 38, 39, 57, and 63) Output voltage 3 (Pins 26 and 27) Output voltage 4 (Pin 1) Feedback resistor Pull-up resistor Pull-down resistor Current consumption VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RFB RPU RPD IDD ∗ Power consumption: 370mW typ., ICX058 load (in normal operating state) I/O Pin Capacitances Item Input pin capacitance Output pin capacitance I/O pin capacitance Symbol CIN COUT CI/O Min. (VDD = VI = 0V, fM = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF –4– CXD1265R Description of Operation 1. Mode Control Symbol GM∗2 PS EF HTSG D1 D2∗2 D3 D4 Pin No. 55 58 3 61 11 12 13 14 L Analog signal processing Serial shutter speed setting H Digital signal processing Parallel shutter speed setting Fix at High in normal operation XSG1, 2 OFF XSG1, 2 ON Fix at Low in normal operation Color Field readout NTSC/EIA Black-and-white Frame readout∗1 PAL/CCIR ∗1 Characteristics of CCD image sensor are guaranteed by field accumulation. ∗2 Operation with GM = High and D2 = High (black-and-white digital signal processing) cannot be used. –5– CXD1265R 2. Changes in I/O Signals in Each Mode Symbol GM D2 TEST2 XSP1 Pin No. 55 12 36 41 Analog color L L L Color separation sample-and-hold pulse output Color separation sample-and-hold pulse output Switching sampleand-hold pulse output Switching sampleand-hold pulse output Delay line clock Delay line clock Burst flag gate pulse output Digital color 1 H L L Halted at High Digital color 2 H L H Color separation sample-and-hold pulse output Color separation sample-and-hold pulse output Switching sampleand-hold pulse output Switching sampleand-hold pulse output Halted at High Halted at Low Burst flag gate pulse output (normally not used) Analog B/W L H L Halted at High XSP2 42 Halted at High Halted at High Precharge level sample-and-hold pulse output Data sample-andhold pulse output Halted at High Halted at Low Halted at Low XSH1 43 Halted at Low XSH2 XDL1 XDL2 BFG 44 45 46 47 Halted at Low Halted at High Halted at Low Burst flag gate pulse output (normally not used) Standby control input Low: Standby High: Normal operation Standby control∗ Low: All circuits halted for standby mode High: Only CL output for standby mode Line identification output CLP2 49 Clamp pulse output CLP3 50 Clamp pulse output Standby control input Low: Standby Clamp pulse output High: Normal operation Standby control∗ Low: All circuits halted for Clamp pulse output standby mode (phase change) High: Only CL output for standby mode Line identification output Halted at Low ID 53 Line identification output ∗ When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low. (Mode combinations other than those shown above cannot be used.) Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG, XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4, PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before standby. –6– CXD1265R 3. Electronic Shutter SMD1 SMD2 L L L H H L H H Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/60 (NTSC), 1/50 (PAL) Low-speed shutter: Shutter speed slower than 1/60 (NTSC), 1/50 (PAL) No shutter operation PS = High: Parallel input; set by ED0 to ED2, SMD1, and SMD2. PS = Low: Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin. 3-1. Parallel input (PS = H) Shutter Speed Compatibility Chart Mode OFF Flickerless NTSC/PAL X NTSC PAL NTSC PAL X X High-speed shutter X X X X X X X X Low-speed shutter∗ X X X X X SMD1 H L L L L L L L L L L L H H H H H H H H SMD2 H L L H H H H H H H H H L L L L L L L L ED0 X X X H H L H L H L H L H L H L H L H L ED1 X X X H H H L L H H L L H H L L H H L L ED2 X X X H H H H H L L L L H H H H L L L L Shutter speed Shutter off 1/100 (S) 1/120 (S) 1/60 (S) 1/50 (S) 1/125 (S) 1/250 (S) 1/500 (S) 1/1000 (S) 1/2000 (S) 1/4000 (S) 1/10000 (S) 2FLD 4FLD 6FLD 8FLD 10FLD 12FLD 14FLD 16FLD ∗ During frame accumulation mode, low speed shutter data set to ED0 to ED2 are all invalid. Shutter speed is 1/30s for NTSC; 1/25s for PAL. –7– CXD1265R 3-2. serial input (PS=L) For serial input (PS = L), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within during the Low period of ED0. –8– CXD1265R AC Characteristics ED2 ts2 th2 ED1 tw1 tw1 ts1 ts0 ED0 tw0 Symbol Min. ED2 set-up time, activated by the rising edge of ED1 ED2 hold time, activated by the rising edge of ED1 ED1 rising set-up time, activated by the rising edge of ED0 ED0 pulse width ED0 rising set-up time, activated by the rising edge of ED1 ED1 pulse width (serial input) 20ns 20ns 20ns 20ns 20ns 20ns Max. — — — 50µs — — tS2 th2 tS1 tW0 tS0 tW1 3-4. Low-speed shutter timing chart (During field accumulation mode) (ED2 : ED1 : ED0 = H : H : H) O VD E O E O E O E O E O E O E XSG1, 2 WEN (ED2 : ED1 : ED0 = H : H : L) XSG1, 2 WEN (During frame accumulation mode) (ED2 : ED1 : ED0 = X : X : X) XSG1, 2 WEN (Fixed at H) –9– CXD1265R 3-5. Shutter speed calculation formula 1. High-speed shutter • NTSC (L16 = load value) T = [26210 – (1FF16 – L16) ] × 63.56µs + 34.9µs • PAL (L16= load value) T = [31210 – (1FF16 – L16) ] × 64.00µs + 35.0µs NTSC Load value 0FA16 0FC16 10016 10816 11816 13716 17616 19616 Shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 Calculated value 1/10156 1/4433 1/2084 1/1012 1/499 1/252 1/125 1/100 Load value 0C816 0CA16 0CE16 0D616 0E616 10516 14316 14916 PAL Shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/120 Calculated value 1/10101 1/4405 1/2070 1/1005 1/495 1/250 1/125 1/120 2. Low-speed shutter (Valid during field accumulation mode only) Shutter speed calculation formula N = 2 × (1FF16 – L16) FLD However, "FF" cannot be used as the load value. Load value 1FE16 1FD16 : : 10116 10016 Shutter speed (FLD) 2 4 : : 508 510 – 10 – Timing Chart (1) NTSC vertical direction FLD BLK/VD HD XSG1 XSG2 ID XV1 XV2 – 11 – 492 494 2 468 13 579 493 XV3 XV4 13 579 2 4 6 8 10 493 CCD 494 PBLK CLP1 CLP2 CLP3 CLP4 CXD1265R However, ID is halted for black-and-white mode Timing Chart (2) PAL vertical direction FLD BLK/VD HD XSG1 XSG2 ID XV1 XV2 – 12 – 582 2 468 13 579 XV3 XV4 13 579 2 4 6 8 10 581 CCD 582 PBLK CLP1 CLP2 CLP3 CLP4 CXD1265R However, ID is halted for black-and-white mode Timing Chart (3) NTSC horizontal direction, analog color 0 120 155 96 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 113 H1 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 XDL1 XDL2 44 62 89 35 53 80 103 140 38 51 75 114 135 140 81 86 140 98 80 71 – 13 – XV1 XV2 XV3 XV4 XSUB CLP1 7 31 CLP2 14 CLP3 CLP4 PBLK 31 ID BFG Black painted portions indicate the optical black output timing of CCD. (GM = L, D2=L, TEST2 = L) CXD1265R Timing Chart (4) NTSC horizontal direction, digital color 1 0 120 155 96 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 113 H1 RG XSHP XSHD XSP1 H XSP2 H XSH1 L XSH2 L XDL1 H XDL2 44 71 62 89 80 53 80 103 98 35 L – 14 – 114 81 86 XV1 XV2 XV3 XV4 XSUB CLP1 7 31 140 CLP2 INPUT PIN 135 140 CLP3 CLP4 PBLK 31 ID BFG 140 Black painted portions indicate the optical black output timing of CCD. (GM = H, D2 = L, TEST2 = L) CXD1265R Timing Chart (5) NTSC horizontal direction, digital color 2 0 120 155 96 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 113 H1 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 XDL1 H XDL2 44 62 89 35 53 80 103 98 80 71 L – 15 – 114 81 86 XV1 XV2 XV3 XV4 XSUB CLP1 7 31 140 CLP2 INPUT PIN 135 140 CLP3 CLP4 PBLK 31 ID BFG 140 Black painted portions indicate the optical black output timing of CCD. (GM = H, D2 = L, TEST2 = H) CXD1265R Timing Chart (6) EIA horizontal direction, analog black-and-white –6 149 0 120 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 113 H1 RG XSHP XSHD XSP1 H XSP2 H XSH1 XSH2 XDL1 H XDL2 44 71 62 89 80 53 80 103 98 35 L – 16 – 38 114 XV1 XV2 XV3 XV4 XSUB CLP1 7 31 140 CLP2 14 CLP3 7 31 135 140 CLP4 PBLK 31 ID L BFG L Black painted portions indicate the optical black output timing of CCD. (GM = L, D2 = H, TEST2 = L) CXD1265R Timing Chart (7) PAL horizontal direction, analog color 0 120 96 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 126 H1 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 XDL1 XDL2 46 79 68 101 90 57 90 112 117 154 38 51 75 128 149 154 81 86 154 35 – 17 – XV1 XV2 XV3 XV4 XSUB CLP1 7 31 CLP2 14 CLP3 CLP4 PBLK 31 ID BFG Black painted portions indicate the optical black output timing of CCD. (GM = L, D2 = L, TEST2 = L) CXD1265R Timing Chart (8) PAL horizontal direction, digital color 1 0 120 96 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 126 H1 RG XSHP XSHD XSP1 H XSP2 H XSH1 L XSH2 L XDL1 H XDL2 46 79 68 101 90 57 90 112 117 35 L – 18 – 81 86 XV1 XV2 XV3 XV4 XSUB CLP1 7 31 154 CLP2 INPUT PIN 128 149 154 CLP3 CLP4 PBLK 31 ID BFG 154 Black painted portions indicate the optical black output timing of CCD. (GM = H, D2 = L, TEST2 = L) CXD1265R Timing Chart (9) PAL horizontal direction, digital color 2 0 120 96 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 170 180 BLK/HD CL 35 126 H1 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 XDL1 H XDL2 46 79 68 101 90 57 90 112 117 35 L – 19 – 81 86 XV1 XV2 XV3 XV4 XSUB CLP1 7 31 154 CLP2 INPUT PIN 128 149 154 CLP3 CLP4 PBLK 31 ID BFG 154 Black painted portions indicate the optical black output timing of CCD. (GM = H, D2 = L, TEST2 = H) CXD1265R Timing Chart (10) CCIR horizontal direction, analog black-and-white –6 0 120 10 20 30 40 50 60 70 80 90 100 110 130 140 150 160 164 170 180 BLK/HD CL 35 126 H1 RG XSHP XSHD XSP1 H XSP2 H XSH1 XSH2 XDL1 H XDL2 46 79 68 101 90 57 90 112 117 35 L – 20 – 38 XV1 XV2 XV3 XV4 XSUB CLP1 7 31 154 CLP2 14 CLP3 7 31 128 149 154 CLP4 PBLK 31 ID L BFG L Black painted portions indicate the optical black output timing of CCD. (GM = L, D2 = H, TEST2 = L) CXD1265R 4-1. Timing Chart of Readout (NTSC/EIA) Field readout HD XV1 ODD XV2 XV3 XV4 578 36 36 36 3 XV1 XV2 EVEN XV3 XV4 XSG1 – 21 – 22 36 3 36 33 3 36 XSG2 Frame readout XV1 ODD XV2 XV3 XV4 XV1 EVEN XV2 XV3 XV4 CXD1265R Unit: Number of clocks (1ck = 69.84ns) 4-2. Timing Chart of Readout (PAL/CCIR) Field readout HD XV1 ODD XV2 XV3 XV4 589 36 36 36 3 XV1 XV2 EVEN XV3 XV4 XSG1 – 22 – 22 36 3 36 33 3 36 XSG2 Frame readout XV1 ODD XV2 XV3 XV4 XV1 XV2 EVEN XV3 XV4 CXD1265R Unit: Number of clocks (1ck = 70.48ns) CXD1265R 5. High-speed Clock Timing Chart CK CL H1 H2 RG XSHP XSHD XSP1 XSP2 XSH1 XSH2 For color mode XSH1 (SHP) XSH2 For black-and-white mode (SHD) XDL1 XDL2 MCK ∗ For black and white mode, XSP1, XSP2, XDL1, and XDL2 are halted. – 23 – CXD1265R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 48 49 10.0 ± 0.1 33 32 A 64 1 0.5 ± 0.08 16 + 0.2 1.5 – 0.1 17 (0.22) + 0.08 0.18 – 0.03 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 ∗QFP064-P-1010-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.3g – 24 – 0.5 ± 0.2 (11.0)