CXD1267AN

CXD1267AN CCD Vertical Clock Driver Description The CXD1267AN is a vertical clock driver for CCD image sensors. This IC is the successor of the CXD1250N with attractive features. Power consumption is reduced approximately 30% for the CXD1267AN version. Features 1) Substrate voltage (Vsub) generator is built-in. • Variable Vsub in the range of 4.0V to 18.5V. • Reduction of peripheral parts saves space. 2) Only two power supplies (+15V and –8.5V) are needed. 3) 3.3V clock interface is acceptable. 4) 20-pin SSOP package is used. 5) Low power consumption 90mW (CXD1267N) 62mW (CXD1267AN) approximately 30% reduction 20 pin SSOP (Plastic) Appllications CCD cameras Structure CMOS Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VL 0 to –10 • Supply voltage VH VL – 0.3 to 2VL + 35 • Supply voltage VM VL – 0.3 to 3.0 • Input voltage VI VL – 0.3 to VH + 0.3 • Output voltage (V2, V4) MVφ VL – 0.3 to VM + 0.3 • Output voltage (V1, V3) HVφ VL – 0.3 to VH + 0.3 • Output voltage (VSHT) HHVφ VL – 0.3 to VH + 0.3 • Operational amplifier output current IDCOUT ±5 • Operating temperature Topr –25 to +85 • Storage temperature Tstg –40 to +125 Recommended Operating Conditions • Supply voltage VH • Supply voltage VM • Supply voltage VL • Input voltage (except for pin 3) VI • Operational amplifier input voltage VIOP • Operating temperature Topr V V V V V V V mA °C °C 14.5 to 15.5 0 –6.0 to –9.0 0 to 6.0 1.0 to 4.5 –20 to +75 V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94X38-PK CXD1267AN Block Diagram and Pin Configuration (Top View) 1 CPP3 Charge Pump CPP2 19 CPP1 20 VH 2 3 4 5 6 7 8 DCIN XSHT XV2 XV1 XSG1 XV3 XSG2 DCOUT VSHT 18 17 VL 16 Vφ2 15 Vφ1 14 VM 13 Vφ3 12 Vφ4 11 9 10 XV4 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol CPP3 VH DCIN XSHT XV2 XV1 XSG1 XV3 XSG2 XV4 Vφ4 Vφ3 VM Vφ1 Vφ2 VL VSHT DCOUT CPP2 CPP1 I/O O — I I I I I I I I O O — O O — O O — — Charge pump Power supply (15V) Operational amplifier input Output control (VSHT) Output control (Vφ2) Output control (Vφ1) Output control (Vφ1) Output control (Vφ3) Output control (Vφ3) Output control (Vφ4) High-voltage output (2 levels: VM, VL) High-voltage output (3 levels: VH, VM, VL) GND High-voltage output (3 levels: VH, VM, VL) High-voltage output (2 levels: VM, VL) Power supply (–8.5V) High-voltage output (2 levels: VH, VL) Operational amplifier output Charge pump Charge pump Description –2– CXD1267AN Truth Table Input XV1, 3 L H L H X X X X XSG1, 2 L L H H X X X X XV2, 4 X X X X L H X X XSHT X X X X X X L H Vφ1, 3 VH Z VM VL X X X X Output Vφ2, 4 X X X X VM VL X X VSHT X X X X X X VH VL X: Don't care Z: High impedance Electrical Characteristics DC Characteristics Item High level input voltage Low level input voltage High level output voltage Middle level output voltage Middle level output voltage Low level output voltage Charge pump output voltage Input current Operating supply current Operating supply current Output current Output current Output current Output current Output current Output current Operational amplifier gain Gain error (Unless otherwise specified, Ta = 25°C, VH = 15V, VM = GND, VL = –8.5V) Symbol VIH VIL VOH VOM1 VOM2 VOL VCPP3 II IH IL IOL IOM1 IOM2 IOH IOSL IOSH G ∆G IO = –20µA IO = 20µA IO = –20µA IO = 20µA –1 ≤ ICPP3 ≤ 0mA IDCOUT = 0mA, Ta = –20 to 75°C VIOP = 4.5V VI = VL to 5V ∗1 ∗1 Vφ1 to 4 = –8.0V Vφ1 to 4 = –0.5V Vφ1, 3 = 0.5V Vφ1, 3 = 14.5V VSHT = –8.0V VSHT = 14.5V IDCOUT = –200/+100µA Ta = –20 to 75°C∗2 IDCOUT = –200/+100µA VIOP = 1.0 to 4.5V Condition Min. 2.3 — 14.9 — –0.1 — 20 –1.0 — –6.0 25 — 9 — 12 — — –3 Typ. — — 15.0 0.0 0.0 –8.5 — 0.0 1.4 –5.0 — — — — — — × 4.40 — Max. — 1.3 — 0.1 — –8.4 — 1.0 2.0 — — –10 — –12 — –7 — +3 % Unit V V V V V V V µA mA mA mA mA mA mA mA mA ∗1 See Measurement Circuit. Shutter speed: 1/10000. ∗2 See Operational Amplifier Gain Characteristic. Note) Current directions: + indicates the direction flowing to IC; – indicates the direction flowing from IC –3– CXD1267AN Switching Characteristics Item Propagation delay time Propagation delay time Propagation delay time Propagation delay time Propagation delay time Propagation delay time Rise time Rise time Rise time Fall time Fall time Fall time Charge pump boosting time Output noise voltage Output noise voltage Output noise voltage Output noise voltage Symbol TPLM TPMH TPLH TPML TPHM TPHL TTLM TTMH TTLH TTML TTHM TTHL TC VCLH VCLL VCMH VCML ∗1 ∗1 ∗1 ∗1 ∗1 ∗1 VL → VM∗1 VM → VH∗1 VL → VH∗1 VM → VL∗1 VH → VM∗1 VH → VL∗1 ∗2 ∗3 ∗3 ∗3 ∗3 Conditions Min. 30 30 30 50 50 50 360 330 30 180 330 24 — — — — — (VH = 15V, VM = GND, VL = –8.5V) Typ. 50 50 50 80 80 80 600 550 50 300 550 40 — — — — — Max. 75 75 75 120 120 120 900 770 75 500 770 60 10 0.5 0.5 0.5 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ms V V V V ∗1 See Response of Voltage Pulse. ∗2 CP1 = 0.1µF, CP2 = 0.1µF, VCPP3 = 20V; boosting time after all power supplies rose. ∗3 See Noise on a Waveform. Note) Each item is evaluated by Measurement Circuit. Notes on Operation (See Application Circuit.) 1. Be sure to protect against static electricity because this IC is MOS structure. 2. A bypass capacitor is connected between each power supply (VH, VL) and GND. 3. To prevent latch-up, use a capacitor of 0.1µF (CP1, CP2) for charge pump. Insert a silicon diode (D2) between CPP3 and CPP1. 4. In order to protect CCD image sensor, pre-clamp is requested prior to clamp by DCOUT. –4– CXD1267AN Measurement Circuit R1 C1 C2 C2 C1 C2 C2 500pF R1 C1 R2 –8.5V 0.1µF 20 19 18 17 16 15 14 0V R1 C1 R1 R1; 27Ω R2; 5Ω C1; 1500pF C2; 3300pF 13 12 11 CXD1267AN 1 0.1µF 2 3 4 5 6 7 8 9 10 15V 4.5V Timing generator (CXD1156Q) Operational Amplifier Gain Characteristics [V] 25.0 Ta = –20 to +75°C IDCOUT = 0µA At VH = 15V, VL = –8.5V At VH = 14.5V, VL = –6.0V Output voltage 2.5/div 0 0.5/div Input voltage 5.0 [V] Note) Operating amplifier maximum output voltage is restricted as shown in the formula below depending on supply voltage setting of VH and VL. Maximum output voltage VDCOUT (max) ≈ VH + | VL | – 0.8V For instance, when VH = 14.5V and VL = –6.0V, output voltage is saturated at approximately 19.7V as shown above figure. –5– CXD1267AN Response of Voltage Pulse VI (5V) XV1 to 4 GND VI (5V) XSG1, 2 GND TPMH VH TTMH TTLM Vφ1, 3 VM TPLM 90% 10% TPML 90% TTML 50% TPHM TTHM 50% VL 10% TTLM TPLM TPML 90% 10% TTML VM Vφ2, 4 VL VI (5V) XSHT GND TPLH VH TTLH VSHT 50% TTHL TPHL 90% VL 10% Noise on a Waveform VCMH VCML VM VCLH VCLL VL –6– CXD1267AN Application Circuit 15V 5V 47kΩ 0kΩ CP1 0.1µF D1 1 0.1µF 0.1µF 3 XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 4 5 6 7 8 9 DCIN XSHT XV2 XV1 XSG1 XV3 XSG2 2 CPP3 VH D2 CPP1 20 CPP2 19 DCOUT 18 C1 VSHT 17 1µF/35V VL 16 Vφ2 15 Vφ1 14 VM 13 Vφ3 12 Vφ4 11 Vφ3 Vφ4 –8.5V 0.1µF 0.1µF R1 100kΩ R2 1MΩ Vφ2 Vφ1 0.1µF C2 SUB CP2 0.1µF D3 D4 10 XV4 CXD1267AN CCD ∗ A peripheral circuit can be simplified by CCD image sensor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Note with power-on sequence To protect CCD image sensor, rise two power supplies as follows. 15V t1 20% 0V 20% t2 t2 ≥ t1 –8.5V –7– CXD1267AN Package Outline Unit: mm 20PIN SSOP (Plastic) ∗6.5 ± 0.1 + 0.1 0.15 – 0.05 20 11 0.10 ∗4.4 ± 0.1 6.4 ± 0.2 0.1 ± 0.1 1 + 0.1 0.22 – 0.05 0.65 10 0.10 M 0° to 10° 1.15 ± 0.1 0.575 MAX 1.45 MAX NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L071 SSOP020-P-0044-AN LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING Cu ALLOY 0.1g –8– 0.5 ± 0.2