CXD1268

CXD1268M CCD Vertical Clock Driver Description The CXD1268M is a clock driver for CCD vertical register drive. Features • On-chip 4-channel driver. (Binary driver × 2, and trinary driver × 2) • Low output ON resistance provides optimal drive for large load capacity CCD. Applications CCD cameras Structure CMOS Absolute Maximum Ratings (GND = 0V, Ta = 25°C) • Supply voltage VH VL to VL + 25 V ∗1 • Supply voltage VM VL to VL + 17 V • Supply voltage VDD GND to GND + 7 V • Supply voltage VL GND – 10 to GND V • Input voltage VI –0.5 to VDD + 0.5 V • Input/output clamp diode current IIC, IOC –10 to +10 mA • Maximum DC load current IODC –3 to +3 mA • Maximum load capacity CL to 30,000 pF/pin • Allowable power dissipation PD to 200 mW • Storage temperature Tstg –60 to +150 °C ∗1 Use VM at less than VDD. Recommended Operating Conditions • Supply voltage VH VM + 6.5 to VM + 15.5 • Supply voltage VL VM – 10.0 to VM – 7.0 • Supply voltage VM 0.0 to 4.0 • Supply voltage VDD 4.75 to 5.25 ∗2 • High level input voltage VIH 3.5 to VDD • Low level input voltage VIL∗2 0.0 to 1.0 • Operating temperature Topr –10 to +60 ∗2 VDD = 5V 20 pin SOP (Plastic) V V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96635-PS CXD1268M Block Diagram VDD 6 SG Input Gate Level Converter Level Converter SG Input Gate Level Converter Level Converter Level Converter VM1 3 VH 16 XSG1 9 Trinary Driver 5 Vφ1 XV1 8 XSG2 12 Trinary Driver 18 Vφ3 XV3 13 XV2 10 Binary Driver 2 Vφ2 XV4 11 Level Converter Binary Driver 19 Vφ4 15 GND 20 VM2 1 VL Pin Configuration (Top View) VL Vφ2 VM1 NC Vφ1 VDD NC XV1 XSG1 1 2 3 4 5 6 7 8 9 20 VM2 19 Vφ4 18 Vφ3 17 16 15 14 13 12 NC VH GND NC XV3 XSG2 XV2 10 11 XV4 –2– CXD1268M Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol VL Vφ2 VM1 NC Vφ1 VDD NC XV1 XSG1 XV2 XV4 XSG2 XV3 NC GND VH NC Vφ3 Vφ4 VM2 O O — High-voltage output (3 levels: VH, VM1, VL) High-voltage output (2 levels: VM2, VL) Middle level power supply for binary — — GND High level power supply for trinary I I I I I I Output control (Vφ1) Output control (Vφ1) Output control (Vφ2) Output control (Vφ4) Output control (Vφ3) Output control (Vφ3) O — High-voltage output (3 levels: VH, VM1, VL) Input section power supply I/O — O — Description Low level power supply High-voltage output (2 levels: VM2, VL) Middle level power supply for trinary Truth Table Input XV1, XV3 H H L L X X XSG1, XSG2 L H L H X X XV2, XV4 X X X X L H Vφ1, Vφ3 VL VL VH VM1 X X X: Don’t care Output Vφ2, Vφ4 X X X X VM2 VL –3– CXD1268M Electrical Characteristics 1. DC Characteristics Item “H” level output voltage “M” level output voltage “L” level output voltage Input current “H” level output ON resistance “M” level output ON resistance “L” level output ON resistance Static current consumption (Unless otherwise specified, VH = 14.5V, VM = 1V, VDD = 5V, GND = 0V, VL = –6V, VIL = GND, VIH = VDD, Ta = –10 to +60°C) Symbol VφH VφM VφL II Ron (H) Ron (M) Ron (L) IDD + IH + IM IφH = –50mA IφM = –50mA IφL = 50mA 18 18 18 10–4 Conditions IφH = –1mA IφM = –1mA IφL = 1mA Min. VH – 0.1 VM – 0.1 VL Typ. Max. VH VM VL + 0.1 1.0 30 30 30 100 Unit V V V µA Ω Ω Ω µA 2. AC Characteristics Item Propagation delay time L → M, M → L Propagation delay time M → H, H → M Rise time L → M Fall time M → L Rise time M → H Fall time H → M Symbol Conditions Waveform diagram (1), no load Waveform diagram (2), no load Refer to waveform diagram (1), output load circuit diagram Refer to waveform diagram (2), output load circuit diagram Min. Typ. 100 200 Max. 200 400 Unit ns ns tPLH, tPHL tPLH, tPHL tTLH, tTHL 200 300 ns tTLH, tTHL Idyn (IDD + IH + IM + IL) 200 300 ns 6.0 Refer to input pulse timing diagram, output load circuit diagram –5.0 0.02 3.8 –3.8 10.0 0.2 5.0 mA mA mA mA Operating current consumption IDD IH + IM IL –4– CXD1268M Waveform Diagram (1) tr tf VDD tr = tf = 20ns GND tPHL 90% 50% 10% tTHL tTLH VφL tPLH VφM input XV1 to XV4 10% 90% 50% output Vφ1 to Vφ4 Waveform Diagram (2) tr tf VDD tr = tf = 20ns 10% tPLH 90% output Vφ1, Vφ3 50% 10% tTLH tTHL VφM tPHL VφH GND input XSG1, XSG2 90% 50% Output Load Circuit Diagram 1600pF 1000pF Vφ1 2000pF Vφ4 3000pF 1000pF Vφ2 2000pF 3000pF Vφ3 1600pF –5– CXD1268M Input Pulse Timing Diagram 63.5µs 2µs 127µs XV1 XV2 XV3 XV4 XSG1, XSG2 5µs 15.7ms Application Circuit CCD image sensor Vφ1 Vφ2 –7.5V 5V 1 VL 2 Vφ2 3 VM1 4 NC 5 Vφ1 VM2 20 Vφ4 19 Vφ3 18 NC 17 VH 16 GND 15 NC 14 XV3 13 XSG2 12 XV4 11 15V Vφ4 Vφ3 timing generator XV1 XSG XV2 6 VDD 7 NC 8 XV1 9 XSG1 10 XV2 XV4 XV3 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes on Operation 1. When applying power, be sure to apply VH before VDD and VM. 2. XSG1 (Pin 9) and XSG2 (Pin 12) can be input separately, although they are also common input. –6– CXD1268M Package Outline Unit: mm 20PIN SOP (PLASTIC) 1.8MAX 13.0MAX 20 11 1.55 1.1 0.1 ± 0.1 7.7 ± 0.3 5.6 1 + 0.1 0.4 – 0.05 0.12 M 1.27 10 0.78MAX + 0.1 0.2 – 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-20P-L071 SOP020-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.3g –7– 0.6 ± 0.2