CXD1812Q

CXD1812Q/R ATAPI I/F CD-ROM DECODER For the availability of this product, please contact the sales office. Description The CXD1812Q/R is a CD-ROM decoder LSI with a built-in ATAPI I/F. Features • Compatible with CD-ROM, CD-I and CD-ROM XA formats • Real time error correction • Automatic multi-block transfer function • Readable Subcode-Q data by byte from the Sub CPU • Capable of transferring up to double speed playback and Mode2 when the 33.8688 MHz clock is used Transfer in Mode3 is possible when the decoder is OFF (The transfer speed depends on playback speed and clock frequency.) • Supports PIO/single-word DMA/multiword DMA data transfer mode • IORDY support available • Automatic reception of PACKET commands Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD –0.5 to +7.0 • Input voltage VI –0.5 to VDD +0.5 • Output voltage VO –0.5 to VDD +0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 (+5.0 typ.) • Operating temperature Topr –20 to +75 CXD1812Q 100 pin QFP (Plastic) CXD1812R 100 pin LQFP (Plastic) V V V °C °C V °C Applications CD-ROM drives Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95233-ST Block Diagram -1 CXD1812Q (QFP) VDD XRAS XCAS MA0 to 9 XMWR MDB0 to 7 XRST 95 26, 27, 30 to 33, 35 to 38 39 41 42 43 to 46, 48 to 51 3, 28, 53, 78 DMA FIFO ADDRESS GEN ATAPI REGISTERs DMA SEQUENCER GND 4 15 22 29 34 40 47 54 65 73 79 84 90 PRIORITY RESOLVER 12 bytes PACKET FIFO 69 to HDB0 to F 72 74 to 77 80 to 83 85 to 88 C2PO 100 DESCRAMBLER 55 HCS0, 1 56 BCLK 1 SYNC CONTROL 57 58 HA0 to 2 60 66 XHRD 67 XHWR HOST I/F Subcode S/P 63 XHAC 68 HDRQ 62 HINT 61 XS16 64 REDY CLOCK GENERATOR subCPU I/F 52 DASP 59 XPDI 89 HRST 91 92 94 93 17 to 21, 23 to 25 7 9 8 6 10 to 14, 16 XCS XRD XTL2 XTL1 HCLK MCLK XWR XINT D0 to 7 A0 to 5 –2– MAIN DATA ERROR CORECTION MDAT 2 LRCK 5 CD•DSP I/F EXCK 96 SBIN 97 SCOR 98 WFCK 99 CXD1812Q/R Block Diagram -2 CXD1812R (LQFP) XRAS XCAS VDD MA0 to 9 XMWR MDB0 to 7 XRST 93 24, 25, 28 to 31, 33 to 36 37 39 1, 26, 51, 76 40 41 to 44, 46 to 49 DMA FIFO ADDRESS GEN ATAPI REGISTERs DMA SEQUENCER GND 2 13 20 27 32 38 45 52 63 71 77 82 88 PRIORITY RESOLVER 12 bytes PACKET FIFO 67 to HDB0 to F 70 72 to 75 78 to 81 83 to 86 C2PO 98 DESCRAMBLER 53 HCS0, 1 54 55 56 HA0 to 2 58 64 XHRD 65 XHWR HOST I/F 61 XHAC 66 HDRQ BCLK 99 SYNC CONTROL XCS XRD XTL2 XTL1 HCLK MCLK D0 to 7 XWR XINT A0 to 5 –3– MAIN DATA ERROR CORECTION Subcode S/P CLOCK GENERATOR subCPU I/F 89 90 92 91 15 to 19, 21 to 23 5 7 6 4 8 to 12, 14 MDAT 100 LRCK 3 CD•DSP I/F EXCK 94 SBIN 95 SCOR 96 WFCK 97 60 HINT 59 XS16 62 REDY 50 DASP 57 XPDI 87 HRST CXD1812Q/R CXD1812Q/R Pin Description Pin No. QFP LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 BCLK MDAT VDD GND LRCK XINT XCS XWR XRD A5 A4 A3 A2 A1 GND A0 D7 D6 D5 D4 D3 GND D2 D1 D0 MA0 MA1 VDD GND MA2 MA3 MA4 MA5 GND MA6 MA7 I I — — I O I I I I I I I I — I I/O I/O I/O I/O I/O — I/O I/O I/O O O — — O O O O — O O Bit clock signal from CD DSP Data signal from CD DSP Power supply Ground LR clock signal from CD DSP Interrupt request signal to CPU Chip select negative logic signal from CPU Strobe negative logic signal for writing data from CPU Strobe negative logic signal for reading data from CPU CPU address (MSB) CPU address CPU address CPU address CPU address Ground CPU address (LSB) CPU data bus (MSB) CPU data bus CPU data bus CPU data bus CPU data bus Ground CPU data bus CPU data bus CPU data bus (LSB) DRAM address (LSB) DRAM address Power supply Ground DRAM address DRAM address DRAM address DRAM address Ground DRAM address DRAM address –4– Symbol I/O Description CXD1812Q/R Pin No. QFP LQFP 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Symbol MA8 MA9 XRAS GND XCAS XMWR MDB0 MDB1 MDB2 MDB3 GND MDB4 MDB5 MDB6 MDB7 DASP VDD GND HCS1 HCS0 HA2 HA0 XPDI HA1 XS16 HINT XHAC REDY GND XHRD XHWR HDRQ HDBF HDB0 HDBE HDB1 I/O O O O — O O I/O I/O I/O I/O — I/O I/O I/O I/O I/O — — I I I I I/O I O O I O — I I O I/O I/O I/O I/O DRAM address DRAM address (MSB) Description DRAM row address strobe negative logic signal Ground DRAM column address strobe negative logic signal DRAM write enable negative logic signal DRAM data bus (LSB) DRAM data bus DRAM data bus DRAM data bus Ground DRAM data bus DRAM data bus DRAM data bus DRAM data bus (MSB) Drive active/slave present negative logic signal; open drain output Power supply Ground Chip select negative logic signal from host Chip select negative logic signal from host Host address (MSB) Host address (LSB) Passed diagnostics negative logic signal; open drain output Host address 16-bit I/O port select negative logic signal; open drain output Interrupt request positive logic signal to host DMA acknowledge negative logic signal from host I/O channel ready positive logic signal; open drain output Ground Strobe negative logic signal for reading data from host Strobe negative logic signal for writing data from host DMA request positive logic signal to host Host data bus (MSB) Host data bus (LSB) Host data bus Host data bus –5– CXD1812Q/R Pin NO. QFP LQFP 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Symbol GND HDBD HDB2 HDBC HDB3 VDD GND HDBB HDB4 HDBA HDB5 GND HDB9 HDB6 HDB8 HDB7 HRST GND XTL2 XTL1 MCLK HCLK XRST EXCK SBIN SCOR WFCK C2PO I/O — I/O I/O I/O I/O — — I/O I/O I/O I/O — I/O I/O I/O I/O I — O I O O I O I I I I Ground Host data bus Host data bus Host data bus Host data bus Power supply Ground Host data bus Host data bus Host data bus Host data bus Ground Host data bus Host data bus Host data bus Host data bus Description Chip reset negative logic signal from host Ground Crystal oscillation circuit output Crystal oscillation circuit input Master clock (XTL1) output Clock output with 1/2 the frequency of XTL1 Chip reset negative logic signal Subcode data read clock signal to CD DSP Subcode data serial input signal from CD DSP Subcode sync positive logic signal from CD DSP Write frame clock signal from CD DSP C2 pointer positive logic signal from CD DSP –6– CXD1812Q/R Electrical Characteristics 1. DC Characteristics Item High level input voltage (1) Low level input voltage (1) High level input voltage (2) Low level input voltage (2) High level input voltage (3) Low level input voltage (3) TTL Schmitt hysteresis High level input voltage (4) Low level input voltage (4) CMOS Schmitt hysteresis High level output voltage (6) Low level output voltage (6) High level output voltage (7) Low level output voltage (7) High level output voltage (8) Low level output voltage (8) Input leakage current Input leakage current∗1 Input current of pull-up input Input current of pull-up input∗1 Output leakage current (9) (10) Oscillation cell logic threshold value Oscillation cell high level input voltage Oscillation cell low level input voltage Oscillation cell feedback resistance Oscillation cell high level output voltage Oscillation cell low level output voltage ∗1 Bidirectional pin Symbol VIH1 VIL1 VIH2 VIL2 Vt1+ Vt1– Vt1+ – Vt1– Vt2+ Vt2– Vt2+ – Vt2– VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 IIL1 IIL2 IIL3 IIL4 IIZ LVth VIH VIL RFB VOH VOL VIN = VSS or VDD IOH = –12mA IOL = 12mA 250k 0.5VDD 0.5VDD 1M 0.7VDD 0.3VDD 2.5M VIN = 0V VIN = 0V High-impedance state IOH1 = –2mA IOL1 = 4mA IOH2 = –6mA IOL2 = 12mA IOH3 = –6mA IOL3 = 4mA –10 –40 –40 –90 –40 0.5VDD –100 –200 VDD – 0.8 0.4 10 40 –240 –440 40 VDD – 0.8 0.4 VDD – 0.8 0.4 0.6 0.8VDD 0.2VDD 0.4 2.2 0.8 0.7VDD 0.3VDD (VDD = 5V ±10%, VSS = 0V, Topr = –20 to +75°C) Conditions Min. 2.2 0.8 Typ. Max. Unit V V V V V V V V V V V V V V V V µA µA µA µA µA V V V Ω V V –7– CXD1812Q/R 1-1. Categories of input pins (1) TTL input level pin: D0 to D7, MDB0 to MDB7, HDB0 to HDBF, DASP, XPDI (2) CMOS input level pin: MDAT, LRCK, SBIN, SCOR, WFCK, C2PO (3) TTL Schmitt input level pin: XCS, XWR, XRD, A0 to A5, HA0 to HA2, XHAC, XHRD, XHWR, HCS0 to HCS1, HRST (4) CMOS Schmitt input level pin: BCLK, XRST (5) Input pin with pull-up resistor: D0 to D7, MDB0 to MDB7, HCS0 to HCS1, HRST 1-2. Categories of output pins (6) Normal output pin: D0 to D7, MDB0 to MDB7, XINT, MA0 to MA9, XMWR, MCLK, HCLK, EXCK (7) Powered output pin: HINT, HDRQ, HDB0 to HDBF, DASP, XPDI, XS16, REDY (8) Proportional output pin: XRAS, XCAS (9) Tristate output pin: XINT, HINT, HDRQ (10) Open drain output pin: DASP, XPDI, XS16, REDY 1-3. Bidirectional pins D0 to D7, MDB0 to MDB7, HDB0 to HDBF, DASP, XPDI 1-4. Oscillation cell Input: XTL1 Output: XTL2 1-5. I/O Capacitance Item Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CI/O Min. (VDD = VI = 0V, f = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF –8– CXD1812Q/R 2. AC Characteristics (VDD = 5V ±10%, VSS = 0V, Topr = –20 to +75°C, Output Load = 50pF) 2-1. CPU Interface (1) Read A0 to A5 XCS Trdw XRD Tas Tdd D0 to D7 Tdf Tah (2) Write A0 to A5 XCS Twwr XWR Tas Tah D0 to D7 Tds Tdh Item Address setup time (for XCS & XRD/XWR ↓) Address hold time (for XCS & XRD/XWR ↑) XRD pulse width Data delay time (for XCS & XRD ↓) Data float time (for XCS & XRD ↑) XWR pulse width Address setup time (for XCS & XWR ↑) Address hold time (for XCS & XWR ↑) Symbol Tas Tah Trdw Tdd Tdf Twwr Tds Tdh Min. 0 0 43 Typ. Max. Unit ns ns ns 43 1 21 7 0 ns ns ns ns ns –9– CXD1812Q/R 2-2. DRAM Interface (1) Read Tras XRAS Trcd XCAS Tasr row col Tasc col col row Tcas Tpc Trp MA0 to MA9 Trah MDB0 to 7 XMWR Tids Tidh Tcah high (2) Write Tras XRAS Trcd XCAS Tasr MA0 to MA9 row col col Tasc col Tcah row Tcas Tpc Trp Trah MDB0 to 7 Tdos Tdof XMWR (Tw = 1/f) Item RAS pulse width RAS precharge width RAS – CAS delay time CAS pulse width Page mode cycle time Row address setup time (for RAS ↓) Row address hold time (for RAS ↓) Column address setup time (for CAS ↓) Column address hold time (for CAS ↓) Input data setup time (for CAS ↑) Input data hold time (for CAS ↑) Data output setup time (for CAS ↓) Data output float time (for CAS ↓) – 10 – Symbol Tras Trp Trcd Tcas Tpc Tasr Trah Tasc Tcah Tids Tidh Tdos Tdof Tw – 7 Tw Tw – 14 Tw + 2 7 0 0 Tw + 3 Min. 3Tw 2Tw 2Tw Tw 2Tw Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns CXD1812Q/R 2-3. HOST Interface (1) PIO HCS0, 1 HA0 to 2 Txsl XS16 Trww XHRD Tas Tah XHWR Tdd HDB0 to F Tdf Tds Tdh Tas Trww Tah REDY Trel Trel Item Address setup time (for XHRD/XHWR ↓) Address hold time (for XHRD/XHWR ↑) XHRD/XHWR pulse width Data delay time (for XHRD ↓) Data float time (for XHRD ↑) Data setup time (for XHWR ↑) Data hold time (for XHWR ↑) XS16 fall time (for Address valid) REDY fall time (for XHRD/XHWR ↓) Symbol Tas Tah Trww Tdd Tdf Tds Tdh Txsl Trel Min. 20 5 50 Typ. Max. Unit ns ns ns 26 5 20 5 8 14 21 ns ns ns ns ns ns – 11 – CXD1812Q/R (2) Single-word DMA HDRQ Trql XHAC Tacs XHRD/ XHWR Tdd HDB0 to F (READ) Tds HDB0 to F (WRITE) Tdh Tdf Trww Tach (3) Multiword DMA HDRQ Trql XHAC Tacs XHRD/ XHWR Tdd HDB0 to F (READ) HDB0 to F (WRITE) Trww Thpw Trww Tach Tdf Tdd Tdf Tds Tdh Tds Tdh (Tw = 1/f) Item HDRQ fall time (for XHAC/XHRD/XHWR ↓) XHRD/XHWR Low pulse width Data delay time (for XHRD ↓) Data float time (for XHRD ↑) Data setup time (for XHWR ↑) Data hold time (for XHWR ↑) XHAC setup time (for XHRD/XHWR ↓) XHAC hold time (for XHRD/XHWR ↑) XHRD/XHWR high pulse width Symbol Trql Trww Tdd Tdf Tds Tdh Tacs Tach Thpw 5 20 5 0 0 25 50 26 19 Min. Typ. Max. Tw +11 Unit ns ns ns ns ns ns ns ns ns – 12 – CXD1812Q/R 2-4. CD DSP Interface (1) BCKRED = "H" Tbck BCLK Tbck MDAT Tsb1 LRCK C2PO Tsb2 Thb2 Thb1 (2) BCKRED = "L" Tbck BCLK Tbck MDAT Tsb1 LRCK C2PO Tsb2 Thb2 Thb1 Item BCLK frequency BCLK pulse width MDAT setup time (for BCLK) MDAT hold time (for BCLK) LRCK, C2PO setup time (for BCLK) LRCK, C2PO hold time (for BCLK) Symbol Fbck Tbck Tsb1 Thb1 Tsb2 Thb2 Min. Typ. Max. 20 Unit MHz ns ns ns ns ns 25 12 12 12 12 – 13 – CXD1812Q/R 2-5. Subcode Interface Subcode Frame SF97 SF0 SF1 SF2 SF3 WFCK SCOR SBIN Twed EXCK Teck EXCK Teck SBIN Tds Tdh (Tw = 1/f) Item WFCK – EXCK delay time EXCK pulse width SBIN setup time (for EXCK ↑) SBIN hold time (for EXCK ↑) Symbol Twed Teck Tds Tdh Min. 2aTw 1/2aTw – 2 12 12 Typ. Max. 3aTw Unit ns ns ns ns a = 48: When EXCKSL (CONFIG0 register bit 3) = High a = 32: When EXCKSL (CONFIG0 register bit 3) = Low – 14 – CXD1812Q/R 2-6. XTL1 and XTL2 Pins (1) When using self-excited oscillation Item Oscillation frequency (2) When inputting a pulse to the XTL1 pin f Symbol Min. Typ. 33.8688 Max. 40 Unit MHz Tw Twhx Twlx Vihx VDD/2 Vilx Item High level pulse width Low level pulse width Pulse cycle Symbol Twhx Twlx Tw Min. 10 10 Typ. Max. Unit ns ns 29 ns – 15 – CXD1812Q/R Description of Functions 1. Pin Description The pin description by function is given below. 1-1. CD player interface (8 pins) This enables direct connection with the Sony's digital signal processor LSI for CD players. Digital signal processor LSI for CD applications are hereafter called "CD DSP." (1) MDAT (medium data: input) Serial data stream from CD DSP. (2) BCLK (bit clock: input) Bit clock signal; MDAT signal strobe. (3) LRCK (LR clock: input) LR clock signal; indicates left and right channels of MDAT signals. (4) C2PO (C2 pointer: input) C2 pointer signal; indicates that an error is contained in MDAT input. (5) WFCK (write frame clock: input) Write frame clock input signal. (6) SCOR (subcode sync OR: input) Subcode sync signal. (7) SBIN (subcode serial input: input) Subcode serial signal. (8) EXCK (external clock: output) Clock output for reading SBIN signals. 1-2. Buffer memory interface (21 pins) This can be connected with up to a 512K-byte DRAM (4M bits). (1) XMWR (DRAM write enable: output) DRAM write enable negative logic output signal. (2) XCAS (column address strobe: output) Negative logic output signal to indicate that column addresses are valid. (3) XRAS (row address strobe: output) Negative logic output signal to indicate that row addresses are valid. (4) MA0 to MA9 (DRAM address: output) DRAM address output. (5) MDB0 to MDB7 (DRAM data bus: input/output) DRAM data bus signal; pulled up by a standard 25kΩ resistor. 1-3. Sub CPU interface (18 pins) (1) XWR (sub CPU write: input) Strobe negative logic signal for writing internal registers. (2) XRD (sub CPU read: input) Strobe negative logic signal for reading internal registers status. (3) D0 to D7 (sub CPU data bus: input/output) 8-bit data bus; pulled up by a standard 25kΩ resistor. (4) A0 to A5 (sub CPU address: input) Address signal for selecting internal registers from sub CPU. (5) XINT (sub CPU interrupt: output) Interrupt request signal to sub CPU. Polarity can be controlled by sub CPU. (6) XCS (chip select: input) Chip select negative logic signal from sub CPU. – 16 – CXD1812Q/R 1-4. HOST interface (31 pins) (1) HCS0 (host chip select: input) Chip select negative logic signal from host; pulled up by a standard 50kΩ resistor. This is connected with the CS1FX pin of ATAPI I/F. (2) HCS1 (host chip select: input) Chip select negative logic signal from host; pulled up by a standard 50kΩ resistor. This is connected with the CS3FX pin of ATAPI I/F. (3) HA0 to HA2 (host address: input) Address signal for selecting internal registers from host. (4) DASP (drive active/slave present: input/output) Negative logic signal to indicate that slave drive is present or drive is active; open drain signal. (5) HDB0 to HDBF (host data bus: input/output) 16-bit host data bus signal. (6) XHRD (host read: input) Data read strobe negative logic signal from host. (7) XHWR (host write: input) Data write strobe negative logic signal from host. (8) XHAC (host DMA acknowledge: input) DMA data request acknowledge negative logic signal from host. (9) HDRQ (host DMA request: output) DMA data request positive logic signal to host; tristate output. (10) HINT (host interrupt: output) Interrupt request positive logic signal to host; tristate output. (11) XS16 (16-bit data transfer: output) Negative logic signal to indicate that the 16-bit data port has been selected; open drain signal. This is connected with the IOCS16 pin of ATAPI I/F. (12) REDY (I/O channel ready: output) Positive logic signal to be negated when the drive is not ready to respond to a data transfer reguest; open drain signal. This is connected with the IORDY pin of ATAPI I/F. (13) XPDI (passed diagnostics: input/output) Negative logic signal that indicates diagnostics of the slave drive has been completed; open drain signal. This is connected with the PDIAG pin of ATAPI I/F. (14) HRST (host reset: input) Reset negative logic signal from host; pulled up by a standard 50kΩ resistor. 1-5. Others (5 pins) (1) XRST (reset: input) Chip reset negative logic input signal. (2) XTL1 (crystal 1: input) (3) XTL2 (crystal 2: output) A crystal oscillator is connected between XTL1 and XTL2. (The capacitor value depends on the crystal oscillator.) (4) MCLK (clock: output) Outputs a clock signal of the same frequency as that of XTL1. The output can be set at low when this clock signal is not used. (5) HCLK (half clock: output) Outputs a clock signal with 1/2 the frequency of XTL1. The output can be set at low when this signal is not used. 1-6. Power supply (17 pins) VDD: 4 pins, GND: 13 pins. – 17 – CXD1812Q/R 2. Sub CPU Write Registers Normally set at low for reserved registers and bits. 2-1. CONFIG0 (configuration 0) register (address 00HEX) bit 7: CINTPOL (sub CPU interrupt polarity) High: The XINT pin becomes high-active. When the register is inactive, the low state is established. Low: The XINT pin becomes low-active. When the register is inactive, high impedance is established. bit 6: M/S SEL (master/slave select) This bit is valid only when M/S EN (bit 5) is high. High: Set this bit high when a slave drive is used. Low: Set this bit low when a master drive is used. bit 5: M/S EN (master/slave mode enable) Set this bit as follows according to the number of drives connected to ATAPI I/F. High: Set this bit high when two drives are connected to ATAPI I/F. One is used as the master drive and the other is the slave drive. Low: Set this bit low when only one drive is connected to ATAPI I/F. bit 4: RESERVED bit 3: EXCKSL (EXCK select) The frequency of EXCK clock signal for picking up subcodes from CD DSP is determined by this bit. The sub CPU sets this register according to the clock frequency and the playback speed of the XTL1 pin. (Max. frequency of EXCK clock signal is 1MHz.) High: The EXCK frequency is 1/48 the frequency of XTL1. When the frequency of the XTL1 pin is more than 32MHz, this bit is set high. Low: The EXCK frequency is determined to be 1/32 the frequency of XTL1. When the frequency of the XTL1 pin is not more than 32MHz, this bit is set low. bit 2: DISMCLK (disable MCLK output) High: The MCLK pin is fixed at low. Low: The clock signal of the same frequency as that of the XTL1 pin is output from the MCLK pin. bit 1: DISHCLK (disable HCLK output) High: HCLK pin is fixed at low. Low: The frequency divider clock signal of half the frequency of XTL1 pin is output from HCLK pin. bit 0: RAMSIZE (RAM size) High: When a 4M-bit DRAM is connected, set this bit high. Low: When a DRAM of up to 2M bits is connected, set this bit low. 2-2. CONFIG1 (configuration 1) register (address 01HEX) bit 7: SWOPEN (sync window open) High: A window for Sync mark detection is opened. In this case, the internal Sync protection circuit is disabled. Low: A window for Sync mark detection is controlled by the internal Sync protection circuit. bit 6 to 4: SYCNGC2 to 0 (sync NG count 2 to 0) Set "010" for these bits. bit 3: RESERVED – 18 – CXD1812Q/R bit 2, 1: RFRSCTL1, 0 (refresh control 1, 0) The refresh interval of the DRAM can be controlled by these bits. Set these bits according to the clock frequency of XTL1. The refresh interval is designed as 512 cycle/8ms. RFRSCTL1 "L" "L" "H" "H" RFRSCTL0 "L" "H" "L" "H" XTL1 frequency: less than 24MHz XTL1 frequency: 24MHz or more XTL1 frequency: 32MHz or more XTL1 frequency: 33.8688MHz or more bit0 RESERVED 2-3. LSTARA (last area) register (address 02HEX) The last area is assigned by this register. The following table shows the set values of LASTARA when the buffer memory is fully used. ENBYTFBT "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" RAM size 32KB LASTARAHEX 0C 0A 19 16 34 2E 69 5E D3 BD 64KB 128KB 256KB 512KB 2-4. LHADR (last HADRC) register (address 03HEX) Assigns the upper limit (upper 8 bits) of HADRC when the automatic transfer mode to the host is disabled, or the upper limit (upper 8 bits) of the address when the row subcode buffering command is executed. The lower 11 bits are assigned to 7FFHEX. 2-5. DRVIF (drive interface) register (address 04HEX) This register controls the connection mode with the CD DSP. After the IC is reset, the sub CPU sets this register according to the CD DSP to be connected. Any change of each bit in this register must be made in the decoder disable status. (After the IC is reset, the address is set 28HEX.) Figs. 1-1 and 1-2 are input timing charts for Sony's typical CD DSP. – 19 – LRCK 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 BCLK MDAT L15 Lch MSB C2 Pointer for Upper byte C2 Pointer for Lower byte L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 R1 R0 L1 L0 Lch LSB Rch LSB C2PO Fig. 1-1. CDL40 and 50 Series Timing Chart (48-bit slot mode) – 20 – 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Rch LSB C2 Pointer for Upper byte LRCK 1 2 3 4 5 6 25 26 27 28 29 30 31 32 BCLK MDAT L14 L15 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Rch MSB Lch MSB C2PO C2 Pointer for Lower byte CXD1812Q/R Fig. 1-2. CDL40 and 50 Series Timing Chart (64-bit slot mode) CXD1812Q/R bit 7: bit 6: bit 5: bit 4, 3: C2PL1ST (C2PO lower byte first) High: When 2 bytes of MDAT are input, C2PO inputs the lower byte first followed by the upper byte. Low: When 2 bytes of MDAT are input, C2PO inputs the upper byte first followed by the lower byte. Here, "upper byte" means the upper 8 bits including MSB from the CD DSP and "lower byte" means the lower 8 bits including LSB from the CD DSP. For example, the Header minute byte is the lower byte and the second byte, the upper byte. LCHLOW (Lch low) High: When LRCK is low, determined to be the left channel data. Low: When LRCK is high, determined to be the left channel data. BCKRED (BCLK rising edge) High: MDAT is strobed at the rising edge of BCLK. Low: MDAT is strobed at the falling edge of BCLK. BCKMD1, 0 (BCLK mode 1, 0) These bits are set according to the number of clocks output for BCLK during one WCLK cycle by the CD DSP. BCKMD1 "L" "L" "H" BCKMD0 "L" "H" "X" 16BCLKs/WCLK 24BCLKs/WCLK 32BCLKs/WCLK bit 2: bit 1, 0: LSB1ST (LSB first) High: Connected with the CD DSP which outputs MDAT with LSB first. Low: Connected with the CD DSP which outputs MDAT with MSB first. RESERVED 2-6. XFRFMT0 (transfer format 0) register (address 05HEX) The transfer format for automatic data transfer is determined by this register. This IC transfers the buffer memory data to the host according to the Mode/Form value written by SCTINF register (address 1EHEX) into the internal RAM by sector and the values of XFRFMT1 and 0 registers. The Mode/Form of bits 3 to 1 depends on the values of bits 2 and 1 of SCTINF register. Regarding Mode 2 in Yellow Book, don't care the Form2 (bit 2) of SCTINF register. Set bits 3 to 1 of XFRFMT0 register high to transfer 2336 bytes of user data. bit 7, 6: bit 5: RESERVED SYNC High: The Sync mark is transferred to the host. Low: The Sync mark is not transferred to the host. HEADER High: The Header's 4 bytes are transferred to the host. Low: The Header's 4 bytes are not transferred to the host. SUBHEADER High: Mode1: This bit has no meaning. Mode 2: The Sub Header's 8 bytes are transferred to the host. Low: The bytes above are not transferred to the host. bit 4: bit 3: – 21 – CXD1812Q/R bit 2: bit 1: bit 0: USERDATA (user data) High: Mode1 and Mode2/Form1: User data (2048 bytes) are transferred to the host. Mode2/Form2: User data (2324 bytes) are transferred to the host. Low: The bytes above are not transferred to the host. PARITY High: Mode1: The EDC, ECC parity and eight 00HEX bytes, for a total of 288 bytes, are transferred to the host. Mode2/Form1: The EDC and ECC parity (280 bytes) are transferred to the host. Mode2/Form2: RESERVED bytes (4 bytes) (the final ones in the sector concerned) are transferred to the host. Low: The bytes above are not transferred to the host. RESERVED Regarding CD-DA data, set bits 5 to 1 high. 2-7. XFRFMT1 (transfer format 1) register (address 06HEX) bit 7: ENBLKEFL (enable block error flag) High: Block error flag (1 byte + 00HEX) is transferred to the host. Here, block error flag means operating OR by bit of the byte error flag. Low: The bytes above are not transferred to the host. bit 6: RESERVED bit 5: ENBYTFBT (enable byte error flag buffering and transfer) When this bit is set high, the following operations are performed. When this bit is set low, the following operations are not performed. This bit is valid only when the USERDATA bit (bit 2) of XFRFMT0 register is set high. (1) When write-only, real-time correction, or CD-DA command is being executed, byte error flag is buffered. (2) When the automatic transfer mode to the host is enabled (that is, the AUTOXFR bit of XFRCTL register (bit 7) is high), byte error flag is transferred to the host. bit 4: RESERVED bit 3: ENSBCBT (enable subcode buffering and transfer) When this bit is set high, the following operations are performed. When this bit is set low, the following operations are not performed. (1) When CD-DA command is being executed, all the subcodes or the subcode-Q are buffered. (2) When the automatic transfer mode to the host is enabled (that is, the AUTOXFR bit of XFRCTL register (bit 7) is high), all the subcodes or the subcode-Q are transferred to the host. bit 2: ALLSBC (all subcodes/subcode-Q) When ENSBCBT is set high, whether all the subcodes or the subcode-Q are to be buffered or transferred to the host is determined. High: All the subcodes Low: Subcode-Q bit 1: RESERVED bit 0: ZASUBQ (zero after sub-Q) This bit is valid only when ENSBCBT is high and ALLSBC is low. High: 6-byte 00HEX in addition to the subcode-Q are transferred to the host. Low: 2-byte CRC and 4-byte 00HEX in addition to the subcode-Q are transferred to the host. – 22 – CXD1812Q/R 2-8. DECCTL0 (decoder control 0) register (address 07HEX) bit 7: AUTODIST (auto distinction) High: Errors are corrected according to the Mode byte and the Form bit read by the drive. Low: Errors are corrected according to the MODESEL and FORMSEL bits (bits 6 and 5). bit 6: MODESEL (mode select) bit 5: FORMSEL (form select) When AUTODIST is set low, the sector is corrected in the Mode or Form indicated below. MODESEL "L" "H" "H" bit 4: bit 3: FORMSEL "L" "L" "H" MODE1 MODE2, FORM1 MODE2, FORM2 bit 2: bit 1: bit 0: RESERVED ENFM2EDC (enable form 2 EDC check) High: EDC check for Form2 is enabled. Low: EDC check for Form2 is disabled. The EDCNG bit of DECSTS0 register is set low. MDBYTCTL (mode byte control) High: Even if there are data other than 0 in the upper 6 bits of the Header's Mode byte, it is not determined to be an error. Set this bit high when a CD-DA command is executed or the disc such as CD-R is played back. Low: If the upper 6 bits of the Header's Mode byte are not "000000," it is determined to be an error. ENDLA (enable drive last area (address)) High: DLAR (drive last area)/SLADR (subcode last address) is enabled. When buffering of the buffer memory area assigned by DLAR is completed while the decoder is executing the write-only, real-time correction, or CD-DA command, the DRVOVRN (drive over run) status is established. When buffering to the address assigned by SLADR is completed while the subcode buffering command is being executed, the DRVOVRN status is established. In the DRVOVRN status,data writing into the buffer is stopped. Low: DLAR (drive last area)/SLADR (subcode last address) is disabled. ATDLRNEW (Auto DLARA renewal) High: When the data transfer to host is completed for one sector, DLARA is renewed in the written area of the sector. Low: Renewal of DLARA is executed by the sub CPU. – 23 – CXD1812Q/R 2-9. DECCTL1 (decoder control 1) register (address 08HEX) bit 7: ENSBQRD (enable subcode-Q read) CRC of subcode-Q is checked by taking in the subcode from DSP. Sub CPU can read subcode-Q data from the SUBQ register. bit 6: RESERVED bit 5 to 3: DECCMD2 to 0 (decoder commands 2 to 0) DECCMD2 "L" "L" "L" "L" "H" "H" bit 2 to 0: RESERVED 2-10. XFRMOD (transfer mode) register (address 09HEX) bit 7: ENHINTCT (enable auto HINT upon start of packet command transfer) High: When packet command transfer starts, there is an interrupt request to the host. Low: When the transfer above starts, there is no interrupt request to the host. bit 6: ENHINTDT (enable auto HINT upon start of data transfer) High: When data transfer with the host starts, there is an interrupt request to the host. Low: When the transfer above starts, there is no interrupt request to the host. bit 5: ENMDMA (enable multiword DMA) This bit is valid for DMA transfer. High: DMA transfer is executed in the multiword mode. Low: DMA transfer is executed in the single-word mode. bit 4: ENDMABIT (enable ATAPI feature register DMA bit) bit 3: PIOSEL (PIO transfer mode select) Transfer mode is determined as shown below from the combination of these bits and the DMA bit (bit 0) of ATAPI feature register. PIOSEL "H" "L" "L" "L" bit 2: ENDMABIT "X" "H" "H" "L" DMA "X" "H" "L" "X" Transfer Mode PIO DMA PIO DMA DECCMD1 "L" "L" "H" "H" "L" "H" DECCMD0 "L" "H" "L" "H" "H" "H" Decoder command Decoder disable Monitor only Write only Real-time correction Raw subcode buffer CD-DA AUTOWAIT (enable auto wait state) This bit is valid for PIO transfer. High: In the cases below, the REDY pin is set low and a wait is automatically applied to the host. Transfer to host: When the host asserts the XHRD signal while the data FIFO is empty. Transfer from host: When the host asserts the XHWR signal while the data FIFO is full. Low: The wait state above does not occur. – 24 – CXD1812Q/R bit 1, 0: WAITCYCL1, 0 These bits are valid for PIO transfer. If the host asserts XHRD/XHWR during data transfer, the REDY pin is set low by the cycle number set with these bits, and a wait is applied. One cycle is XTL1 cycle. 00: Wait state does not occur. 01: Wait state of 4 to 8 cycles occurs. 10: Wait state of 8 to 12 cycles occurs. 11: Wait state of 12 to 16 cycles occurs. 2-11. XFRCTL0 (transfer control 0) register (address 0AHEX) bit 7: AUTOXFR (auto transfer) High: The automatic transfer mode to the host described later is enabled. Low: The automatic transfer mode to the host above is disabled. Transfer to the host is executed by setting HADRC and HXFRC. bit 6 to 4: RESERVED bit 3: CPUDMAEN (sub CPU DMA enable) The buffer memory access by sub CPU is enabled by setting this bit high. The sub CPU sets this bit high after the head addresses of buffer access have been set on the CADRC. bit 2: CPUSRC (sub CPU source) High: Data are transferred from sub CPU to buffer memory. Low: Data are transferred from buffer memory to sub CPU. bit 1 to 0: RESERVED 2-12. XFRCTL1 (transfer control 1) register (address 0BHEX) bit 7: PFIFOCL (packet FIFO clear) When this bit is set high, the packet FIFO is cleared. This bit is automatically set low after FIFO has been cleared. bit 6: RESERVED bit 5: AUTOEND (enable auto transfer termination) The following settings are automatically made upon completion of data transfer. High: ATAPI status register - bit 7/bit 6/bit 3: BUSY/DRDY/DRQ = Low/High/Low ATAPI interrupt reason register - bit 1/bit 0: IO/CoD = High/High Interrupt request signal to host: HINT = High Low: ATAPI status register - bit 7/bit 3: BUSY/DRQ = High/Low Interrupt request signal to host: HINT = Low bit 4: HSTXFREN (host transfer enable) When this bit is set high, transfer starts between the host and buffer memory. This bit is automatically set low when transfer is completed. The following settings are automatically operated by setting this bit high. ATAPI status register -bit 3: DRQ = High ATAPI status register -bit 7: BUSY = Low (in the PIO mode) bit 3, 2: RESERVED – 25 – CXD1812Q/R bit 1: bit 0: IO (host transfer direction) To set this bit, the ATAPI status register -bit 7: BUSY bit must be high. High: Data are transferred from the buffer memory to the host. Low: Data are transferred from the host to the buffer memory. CoD (command or data) To set this bit, the ATAPI status register -bit 7: BUSY bit must be high. High: Indicates that data transferred are Command. Low: Indicates that the data transferred are user data. 2-13. RESERVED (address 0CHEX) 2-14. CHPCTL0 (chip control 0) register (address 0DHEX) bit 7: CHIPRST (chip reset) This IC is reset by setting this bit high. bit 6: TGTMET (target met) (1) If the target sector is found while the write-only or real-time correction command is being executed, the sub CPU sets TGTMET high. (2) TGTMET bit is sampled at the 3/4 sector (variable depending on playback speed) after the decoder interrupt. Therefore, if the target sector has been found, the sub CPU must set the TGTMET bit high within this time after DECINT. (3) Once the TGTMET bit is set high, the high state is held until the decoder is disabled. (4) When the sampled TGTMET is low, while write-only or real-time correction is executed, •the buffering area of main data or subcode is not renewed. • main data are not corrected. bit 5: INCTGT (increment target register) When this bit is set high, TARGET registers (TGTMIN, TGTSEC, TGTBLK) are incremented. TARGET registers use the BCD code. TGTMIN, TGTSEC, and TGTBLK are connected in cascading fashion, and are incremented as follows: (1) The TGTBLK register value is always incremented by this bit. The address number 0 follows 74. (2) The TGTSEC register value is incremented when this bit is high while the TGTBLK register value is 74. The address number 0 follows 59. (3) The TGTMIN register value is incremented when this bit is high, while the TGTBLK register value is 74 and the TGTSEC register value 59. The address number 0 follows 99. bit 4: RPCORTRG (repeat correction trigger) When this bit is set high with the decoder disabled, error correction for the CD-ROM sector starts. The sector to be corrected is assigned by the BFARA# register. bit 3 to 0: RESERVED – 26 – CXD1812Q/R 2-15. CHPCTL1 (chip control 1) register (address 0EHEX) bit 7 to 3: RESERVED bit 2: DASP (DASP pin control) When this bit is set high, the DASP signal is asserted. bit 1: PDIAG (XPDI pin control) When this bit is set high, the XPDI signal is asserted. bit 0: CLRHINT (clear HINT) HINT is cleared by setting this bit high. This bit is automatically set low when HINT has been cleared. 2-16. Diskette change/drive address register (address 0FHEX) bit 7: RESERVED bit 6 to 2: Optional values can be set by sub CPU. These values can be read from bits 6 to 2 of the diskette change/drive address register of the host. bit 1 to 0: RESERVED 2-17. ATAPI error register (address 10HEX) This register corresponds to the ATAPI error register of the host. The sub CPU can set any optional values. bit 7 to 4: SENSE KEY bit 3: MCR (Media Change Requested) bit 2: ABRT (Aborted Command) bit 1: EOM (End Of Media Detected) bit 0: ILI (Illegal Length Indication) 2-18. ATAPI feature register (address 11HEX) This register corresponds to the ATAPI feature register of the host. The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is high. bit 0: DMA 2-19. ATAPI interrupt reason register (address 12HEX) This register corresponds to the ATAPI interrupt reason register of the host. The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is high. bit 1: IO This bit is equivalent to the XFRCTL1 (address 0BHEX) register -bit 1. bit 0: CoD This bit is equivalent to the XFRCTL1 (address 0BHEX) register -bit 0. 2-20. ATA sector number register (address 13HEX) This register corresponds to the ATA sector number register of the host. The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is high. 2-21. ATAPI byte count high/low register (address 14, 15HEX) This register corresponds to the ATAPI byte count high/low register of the host. The number of bytes to be transferred is set. The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is high. – 27 – CXD1812Q/R 2-22. ATAPI drive select register (address 16HEX) This register corresponds to the ATAPI drive select register of the host. The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is high. bit 4: DRV 2-23. ATA command register (address 17HEX) This register corresponds to the ATA command register of the host. The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is high. However, the ATAPI soft reset command (08HEX) can be set regardless of the value of the BUSY bit. 2-24. RESERVED (address 18HEX) 2-25. ATAPI status 1 register (address 19HEX) bit 7, 6: RESERVED bit 5: DRDY1 (drive 1 ready) This bit corresponds to the ATAPI status register -bit 6: DRDY bit of the host. The DRDY status of the slave drive is set. bit 4: DSC1 (drive 1 seek complete) This bit corresponds to the ATAPI status register -bit 4: DSC bit of the host. The DSC status of the slave drive is set. bit 3: HST5 This bit corresponds to the ATAPI status register -bit 5 of the host. bit 2: HST1 This bit corresponds to the ATAPI status register -bit 1 of the host. bit 1: DRDY0 (drive 0 ready) This bit corresponds to the ATAPI status register -bit 6: DRDY bit of the host. The DRDY status of the master drive is set. bit 0: DSC0 (drive 0 seek complete) This bit corresponds to the ATAPI status register -bit 4: DSC bit of the host. The DSC status of the master drive is set. 2-26. ATAPI status 2/drive control register (address 1AHEX) bit 7: BUSY This bit corresponds to the ATAPI status register -bit 7 of the host. This bit must be set high when the sub CPU accesses the group of command block registers. bit 6: RESERVED bit 5: CORR This bit corresponds to the ATAPI status register -bit 2 of the host. bit 4: ENHINT (enable HINT) An interrupt to the host can be made by setting this bit high. bit 3 to 1: RESERVED bit 0: CHECK This bit corresponds to the ATAPI status register -bit 0 of the host. – 28 – CXD1812Q/R 2-27. UNLOCK (release lock mode) register (address 1BHEX) The bits 5 to 0 of ATAPI status 1 register (address 19HEX), the bits 1 and 0 of XFRCTL1 register (address 0BHEX), and ATAPI interrupt reason register (address 12HEX) are locked in the cases below, making setting from sub CPU impossible. • When an ATAPI packet command (A0HEX) is detected. • When data transfer with the host is completed while the XFRCTL1 register (address 0BHEX) bit 5: AUTOEND is high. The sub CPU can release the lock mode above by accessing this register. 2-28. CPUBWDT (CPU buffer write data) register (address 1CHEX) The sub CPU writes data to be written in the buffer memory into this register. 2-29. RESERVED (address 1DHEX) 2-30. SCTINF (sector information) register (address 1EHEX) The current sector information is written into this register at DECINT. For automatic transfer of information to the host, make sure this register is set for each DECINT. The value of this register is written into the internal RAM. bit 7 to 3: RESERVED bit 2: Mode2 High: This sector is in Mode2. Low: This sector is in Mode1 or CD-DA. bit 1: Form2 This bit is valid only when the Mode2 bit is high. High: This sector is in Form2. Low: This sector is in Form1. Both low and high are available for this bit in the Mode2 for Yellow Book. MODE2 "L" "H" "H" "L" bit 0: RESERVED FORM2 "L" "L" "H" "X" MODE1 MODE2/FORM1 MODE2/FORM2 CD-DA 2-31. RESERVED register (address 1F, 20HEX) 2-32. TGTMIN (target minute) register (address 21HEX) 0 to 99 2-33. TGTSEC (target sector ) register (address 22HEX) 0 to 59 – 29 – CXD1812Q/R 2-34. TGTBLK (target block) register (address 23HEX) 0 to 74 When the monitor-only, write-only, or real-time correction command is executed, set the addresses of the target sector in three target registers. This address is compared with the read sector address, and if they do not match, the TGTNTMET (target not met) status (DECSTS0 register: bit 0) is established. 2-35. XFRCNT (transfer block counter) register (address 24HEX) This 8-bit register indicates the remaining number of blocks to be transferred. The sub CPU sets the total number of blocks to be transferred before transfer starts. This register value is decremented after one block has been transferred. The sub CPU can read the value of XFRCNT at any time. However, take care over ±1 error between the read value and actual one, because the reading from sub CPU does not synchronize with variations of XFRCNT. 2-36. BFARA# (buffering area number) register (address 25HEX) The buffer area is indicated by this register when write-only, real-time correction, or CD-DA command is executed. The sub CPU, first assigns the area to start buffering before any of these commands is executed. The register value is incremented after one sector is buffered. Buffering starts from the address 0 when the subcode buffering command is executed. 2-37. DLARA (drive last area) register (address 26HEX) While the decoder is executing the write-only, real-time correction, or CD-DA command, the last area for buffering is assigned by this register. When the ENDLA (bit 1) of the DECCTL0 register is set high and data from the drive (CD DSP) are written into the area assigned by DLARA while the decoder is executing any of the above commands, all subsequent buffering is prohibited. 2-38. XFRARA (transfer area) register (address 27HEX) The first area for starting transfer is assigned in the automatic transfer mode. The register value is incremented after one block is transferred. The sub CPU can read the value of XFRARA at any time. However, take care over ±1 error between the read value and actual one, because the reading from sub CPU does not synchronize with the variation of XFRARA. 2-39. RESERVED (address 28HEX) 2-40. HXFRC-H, M, L (host transfer counter - high, middle, low) register (address 29 to 2BHEX) The number of bytes to be transferred is set in the manual transfer mode. (19 bits) 2-41. RESERVED (address 2CHEX) 2-42. HADRC-H, M, L (host address counter - high, middle, low) register (address 2D to 2FHEX) The head address to start transfer is assigned in the manual transfer mode. 2-43. RESERVED (address 30HEX) 2-44. SLADR-H, M, L (subcode last address - high, middle, low) register (address 31 to 33HEX) While the subcode buffering command is being executed, the last address for buffering is set. When the ENDLA (bit 1) of the DECCTL0 register is set high and data are written into the buffer address assigned by SLADR while the decoder is executing the subcode buffering command, all subsequent buffering is prohibited. – 30 – CXD1812Q/R 2-45. RESERVED (address 34HEX) 2-46. CADRC-H, M, L (sub CPU address counter - high, middle, low) register (address 35 to 37HEX) The addresses are set by this register when the sub CPU accesses the buffer memory. The register value is incremented if the data concerned are read from the buffer memory or are written into it. 2-47. RESERVED (address 38 to 3BHEX) 2-48. CLRINT0 (clear interrupt status 0) register (address 3CHEX) When each bit of this register is set high, the corresponding interrupt status is cleared. The bit is automatically set low after its interrupt status has been cleared. Therefore, there is no need for the sub CPU to reset to low. bit 7: DECINT (Decoder Interrupt) bit 6: DECTOUT (Decoder Timeout) bit 5: DRVOVRN (Drive Overrun) bit 4: SUBCSYNC (Subcode Sync) bit 3, 2: RESERVED bit 1: SOFTRST (SRST Detected) bit 0: HARDRST (HRST Detected) 2-49. CLRINT1 (clear interrupt status 1) register (address 3DHEX) When each bit of this register is set high, the corresponding interrupt status is cleared. The bit is automatically set low after its interrupt status has been cleared. Therefore, there is no need for the sub CPU to reset to low. bit 7: PFIFOFUL (Packet FIFO Full) bit 6: RESERVED bit 5: RSTCMD (Reset Command) bit 4: STSREAD (Host Status Read) bit 3: HSTCMD (Host Command) bit 2: PIONG (PIO Transfer NG) bit 1: XFRSTOP (Transfer Stop) bit 0: BLXFRCMP (Block Transfer Complete) 2-50. INTEN0 (interrupt enable 0) register (address 3EHEX) When each bit of this register is set high, the interrupt request to the sub CPU by the corresponding interrupt status is enabled. (That is, the XINT pin becomes active in the interrupt status.) Each bit value of this register has no effect on the corresponding interrupt status. bit 7: DECINT (Decoder Interrupt) bit 6: DECTOUT (Decoder Timeout) bit 5: DRVOVRN (Drive Overrun) bit 4: SUBCSYNC (Subcode Sync) bit 3, 2: RESERVED bit 1: SOFTRST (SRST Detected) bit 0: HARDRST (HRST Detected) – 31 – CXD1812Q/R 2-51. INTEN1 (interrupt enable 1) register (address 3FHEX) When each bit of this register is set high, the interrupt request to the sub CPU by the corresponding interrupt status is enabled. (That is, the XINT pin becomes active in the interrupt status.) Each bit value of this register has no effect on the corresponding interrupt status. bit 7: PFIFOFUL (Packet FIFO Full) bit 6: RESERVED bit 5: RSTCMD (Reset Command) bit 4: STSREAD (Host Status Read) bit 3: HSTCMD (Host Command) bit 2: PIONG (PIO Transfer NG) bit 1: XFRSTOP (Transfer Stop) bit 0: BLXFRCMP (Block Transfer Complete) – 32 – CXD1812Q/R 3. Sub CPU Read Registers Descriptions that are identical with those for the write registers are omitted here. 3-1. DRVSTS (drive status) register (address 00HEX) The values set by the sub CPU can be read by this register. bit 7: CINTPOL (subCPU Interrupt Polarity) bit 6: M/S SEL (Master/Slave select) bit 5: M/S EN (Master/Slave mode Enable) bit 4, 3: RESERVED bit 2, 1: RFRSCTL1, 0 (Refresh Control1, 0) bit 1: RESERVED 3-2. RAWHDR (raw header) register (address 01HEX) The Header bytes of the sector sent from the CD DSP can be read by this register at DECINT. 3-3. BFHDR (buffer header) register (address 02HEX) The Header bytes of the current sector can be read when the write-only or real-time correction command is executed, or after repeat correction has been executed. This register is invalid when the decoder is executing the disable or the monitor-only command. 3-4. BFSHDR (buffer sub header) register (address 03HEX) The Sub Header bytes of the current sector can be read when the write-only or real-time correction command is executed, or after repeat correction has been executed. This register is invalid when the decoder is executing the disable or the monitor-only command. 3-5. RAWHDRFLG (raw header flag) register (address 04HEX) Indicates the C2PO value in the RAWHDR register. bit 7: Minute bit 6: Second bit 5: Block bit 4: Mode bit 3 to 0: RESERVED 3-6. BFHDRFLG (buffer header flag) (address 05HEX) Indicates the error state of each byte of BFHDR and BFSHDR registers. High means an error. bit 7: Minute bit 6: Second bit 5: Block bit 4: Mode bit 3: File bit 2: Channel bit 1: Submode bit 0: Data Type – 33 – CXD1812Q/R 3-7. RESERVED (address 06HEX) 3-8. DECSTS0 (decoder status 0) register (address 07HEX) bit 7: SHRTSCT (short sector) Indicates that the Sync mark interval was not more than 2351 bytes. This sector does not remain in the buffer memory. bit 6: NOSYNC Indicates that the Sync mark was inserted, because one was not detected at the prescribed position. bit 5: CORINH (correction inhibit) This is high if the current sector Mode and Form cannot be determined when the AUTODIST bit of the DECCTL register is set high. ECC or EDC is not executed in this sector. The CORINH bit is invalid when AUTODIST is set low. It is high under any of the conditions below when the AUTODIST bit is set high. (1) When there is an error in the Mode byte. (2) When the Mode byte is a value other than 01HEX or 02HEX. (3) When the Mode byte is 02HEX and the C2 pointer is high in the submode byte. bit 4: ERINBLK (erasure in block) When the decoder is operating in the monitor-only, write-only, or real-time correction mode, this indicates that at least a 1-byte error flag (C2PO) has been raised in the data, excluding the Sync mark from the current sector CD DSP. When the decoder is operating in the CD-DA mode, this indicates that at least a 1-byte error flag (C2PO) has been raised in the data from one sector (2352 bytes). bit 3: CORDONE (correction done) Indicates that there is an error-corrected byte in the current sector. bit 2: EDCNG Indicates that an error was found by the EDC check in the current sector. bit 1: ECCNG Indicates that there was an uncorrectable error from the Header byte to the P parity byte in the current sector. (ECCNG = don't care in the Mode2, Form2 sectors.) bit 0: TGTNTMET (target not met) Indicates that the target addresses in the TGTMNT, TGTSEC, and TGTBLK registers do not correspond with that of the read sector. 3-9. DECSTS1 (decoder status 1) register (address 08HEX) bit 7 to 3: RESERVED bit 2: EDCALL0 (EDC all 0) This bit is high if there are no errors in the 4-EDC parity bytes of the current sector and the value is 00HEX. bit 1: CMODE (correction mode) bit 0: CFORM (correction form) Indicates the Mode and Form the decoder has discriminated to correct errors of the current sector when the decoder is operating in the real-time correction or repeat correction mode. CMODE "L" "H" "H" CFORM "X" "L" "H" MODE1 MODE2, FORM1 MODE2, FORM2 – 34 – CXD1812Q/R 3-10. XFRMOD (transfer mode) register (address 09HEX) The values set by sub CPU can be read by this register. bit 7: ENHINTCT (Enable Auto HINT upon Start of Packet Command Transfer) bit 6: ENHINTDT (Enable Auto HINT upon Start of Data Transfer) bit 5: ENMDMA (Enable Multiword DMA) bit 4: ENDMABIT (Enable ATAPI Feature resister DMA bit) bit 3: PIOSEL (PIO Transfer Mode Select) bit 2: AUTOWAIT (Enable Auto Wait State) bit 1, 0: WAITCYCL1, 0 (Wait Cycle 1, 0) 3-11. XFRSTS0 (data transfer status 0) register (address 0AHEX) bit 7 to 2: RESERVED bit 1: CBFWRRDY (sub CPU buffer write ready) The sub CPU can write in the CPUBWDT register when this bit is high. bit 0: CBFRDRDY (sub CPU buffer read ready) The sub CPU can read the CPUBWDT register when this bit is high. 3-12. XFRSTS1 (data transfer status 1) register (address 0BHEX) bit 7, 6: RESERVED bit 5: AUTOEND (enable auto transfer termination) Value set by sub CPU can be read. bit 4: RESERVED bit 3: PFIFOFUL (packet FIFO full status) When a 12-byte packet command is written to the packet FIFO from the host, this bit is set high. bit 2: PFIFOEMP (packet FIFO empty status) When 12-byte data are read by sub CPU from the packet FIFO, this bit is set high. These bits are automatically cleared when an ATAPI packet command (A0HEX) or an ATAPI soft reset command (08HEX) is issued. bit 1: IO (HOST transfer direction) This bit can be set by both sub CPU and host. In the cases below, the bit is automatically set. High: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer has been completed. Low: When an ATAPI packet command (A0HEX) is issued. CoD (command or data) This bit can be set by both sub CPU and host. In the cases below, this bit is automatically set. High: When an ATAPI packet command (A0HEX) is issued. Low: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer has been completed. bit 0: – 35 – CXD1812Q/R 3-13. RESERVED (address 0C, 0DHEX) 3-14. CHPSTS (chip status) register (address 0EHEX) bit 7 to 3: RESERVED bit 2: DASP bit 1: PDIAG The DASP and XPDI pins can be monitored from these bits. Positive logic. bit 0: RESERVED 3-15. REV (revision number) register (address 0FHEX) The revision number of this IC is 83HEX. 3-16. ATAPI error register (address 10HEX) This register corresponds to the ATAPI error register of the host. The values set by sub CPU can be read. bit 7 to 4: SENSE KEY bit 3: MCR (Media Change Requested) bit 2: ABRT (Aborted Command) bit 1: EOM (End Of Media Detected) bit 0: ILI (Illegal Length Indication) 3-17. ATAPI feature register (address 11HEX) This register corresponds to the ATAPI feature register of the host. The values set by sub CPU or host can be read. bit 0: DMA 3-18. ATA sector count register (address 12HEX) This register corresponds to the ATA sector count/ATAPI interrupt reason register of the host. The values set by sub CPU or host can be read. 3-19. ATAPI sector number register (address 13HEX) This register corresponds to the ATA sector number register of the host. The values set by sub CPU or host can be read. 3-20. ATAPI byte count high/low register (address 14, 15HEX) This register corresponds to the byte count high/low register of the host. The values set by sub CPU or host can be read. 3-21. ATAPI drive select register (address 16HEX) This register corresponds to the ATAPI drive select register of the host. The values set by sub CPU or host can be read. bit 4: DRV 3-22. ATA command register (address 17HEX) This register corresponds to the ATA command register of the host. The values set by sub CPU or host can be read. – 36 – CXD1812Q/R 3-23. ATAPI packet command register (address 18HEX) This register is a 12-bytes FIFO. The ATAPI packet command issued from the host can be read by reading this register 12 times. 3-24. ATAPI status 1 register (address 19HEX) The values set by sub CPU can be read. bit 7, 6: RESERVED bit 5: DRDY1 (Drive1 Ready) bit 4: DSC1 (Drive1 Seek Complete) bit 3: HST5 bit 2: HST1 bit 1: DRDY0 (Drive0 Ready) bit 0: DSC0 (Drive0 Seek Complete) 3-25. ATAPI status 2 register (address 1AHEX) bit 7: BUSY In the cases below, the bit is set automatically. The bit can also be set directly by the sub CPU. High: When the host writes a command into the ATAPI command register. High: When the transfer of a 6-words (12-bytes) packet command from the host has been completed. High: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is low and the data transfer with the host has been completed. High: When various reset signals have been asserted. Low: When an ATAPI packet command (A0HEX) is issued and the setting of packet command transfer has been completed. Low: When the data transfer with the host is activated in the PIO mode. Low: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer with the host has been completed. bit 6: RESERVED bit 5: CORR The values set by sub CPU can be read. bit 4: HINT The HINT signal can be monitored. In the cases below, this bit is set automatically. • When the XFRMOD register (09HEX) -bit 7: ENHINTCT is high and the setting of packet command transfer is completed. • When the XFRMOD register (09HEX) -bit 6: ENHINTDT is high and the data transfer with the host is activated. • When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer with the host is completed. The bit is reset in the cases below. • When the host has read the ATAPI status register. • When the transfer of 12-bytes packet command has been completed before the host reads the ATAPI status register. • When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is low and the data transfer with the host has been completed before the host reads the ATAPI status register. bit 3: HRST The HRST pin can be monitored. bit 2: SRST bit 1: XHINEN This bit corresponds to the ATAPI device control register - bit 2, 1 of the host. The values set by the host can be read. bit 0: CHECK The values set by sub CPU can be read. – 37 – CXD1812Q/R 3-26. CSCTARA (current sector area) (address 1BHEX) Indicates the area number being written in the current sector. 3-27. CPUBRDT (CPU buffer read data) register (address 1CHEX) The sub CPU reads data from the buffer memory via this register. 3-28. SBCSTS (subcode status) register (address 1DHEX) The error status of the subcode written to the buffer while the CD-DA command is executed is indicated by this register. The period of validity is from a DECINT to the next DECINT. bit 7: SBCOVRN (subcode overrun) The SBCOVRN status is established when the ENSBCBT (bit 3) of the XFRFMT1 register is set high and subcode buffering to the area assigned by DLARA is completed while the decoder is executing the CD-DA command. Establishment of DRVOVRN and SBCOVRN states involves a time difference. bit 6: OVERFLOW Indicates that the FIFO of SBCSTS has overflowed with frequent occurrences of the subcode short sync. Subcode buffering is stopped by this overflow. Subcode has not been buffered in sectors obtained by subsequent interrupts of the decoder. bit 5: BFNTVAL (buffer not valid) Indicates that valid data have not been written to the buffer due to the short subcode sector. bit 4: NOSYNC0 Indicates that the Sync mark was inserted because subcode Sync mark was not detected at the prescribed position. bit 3 to 1: RESERVED bit 0: SUBQERR0 (subcode-Q error 0) Indicates that the subcode-Q was determined to be an error by the CRC check when ALLSBC is low. 3-29. SBQSTS (subcode-Q status) register (address 1EHEX) This register indicates the error status of the subcode-Q taken from CD DSP. The period of validity is from a SBCSYNC to the next SBCSYNC. bit 7 to 3: RESERVED bit 2: SHTSBCS1 (short subcode sector 1) Indicates that the subcode Sync mark interval after the previous SBCSYNC interrupt occurred was less than 98WFCK. bit 1: NOSYNC1 Indicates that the Sync mark was inserted because subcode Sync mark was not detected at the prescribed position. bit 0: SUBQERR1 (subcode-Q error 1) Indicates that the subcode-Q was determined to be an error by the CRC check. 3-30. SBQDT (subcode-Q DATA) register (address 1FHEX) The subcode-Q value can be read by reading this register 10 times. The read subcode-Q is data just before the SBCSYNC interrupt. 3-31. RESERVED (address 20HEX) 3-32. TGTMIN (target minute) register (address 21HEX) 3-33. TGTSEC (target second) register (address 22HEX) – 38 – CXD1812Q/R 3-34. TGTBLK (target block) register (address 23HEX) 3-35. XFRCNT (transfer block counter) register (address 24HEX) 3-36. BFARA# (buffering area number) register (address 25HEX) 3-37. DLARA (drive last area) register (address 26HEX) 3-38. XFRARA (transfer area) register (address 27HEX) 3-39. RESERVED (address 28HEX) 3-40. HXFRC-H, M, L (host transfer counter - high, middle, low) register (address 29 to 2BHEX) 3-41. RESERVED (address 2CHEX) 3-42. HADRC-H, M, L (host address counter - high, middle, low) register (address 2D to 2FHEX) 3-43. RESERVED (address 30HEX) 3-44. SLDR-H, M, L (subcode last address - high, middle, low) register (address 31 to 33HEX) 3-45. RESERVED (address 34HEX) 3-46. CADRC-H, M, L (sub CPU address counter - high, middle, low) register (address 35 to 37HEX) 3-47. RESERVED (address 38HEX) 3-48. SADRC-H, M, L (subcode address counter - high, middle, low) register (address 39 to 3BHEX) The buffer address can be read in the subcode buffering command. – 39 – CXD1812Q/R 3-49. INTSTS0 (interrupt status 0) register (address 3CHEX) The value of each bit in this register is the value of corresponding interrupt status. These bits are not affected by the values of the INTEN0 register bits. bit 7: DECINT (decoder interrupt) This interrupt occurs when the decoder is operating a command. (1) The DECINT status is established if the Header byte is received from CD DSP when the Sync mark is detected or inserted while the decoder is executing the write-only, monitor-only, or realtime correction command. However, it is not established if the Sync mark interval is less than 2352 bytes when its detection window is open. (2) The DECINT status is established each time one correction is completed when the decoder is in the repeat correction mode. (3) The DECINT status is established each time 2352 bytes of data are written while the decoder is executing the CD-DA command. (4) The DECINT status is established when the subcode Sync mark is detected or is inserted when the decoder is executing subcode buffering. However, it is not established if the interval from the DECINT to the next subcode Sync mark detected is less than 98WFCK. bit 6: DECTOUT (decoder timeout) The DECTOUT status is established when the Sync mark is not detected even after the time it takes to search three sectors (40.6ms at normal speed playback) has elapsed after the decoder has been set to the monitor-only, write-only or real-time correction mode. bit 5: DRVOVRN (drive overrun) The DRVOVRN status is established when the buffering into the area assigned by DLARA is completed while the decoder is executing the write-only, real-time correction or CD-DA command. The DRVOVRN status is also established when the buffering into the address assigned by SLADR is completed while the decoder is executing the subcode buffering command. bit 4: SUBCSYNC (subcode sync) The SUBCSYNC status is established when the subcode Sync mark is detected or inserted while taking-in of subcode is enabled. However, it is not established if the interval from the SUBCSYNC to the next subcode Sync mark detected is less than 98WFCK. If the SUBCSYNC interrupt is not cleared within 95WFCK from the interrupt, the SUBCSYNC status is not established when the next subcode Sync mark is detected or inserted. In this case, the subcode-Q read from the SBQDT register is not renewed. bit 3, 2: RESERVED bit 1: SOFTRST (SRST detected) The SOFTRST status is established when the host asserts the ATAPI device control register -bit 2: SRST. bit 0: HARDRST (HRST detected) The HARDRST status is established when the host asserts the HRST pin. – 40 – CXD1812Q/R 3-50. INSTS1 (interrupt status 1) register (address 3DHEX) The value of each bit in this register is that of the corresponding interrupt status. These bits are not affected by the values of the INTEN1 register bits. bit 7: PFIFOFUL (packet FIFO full) The PFIFOFUL status is established when the transfer of a 6-words (12 bytes) packet command from the host is completed. bit 6: RESERVED bit 5: RSTCMD (reset command) The RSTCMD status is established when an ATAPI soft reset command (08HEX) is issued from the host. bit 4: STSREAD (HOST status read) The STSREAD status is established when the ATAPI status register is read by the host after data transfer with the host has been completed. bit 3: HSTCMD (host command) The HSTCMD status is established when the command is written into the ATA command register from the host. bit 2: PIONG (PIO transfer NG) The PIONG status is established if a read/write operation is executed by the host when the IO channel ready signal: REDY is low (not ready) during data transfer in the PIO mode. bit 1: XFRSTOP (transfer stop) The XFRSTOP status is established when all transfers are completed when the automatic transfer mode to the host is enabled. The XFRSTOP status is also established after transfer to the host is completed by HXFRC when the automatic transfer mode to the host is disabled. bit 0: BLXFRCMP (block transfer complete) The BLXFRCMP status is established after one block transfer is completed when the automatic transfer mode to the host is enabled. 3-51. INTEN0 (interrupt enable 0) register (address 3EHEX) The values written to the INTEN0 register can be read as they are. 3-52. INTEN1 (interrupt enable 1) register (address 3FHEX) The values written to the INTEN1 register can be read as they are. – 41 – CXD1812Q/R REG CONFIG0 CONFIG1 LSTARA LHADR DRVIF XFRFMT0 XFRFMT1 DECCTL0 DECCTL1 XFRMOD XFRCTL0 XFRCTL1 ADR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C bit7 CINT POL SW OPEN b7 b7 C2PO L1st "L" BLKE FLAG AUTO DIST ENSB QRD ENHI NTCT AUTO XFR PFIF O CL "L" CHIP RST "L" "L" bit6 M/S SEL "L" b6 b6 LCH LOW "L" "L" MODE SEL "L" ENHI NTDT "L" "L" "L" TGT MET "L" b6 bit5 M/S EN "H" b5 b5 BCLK RED SYNC ENBY TFBT FORM SEL DEC CMD2 EN MDMA "L" AUTO END "L" INC TGT "L" b5 bit4 "L" "L" b4 b4 BCLK MD1 HEAD ER "L" "L" DEC CMD1 ENDM ABIT "L" HSTX FREN "L" RPCO RTRG "L" b4 bit3 EXCK SEL "L" b3 b3 BCLK MD0 SBHE ADER ENSB CBT ENFM 2EDC DEC CMD0 PIO SEL CPUD MAEN "L" "L" "L" "L" b3 MCR bit2 DIS MCLK RFRS CTL1 b2 b2 LSB 1st USER DATA ALL SBC MDBY TCTL "L" AUTO WAIT CPU SRC "L" "L" "L" DASP b2 ABRT b2 b2 b2 b10 b2 bit1 DIS HCLK RFRS CTL0 b1 b1 "L" PARI TY "L" EN DLA "L" WAIT CYCL1 "L" IO "L" "L" PDIAG "L" EOM b1 IO b1 b9 b1 bit0 RAM SIZE "L" b0 b0 "L" "L" ZA SUBQ ATDL RNEW "L" WAIT CYCL0 "L" CoD "L" "L" CLR HINT "L" ILI DMA CoD b0 b8 b0 CHPCTL0 CHPCTL1 DISCHG DRVADR ERROR FEATUR INT REASON SECTOR NUMBER BYTE CNT-H BYTE CNT-L 0D 0E 0F 10 11 12 13 14 15 SENSE KEY b7 b7 b7 b15 b7 b6 b6 b6 b14 b6 b5 b5 b5 b13 b5 b4 b4 b4 b12 b4 b3 b3 b3 b11 b3 Sub CPU write registers (1) – 42 – CXD1812Q/R REG DRIVE SELECT HOST CMD ADR 16 17 18 bit7 b7 b7 "L" "L" BUSY bit6 b6 b6 "L" "L" "L" bit5 b5 b5 "L" bit4 DRV b4 "L" bit3 b3 b3 "L" HST5 "L" bit2 b2 b2 "L" HST1 "L" bit1 b1 b1 "L" bit0 b0 b0 "L" ATAPI STS 1 ATAPI STS 2 UN LOCK CPUBW DT 19 1A 1B 1C 1D DRDY1 DSC1 CORR EN HINT DRDY0 DSC0 "L" CHECK b7 "L" "L" "L" "L" b7 b7 b7 b7 b7 b7 b7 "L" "L" b15 b7 b6 "L" "L" "L" "L" b6 b6 b6 b6 b6 b6 b6 "L" "L" b14 b6 b5 "L" "L" "L" "L" b5 b5 b5 b5 b5 b5 b5 "L" "L" b13 b5 b4 "L" "L" "L" "L" b4 b4 b4 b4 b4 b4 b4 "L" "L" b12 b4 b3 "L" "L" "L" "L" b3 b3 b3 b3 b3 b3 b3 "L" "L" b11 b3 b2 "L" b1 "L" b0 "L" SCTINF 1E 1F 20 MODE2 FORM2 "L" "L" "L" b2 b2 b2 b2 b2 b2 b2 "L" b18 b10 b2 "L" "L" b1 b1 b1 b1 b1 b1 b1 "L" b17 b9 b1 "L" "L" b0 b0 b0 b0 b0 b0 b0 "L" b16 b8 b0 TGTMIN TGTSEC TGTBLK XFRCNT BFARA# DLARA XFRARA 21 22 23 24 25 26 27 28 HXFRC -H HXFRC -M HXFRC -L 29 2A 2B Sub CPU write registers (2) – 43 – CXD1812Q/R REG ADR 2C bit7 "L" "L" b15 b7 "L" "L" b15 b7 "L" "L" b15 b7 "L" "L" "L" "L" DEC INT PFIF OFUL DEC INT PFIF OFUL bit6 "L" "L" b14 b6 "L" "L" b14 b6 "L" "L" b14 b6 "L" "L" "L" "L" DEC TOUT "L" DEC TOUT "L" bit5 "L" "L" b13 b5 "L" "L" b13 b5 "L" "L" b13 b5 "L" "L" "L" "L" DRV OVRN RST CMD DRV OVRN RST CMD bit4 "L" "L" b12 b4 "L" "L" b12 b4 "L" "L" b12 b4 "L" "L" "L" "L" SUBC SYNC STS READ SUBC SYNC STS READ bit3 "L" "L" b11 b3 "L" "L" b11 b3 "L" "L" b11 b3 "L" "L" "L" "L" "L" HST CMD "L" HST CMD bit2 "L" b18 b10 b2 "L" b18 b10 b2 "L" b18 b10 b2 "L" "L" "L" "L" "L" PIO NG "L" PIO NG bit1 "L" b17 b9 b1 "L" b17 b9 b1 "L" b17 b9 b1 "L" "L" "L" "L" SOFT RST XFR STOP SOFT RST XFR STOP bit0 "L" b16 b8 b0 "L" b16 b8 b0 "L" b16 b8 b0 "L" "L" "L" "L" HARD RST BLXF RCMP HARD RST BLXF RCMP HADRC -H HADRC -M HADRC -L 2D 2E 2F 30 SLADR -H SLADR -M SLADR -L 31 32 33 34 CADRC -H CADRC -M CADRC -L 35 36 37 38 39 3A 3B CLRINT0 CLRINT1 INTEN0 INTEN1 3C 3D 3E 3F Sub CPU write registers (3) – 44 – CXD1812Q/R REG DRVSTS RAWHDR BFHDR BFSHDR RAWHDR FLG BFHDR FLG ADR 00 01 02 03 04 05 06 bit7 CINT POL b7 b7 b7 MIN UTE MIN UTE bit6 M/S SEL b6 b6 b6 SEC OND SEC OND bit5 M/S EN b5 b5 b5 BLO CK BLO CK bit4 "L" b4 b4 b4 MODE MODE bit3 "L" b3 b3 b3 "H" FILE bit2 RFRS CTL1 b2 b2 b2 "H" CHAN NEL bit1 RFRS CTL0 b1 b1 b1 "H" SUB MODE bit0 "L" b0 b0 b0 "H" DATA TYPE DECSTS0 DECSTS1 XFRMOD XFRSTS0 XFRSTS1 07 08 09 0A 0B 0C 0D SHRT SCT "Z" ENHI NTCT "H" "L" NO SYNC "Z" ENHI NTDT "H" "L" COR INH "Z" EN MDMA "H" AUTO END ERIN BLK "Z" ENDM ABIT "H" "L" COR DONE "Z" PIO SEL "H" PFIF OFUL EDC NG EDC ALL0 AUTO WAIT "H" PFIF OEMP ECC NG C MODE WAIT CYCL1 CBFW RRDY IO TGTN TMET C FORM WAIT CYCL0 CBFR DRDY CoD CHPSTS REV ERROR FEATUR SECTOR COUNT SECTOR NUMBER BYTE CNT-H BYTE CNT-L 0E 0F 10 11 12 13 14 15 "L" "H" "L" "L" "L" "L" "L" "L" "L" "L" MCR DASP "L" ABRT b2 b2 b2 b10 b2 PDIAG "H" EOM b1 b1 b1 b9 b1 "L" "H" ILI DMA b0 b0 b8 b0 SENSE KEY b7 b7 b7 b15 b7 b6 b6 b6 b14 b6 b5 b5 b5 b13 b5 b4 b4 b4 b12 b4 b3 b3 b3 b11 b3 Sub CPU read registers (1) – 45 – CXD1812Q/R REG DRIVE SELECT HOST CMD PACKET CMD ATAPI STS 1 ATAPI STS 2 CSCT ARA CPUBR DT SBCSTS SBQSTS SUBQDT ADR 16 17 18 19 1A 1B 1C 1D 1E 1F 20 bit7 b7 b7 b7 "L" BUSY b7 b7 SBC OVRN "H" b7 bit6 LBA b6 b6 "L" "L" b6 b6 OVER FLOW "H" b6 bit5 b5 b5 b5 bit4 DRV b4 b4 bit3 b3 b3 b3 HST5 HRST b3 b3 "H" "H" b3 bit2 b2 b2 b2 HST1 SRST b2 b2 "H" SHTS BCS1 b2 bit1 b1 b1 b1 bit0 b0 b0 b0 DRDY1 DSC1 CORR b5 b5 BFNT VAL "H" b5 HINT b4 b4 NOSY NC0 "H" b4 DRDY0 DSC0 XHIN TEN b1 b1 "H" NOSY NC1 b1 CHECK b0 b0 SUBQ ERR0 SUBQ ERR1 b0 TGTMIN TGTSEC TGTBLK XFRCNT BFARA# DLARA XFRARA 21 22 23 24 25 26 27 28 b7 "L" "L" b7 b7 b7 b7 b6 b6 b6 b6 b6 b6 b6 b5 b5 b5 b5 b5 b5 b5 b4 b4 b4 b4 b4 b4 b4 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b1 b1 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 b0 b0 HXFRC -H HXFRC -M HXFRC -L 29 2A 2B "Z" b15 b7 "Z" b14 b6 "Z" b13 b5 "Z" b12 b12 "Z" b11 b3 b18 b10 b2 b17 b9 b1 b16 b8 b0 Sub CPU read registers (2) – 46 – CXD1812Q/R REG ADR 2C bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 HADRC -H HADRC -M HADRC -L 2D 2E 2F 30 "L" b15 b7 "L" b14 b6 "L" b13 b5 "L" b12 b4 "L" b11 b3 b18 b10 b2 b17 b9 b1 b16 b8 b0 SLADR -H SLADR -M SLADR -L 31 32 33 34 "L" b15 b7 "L" b14 b6 "L" b13 b5 "L" b12 b4 "L" b11 b3 b18 b10 b2 b17 b9 b1 b16 b8 b0 CADRC -H CADRC -M CADRC -L 35 36 37 38 "H" b15 b7 "H" b14 b6 "H" b13 b5 "H" b12 b4 "H" b11 b3 b18 b10 b2 b17 b9 b1 b16 b8 b0 SADRC -H SADRC -M SADRC -L INTSTS0 INTSTS1 INTEN0 INTEN1 39 3A 3B 3C 3D 3E 3F "L" b15 b7 DEC INT PFIF OFUL DEC INT PFIF OFUL "L" b14 b6 DEC TOUT "L" DEC TOUT "L" "L" b13 b6 DRV OVRN RST CMD DRV OVRN RST CMD "L" b12 b4 SUBC SYNC STS READ SUBC SYNC STS READ "L" b11 b3 "L" HST CMD "L" HST CMD b18 b10 b2 "L" PIO NG "L" PIO NG b17 b9 b1 SOFT RST XFR STOP SOFT RST XFR STOP b16 b8 b0 HARD RST BLXF RCMP HARD RST BLXF RCMP Sub CPU read registers (3) – 47 – CXD1812Q/R 4. HOST Interface The following ATAPI registers are supported. Address HCS0 HCS1 HA2 HA1 HA0 Read (XHRD) Register Write (XHWR) Control block registers 1 1 0 0 1 1 1 1 0 1 Alternate ATAPI Status Diskette Change/Drive Address Command block registers 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ATAPI Status ATAPI Error ATAPI Interrupt Reason Data ATAPI Feature ATA Sector Count ATAPI Device Control Unused ATA Sector Number ATAPI Byte Count Low ATAPI Byte Count High ATAPI Drive Select ATA Command The bit width of all registers excluding the data register is 8 bits. The bit width of the data register is 16 bits. Command block registers The host can read/write to the command block registers only when the BUSY bit (ATAPI status register -bit 7) is low. When the BUSY bit is high, the value of the alternate ATAPI status register is read. 4-1. Data register (read/write) This register is valid only when the DRQ bit (ATAPI status register -bit 3) is high. The bit width of this register is 16 bits. 4-2. ATAPI error register (read) The error status of the command finally executed by the drive is read by this register. bit 7 to 4: SENSE KEY bit 3: MCR (Media Change Requested) bit 2: ABRT (Aborted Command) bit 1: EOM (End Of Media Detected) bit 0: ILI (Illegal Length Indication) 4-3. ATAPI feature register (write) bit 7 to 1: Optional values can be set. bit 0: DMA (optional) Set this bit high for data transfer in the DMA mode. However, the transfer mode is determined by the combination of this bit and the ENDMABIT (bit 4) and PIOSEL (bit 3) bits of the sub CPU transfer mode register (address 09HEX). – 48 – CXD1812Q/R 4-4. ATAPI interrupt reason (read)/ATA sector count (write) register This 8-bytes register can be read/written by both host and sub CPU. bit 1: IO (In or Out) bit 0: CoD (Command or Data) The direction and type of data transfer are determined by the three bits: IO, CoD, and DRQ (ATAPI status register -bit 3). DRQ "H" "H" "H" "H" "L" IO "L" "L" "H" "H" "H" CoD "L" "H" "L" "H" "H" Status of transfer Data transfer from host Packet command transfer from host Data transfer to host RESERVED Data transfer termination status 4-5. ATA sector number register (read/write) This 8-bytes register can be read/written by both host and sub CPU. 4-6. ATAPI byte count low/high register (read/write) This register sets the number of bytes transferred by one data transfer request (DRQ). (16 bits) This register can be read/written by both host and sub CPU. 4-7. ATAPI drive select register (read/write) This 8-bytes register can be read/written by both host and sub CPU. bit 4: DRV This bit allows the host to select the drive. High: Selects the slave drive. Low: Selects the master drive. 4-8. ATAPI status register (read) This register allows the host to read the drive status. The interrupt request signal: HINT to the host is cleared by reading this register. bit 7 BUSY bit 6 DRDY (Drive Ready) bit 4 DSC (Drive Seek Complete) bit 3 DRQ (Data Request) bit 2 CORR (Corrected Data) bit 0 CHECK bit 5, 1: The values set by sub CPU can be read. 4-9. ATA command register (write) This register allows the host to write the ATA command. The interrupt request is applied to sub CPU by writing a command to this register. – 49 – CXD1812Q/R Control Block Registers 4-10. Alternate ATAPI status register (read) This register is identical to the ATAPI status register. However, the interrupt request signal: HINT to the host is not cleared by reading this register. 4-11. ATAPI device control register (write) bit 7 to 3: RESERVED bit 2: SRST This bit is the ATA soft reset bit. (See appendix.) bit 1: nIEN When this bit is set low while a drive is selected, the interrupt request signal: HINT to the host is enabled. When this bit is high or the drive is not selected, the HINT pin generates a high impedance. bit 0: RESERVED 4-12. Diskette change/drive address register (read) bit 7: Hi-Z bit 6 to 2: The values set by sub CPU can be read. bit 1: nDS1 This is low when the slave drive is selected. bit 0: nDS0 This is low when the master drive is selected. – 50 – CXD1812Q/R Appendix: Reset Condition XRST: CRST: HRST: RCMD: SRST: XRST pin CHPCTL0 register (0DHEX) -bit 7 HRST pin ATAPI soft reset command (08HEX) ATAPI software reset 1. Sub CPU write registers REG CONFIG0 CONFIG1 LSTARA LHADR DRVIF XFRFMT0 XFRFMT1 DECCTL0 DECCTL1 XFRMOD XFRCTL0 XFRCTL1 CHPCTL0 CHPCTL1 DISCHG ERROR FEATUR IREASON SECTNO. BYTCNT-H BYTCNT-L DRVSEL HSTCMD ASTS1 ASTS2 UNLOCK CPUBWDT SCTINF ADR 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 19h 1Ah 1Bh 1Ch 1Eh O O O O – 51 – 0 X 0 X 0 X 0 X 0 X 0 0 0 0 0 X XRST O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O CRST O HRST RCMD SRST Bit 7 0 0 X 0 0 0 X 0 1 0 0 X 1 0 X 0 X X 0 0 0 0 0 0 0 0 X 1 1 6 0 0 X 0 0 0 X X 0 X 1 X X X X 0 X 0 0 0 0 0 0 0 0 0 X X X 5 0 1 X 0 0 1 0 0 0 0 0 0 X 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0 X 4 X 0 X 0 0 0 0 X X 0 0 X X 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0 X 3 0 X X 0 0 1 0 0 0 0 1 X 0 X X X X 0 0 0 0 0 0 0 0 0 0 X X 2 0 0 0 0 0 0 0 0 1 X 0 X 0 X X X 1 0 0 0 0 0 0 0 0 0 0 X X 1 0 1 1 0 0 X 0 X 0 X 0 X X 0 0 X 0 X 0 0 0 0 0 0 0 0 0 X X 0 0 X X 0 0 0 X 0 1 X 0 X X 0 0 X X X 0 0 0 0 0 0 0 0 0 0 X CXD1812Q/R REG TGTMIN TGTSEC TGTBLK XFRCNT BFARA DLARA XFRARA HXFRC-H HXFRC-M HXFRC-L HADRC-H HADRC-M HADRC-L SLADR-H SLADR-M SLADR-L CADRC-H CADRC-M CADRC-L CLRINT0 CLRINT1 INTEN0 INTEN1 ADR 21h 22h 23h 24h 25h 26h 27h 29h 2Ah 2Bh 2Dh 2Eh 2Fh 31h 32h 33h 35h 36h 37h 3Ch 3Dh 3Eh 3Fh XRST O O O O O O O O O O O O O O O O O O O O O O O CRST O O O O O O O O O O O O O O O O O O O O O O O HRST RCMD SRST Bit 7 0 0 0 0 0 0 0 X 0 0 X 0 0 X 0 0 X 0 0 0 0 0 0 6 0 0 0 0 0 0 0 X 0 0 X 0 0 X 0 0 X 0 0 0 X 0 X 5 0 0 0 0 0 0 0 X 0 0 X 0 0 X 0 0 X 0 0 0 0 0 0 4 0 0 0 0 0 0 0 X 0 0 X 0 0 X 0 0 X 0 0 0 0 0 0 3 0 0 0 0 0 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 X 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 X 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 – 52 – CXD1812Q/R 2. Sub CPU read registers REG DRVSTS RAWHDR BFHDR BFSHDR RAWHDFG BFHDRFG DECSTS0 DECSTS1 XFRMOD XFRSTS0 XFRSTS1 CHPSTS REV ERROR FEATUR IREASON SECTNO. BYTCNT-H BYTCNT-L DRVSEL HSTCMD PACCMD ASTS1 ADR 00h 01h 02h 03h 04h 05h 07h 08h 09h 0Ah 0Bh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h O O O O O O O O O O O ASTS2 1Ah O O O O O O O O O O O O O O CSCTARA CPUBRDT SBCSTS SBQSTS SBQDT TGTMIN TGTSEC TGTBLK XFRCNT 1Bh 1Ch 1Dh 1Eh 1Fh 21h 22h 23h 24h O O O O O O O O – 53 – O O O O O O O O O O O O O XRST O O O O O O O O O CRST O O O O O O O O O O O O O O O O O O O O O O HRST RCMD SRST Bit 7 0 0 0 0 0 0 0 X 0 X 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 X 1 X 0 0 0 0 6 0 0 0 0 0 0 0 X 1 X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 X 0 0 0 0 5 0 0 0 0 0 0 0 X 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 X 1 X 0 0 0 0 4 0 0 0 0 0 0 0 X 0 X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 X 1 X 0 0 0 0 3 0 0 0 0 1 0 0 X 1 X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 X X 0 0 X 1 X 0 0 0 0 2 0 0 0 0 1 0 1 0 0 X 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 0 0 X 0 X 0 0 0 0 1 1 0 0 0 1 0 0 0 0 X 0 0 X 1 0 0 0 0 0 0 0 0 0 0 1 1 X X 0 0 X 0 X 0 0 0 0 0 0 0 0 0 1 0 0 0 0 X 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 X 0 X 0 0 0 0 CXD1812Q/R REG BFARA DLARA XFRARA HXFRC-H HXFRC-M HXFRC-L HADRC-H HADRC-M HADRC-L SLADR-H SLADR-M SLADR-L CADRC-H CADRC-M CADRC-L SADRC-H SADRC-M SADRC-L ADR 25h 26h 27h 29h 2Ah 2Bh 2Dh 2Eh 2Fh 31h 32h 33h 35h 36h 37h 39h 3Ah 3Bh XRST O O O O O O O O O O O O O O O O O O O CRST O O O O O O O O O O O O O O O O O O O HRST RCMD SRST Bit 7 0 0 0 X 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 0 0 0 X 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 X X 0 0 0 0 0 5 0 0 0 X 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 X X 0 X 1 0 0 4 0 0 0 X 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 X X 0 0 0 0 0 3 0 0 0 X 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X 0 X X 0 0 INTSTS0 3Ch O O O O O O X X 0 0 0 0 0 INTSTS1 3Dh INTEN0 INTEN1 3Eh 3Fh O O O O – 54 – Application Circuit DRAM 39 41 42 26, 27, 30 to 33, 35 to 38 ATAPI bus 43 to 46, 48 to 51 XRAS XCAS XMWR MA0 to 9 LRCK 32 5 2 1 BCLK 57 HA0 to 2 58 60 XHRD 66 CXD1812Q 97 SBIN 98 SCOR HDRQ 68 99 WFCK HINT 62 XS16 61 REDY 64 93 MCLK 94 HCLK DASP 52 XPDI 59 XHWR 67 XHAC 63 100 C2PO HCS0, 1 55 56 MDAT LRCK MDB0 to 7 HDB0 to F 69 to 72 74 to 77 80 to 83 85 to 88 DA16 34 DA15 35 C2PO 44 CXD2500 96 EXCK EXCK 65 PSSL XTSL 30 55 53 XTAI XTL1 XRD XRST XCS XWR A0 to 5 XTL2 95 91 6 92 XINT 7 8 9 10 to 14, 16 17 to 21, 23 to 25 D0 to 7 – 55 – 33.8688MHz subCPU SBSO 64 SCOR 63 WFCK 62 HRST 89 10kΩ CXD1812Q/R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD1812Q/R Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 A 0.65 ±0.12 M + 0.35 2.75 – 0.15 0.15 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 26 (0.22) + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 ∗QFP100-P-1414-A – 56 – 0.5 ± 0.2 A (15.0)