CXD2043

CXD2043Q Digital Comb Filter (NTSC) For the availability of this product, please contact the sales office. Description The CXD2043Q is an adaptive comb filter compatible with NTSC system, and can provide high-precision Y/C separation with a single-chip. Features • Y/C separation by adaptive processing • Horizontal aperture compensation circuit • 8-bit A/D converter (1-channel) • 8-bit D/A converter (2-channel) • Two 1H delay lines • 4-PLL Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) • Supply voltage DVDD VSS – 0.5 to +7.0 V YVDD VSS – 0.5 to +7.0 V CVDD VSS – 0.5 to +7.0 V PVDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Block Diagram 80 pin QFP (Plastic) Recommended Operating Conditions • Supply voltage DVDD 5.0 ± 0.25 YVDD 5.0 ± 0.25 CVDD 5.0 ± 0.25 PVDD 5.0 ± 0.25 • Operating temperature Topr –20 to +75 Structure Silicon gate CMOS IC Applications Y/C separation for color TVs and VCRs V V V V °C DL ADIN 27 A/D 1HDL 1HDL DAC 31 AYO 43 to 48 Y8 to Y1 · 51 · 52 71 VI8 to VI1 to 78 BPF BPF BPF Adaptive Filter Operation DAC 41 ACO 54 to C8 to C1 61 Logic Operation Phase Comparison 4FSC 1/4 VCO 9 FIN 10 CPO 12 VCV Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95812-ST CXD2043Q Pin Configuration XCOE APCN XYOE DVDD DVSS CVSS TST ACO C1 C2 C3 C4 C5 C6 C7 C8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DVSS 65 DVDD 66 40 CVDD 39 CVG 38 CVRF 37 CIRF 36 VB 35 YIRF 34 YVRF 33 YVG 32 YVDD 31 AYO 30 YVSS 29 RT 28 AAVD 27 ADIN 26 AAVS 25 RB TEST 67 TEST 68 TEST 69 BPF 70 VI8 71 VI7 72 VI6 73 VI5 74 VI4 75 VI3 76 VI2 77 VI1 78 ADCO 79 INSL 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol OCLK DVSS DVDD CLKO MCK ADCK CK4 TEST FIN CPO PVSS I/O I — — O I I O I I O — Description Clock amplifier input. Input at 0.8Vp-p or more by eliminating DC components with a capacitor. Digital ground Digital power supply Clock amplifier output. Left open when the clock amplifier is not used. Master clock input Clock input for A/D converter. Input the same clock signal as for Pin 5. 4FSC clock output. Generated from the built-in 4-PLL. Test. Fix to Low. FSC clock input. Input FSC which is burst-locked. Connect to DVss when the PLL is not used. Phase comparison output for the built-in PLL. Left open when the PLL is not used. PLL analog ground –2– CPON ADCK VCEN ADVD OCLK CLKO ADVS TEST TEST TEST TEST DVDD PVDD PVSS DVSS MCK CLPI CPO CRV VCV CK4 ICP FIN GR CXD2043Q Pin No. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Symbol VCV TEST TEST VCEN TEST PVDD CLPI CPON ADVD ADVS ICP CRV GR RB AAVS ADIN AAVD RT YVSS AYO YVDD YVG YVRF YIRF VB CIRF CVRF CVG CVDD ACO CVSS Y8 Y7 Y6 I/O I I I I O — I I — — I I — O — I — O — O — O I I O O I O — O — O O O Description Control voltage input for the built-in VCO oscillation. Connect to PVss when the PLL is not used. Test. Fix to Low. Test. Fix to Low. Built-in VCO oscillation enable. Connect to PVDD when using the PLL. Connect to PVss when the PLL is not used. Test. Left open. PLL analog power supply Clamp pulse input for A/D converter (negative polarity). Connect to DVDD when the clamp is off. High: Clamp function is set to off, and only the normal A/D converter function is enabled. Low: Clamp function is enabled. Digital power supply for A/D converter Digital ground for A/D converter Clamp control voltage Clamp reference voltage input Connect to analog ground. A/D converter reference voltage (bottom) Analog ground for A/D converter Comb filter analog input (A/D converter input) Analog power supply for A/D converter A/D converter reference voltage (top) Analog ground for Y-D/A converter Analog luminance signal output Analog power supply for Y-D/A converter Connect to YVDD via a capacitor of approximately 0.1µF. VRF for Y. Sets the output full-scale value for Y. Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin. Connect to YVss via a capacitor of approximately 0.1µF. Connect a resistor of 16 times (16R) that of the output resistor "R" of ACO pin. VRF for C. Sets the output full-scale value for C. Connect to CVDD via a capacitor of approximately 0.1µF. Analog power supply for C-D/A converter Analog chroma signal output Analog ground for C-D/A converter Digital luminance signal output (MSB) Digital luminance signal output Digital luminance signal output –3– CXD2043Q Pin No. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Symbol Y5 Y4 Y3 DVSS DVDD Y2 Y1 XYOE C8 C7 C6 C5 C4 C3 C2 C1 XCOE I/O O O O — — O O I O O O O O O O O I Digital luminance signal output Digital luminance signal output Digital luminance signal output Digital ground Digital power supply Digital luminance signal output Description Digital luminance signal output (LSB) Digital luminance signal output control High: High impedance Low: Standard output Digital chroma signal output (MSB) Digital chroma signal output Digital chroma signal output Digital chroma signal output Digital chroma signal output Digital chroma signal output Digital chroma signal output Digital chroma signal output (LSB) Digital chroma signal output control. High: High impedance Low: Standard output Aperture compensation switching. High: Aperture compensation ON Low: Aperture compensation OFF Y output through mode. High: Outputs the input composite video signal from the Y output. At this time, there is 1H + 18 clock delay from the input. Low: Y/C separation mode Digital ground Digital power supply Test. Fix to Low. Test. Fix to Low. Test. Fix to Low. High: Fixed to BPF separation Low: Standard mode Digital composite video input (MSB) Digital composite video input Digital composite video input Digital composite video input Digital composite video input Digital composite video input –4– 63 APCN I 64 TST I 65 66 67 68 69 70 71 72 73 74 75 76 DVSS DVDD TEST TEST TEST BPF VI8 VI7 VI6 VI5 VI4 VI3 — — I I I I I I I I I I CXD2043Q Pin No. 77 78 79 Symbol VI2 VI1 ADCO I/O I I I Digital composite video input Digital composite video input (LSB) Description High: Video signals taken in form A/D converter are output from the Y output pins (Y8 to Y1) as 8-bit digital data with a 3.5 clock delay. Low: Normal mode Input switching. High: Digital input Low: Analog input. 80 INSL I –5– CXD2043Q Electrical Characteristics DC Characteristics Item Symbol DVDD AAVD Supply voltage ADVD YVDD CVDD Operating temperature Supply current High level input voltage Low level input voltage High level output voltage Topr IDD VIH VIL VOH Clock 14MHz CMOS level CMOS level IOH = –2mA IOH = –4mA (Pins 4, 7) VOL LVth VIN RFB OCLK (Pin 1) IOL = 4mA IOL = 8mA (Pins 4, 7) — 0.8 250k VDD/2 — 1M — VDD 2.5M V Vp-p Ω VSS — 0.4 — –20 — VDD × 0.7 VSS VDD – 0.8 — — — — — +75 80 VDD VDD × 0.3 VDD V °C mA V V — 4.75 5.0 5.25 V Conditions (VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C) Min. Typ. Max. Unit Low level output voltage Logical Vth Input voltage Feedback resistor AC Characteristics Item Data setup time Data hold time Propagation delay time Clock frequency Symbol (VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C, CL = 20pF) Conditions MCK → VI [8 : 1] MCK → VI [8 : 1] MCK → Y [A : 1] MCK → C [A : 1] — Min. 15.0 10.0 — 14 Typ. — — — 4fsc Max. — — 40 15 Unit ns ns ns MHz tdsu tdh tpd f Pin Capacitance Item Input capacitance Output capacitance Symbol CIN COUT Conditions — — (Ta = 25°C, f = 1MHz, VIN = VOUT = 0V) Min. — — Typ. — — Max. 9 11 Unit pF pF –6– CXD2043Q ADC Characteristics Item Resolution Max. conversion speed Analog input band width Self bias Propagation delay time Differential linearity error Integral linearity error Clamp offset voltage n fmax BW VRB VRT – VRB –3dB Symbol Conditions (VDD = 5V, Ta = 25°C, f = 10MHz) Min. — 14.3 — 0.48 1.96 — –1.0 –3.0 VREF = VRB VREF = VRT –20 –30 Typ. 8 — 18 0.52 2.08 — — — 0 –10 Max. — — — 0.56 2.22 45 +1.0 +3.0 +20 +10 Unit bit MSPS MHz V V ns LSB LSB mV mV tpd ED EL EOC DAC Characteristics Item Resolution Max. conversion speed Differential linearity error Integral linearity error Output full-scale voltage Output full-scale current Output offset voltage n (VDD = 5V, VRF = 2V, IRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz) Symbol Conditions — — — — — — — — ∗1 Min. — 14.3 –0.5 –1.5 1.805 — — 1.8 — Typ. 8 — — — 1.90 9.5 — — 30 Max. — — +0.5 +1.5 1.995 15 1.0 2.1 — Unit bit MSPS LSB LSB V mA mV V pV-s fmax ED EL VFS IFS VOS Precision guaranteed output voltage VOC range Glitch energy ∗1 R = 75Ω, 1Vp-p output GE –7– CXD2043Q Application Circuit for A/D Converter (1) In the case of input clamp pulse directly. 0.01µ ADC Input 47µ 75 29 RT 27 ADIN CLPI 18 CPON 19 ADCK 6 Clamp Pulse 10p 25 RB 0.01µ ADC Clock 20k 23 CRV 22 ICP 0.01µ 24 GR 28 AAVD 0.1µ 26 AAVS ADVD 20 ADVS 21 0.1µ (2) In the case of not using the internal clamp circuit 0.01µ ADC Input 75 29 RT 27 ADIN CLPI 18 CPON 19 ADCK 6 ADC Clock 10p 25 RB 0.01µ 23 CRV 22 ICP 24 GR 28 AAVD 0.1µ 26 AAVS ADVD 20 ADVS 21 0.1µ –8– CXD2043Q Application Circuit for D/A Converter AYO 31 0.1µ 32 YVDD 0.1µ 30 YVSS YVG 33 1k 200 (R) Y OUTPUT YVRF 34 CLOCK 5 MCK YIRF 35 3.3k (R') DVDD VB 36 0.1µ DVSS ACO 41 200 (R) C OUTPUT 0.1µ 40 CVDD CVG 39 0.1µ 42 CVSS CVRF 38 1k CIRF 37 3.3k (R') • Method of Selecting Output Resistance The CXD2043Q has a built-in current output-type D/A converter. To obtain the output voltages, connect resistances to AYO and ACO pins. The voltage and current specifications are: Output full-scale voltage: VFS = 0.5 to 2.0V Output full-scale current: IFS = 0 to 15mA Calculate the output resistance using the relationship VFS = IFS × R. In addition, connect a resistance of 16 times the output resistance to the reference current pin (YIRF, CIRF). In the case where the value comes to be impractical, use a value of resistance as close to the value calculated as possible. Note that, at this time, VFS = VRF × 16R/R' (VRF: Pin voltage of YVRF and CVRF). R is the resistance connected to AYO/ACO, and R' is the resistance connected to YIRF/CIRF. Power consumption can be reduced by using higher resistance values, but then glitch energy and data settling time increase contrastingly. Select optimum resistance values according to the system applications. • VDD, VSS Separate the analog and digital systems around the device to reduce noise effect. YVDD and CVDD are respectively by-passed to YVSS and CVSS as close to each other as possible through ceramic capacitor of approximately 0.1µF. –9– Application Circuit A5V D5V 0.01µ 220 IN GND 3 0.01µ 0.1µ CVRF 10k A5V OUT 1 2 C OUT LPF Y2 C1 Y1 C6 C5 Y3 Y4 Y5 Y6 Y7 Y8 C3 C4 C2 TST C7 C8 DVDD DVSS APCN XCOE XYOE CVSS CVDD 40 CVG 39 CVRF 38 CIRF 37 VB 36 YIRF 35 YVRF 34 0.1µ A5V 220 0.01µ 0.1µ 0.1µ A5V 0.1µ 0.1µ 2 IN 47µ D5V LPF YVG 33 YVDD 32 AYO 31 YVSS 30 RT 29 AAVD 28 ADIN 27 AAVS 26 3.3k 0.1µ 3.3k A5V 65 DVSS 66 DVDD D5V 67 TEST 68 TEST 69 TEST 70 BPF ACO 0.01µ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LPF YVVRF 10k 1 IN OUT GND 3 2 Y OUT 71 VI8 72 VI7 CXD2043Q IC1 73 VI6 OCLK CK4 TEST CPON ADCK VCV CLPI MCK PVSS PVDD CLKO CPO TEST DVDD FIN VCEN DVSS TEST TEST ADVD ADVS ICP CRV GR – 10 – RB 25 56k 560k A5V 0.022µ 0.01µ 0.01µ 10µ VREF 5k 74 VI5 75 VI4 76 VI3 77 VI2 78 VI1 A5V NPN 1 OUT GND 3 VIDEO IN 79 ADCO 80 INSL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0.001µ D5V 0.01µ fsc IN Clamp Pulse IN CXD2043Q Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2043Q Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.2 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 QFP080-P-1420 – 11 – 0.8 ± 0.2 1 24 16.3