CXD2044Q

CXD2044Q Digital Comb Filter (NTSC/PAL/PAL-M/PAL-N) For the availability of this product, please contact the sales office. Description The CXD2044Q is an adaptive intra-field comb filter compatible with NTSC, PAL, PAL-M and PAL-N systems, and can provide high-precision Y/C separation with a single chip. Features • Intra-field Y/C separation by adaptive processing • 8-bit A/D converter (1-channel) • 8-bit D/A converter (2-channel) • Four 1H delay lines • Clock 4fsc Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) • Supply voltage DVDD VSS – 0.5 to +7.0 V AAVD VSS – 0.5 to +7.0 V ADVD VSS – 0.5 to +7.0 V YVDD VSS – 0.5 to +7.0 V CVDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Storage temperature Tstg –55 to +150 °C Block Diagram 80 pin QFP (Plastic) Recommended Operating Conditions 5.0 ± 0.25 • Supply voltage DVDD AAVD 5.0 ± 0.25 ADVD 5.0 ± 0.25 YVDD 5.0 ± 0.25 CVDD 5.0 ± 0.25 • Analog input ADIN • Operating temperature Topr 1.8 –20 to +75 V V V V V Vp-p °C Applications Y/C separation for color TVs and VCRs Structure Silicon gate CMOS IC Analog Vin A/D NTSC: 1H PAL: 2H NTSC: 1H PAL: 2H DL D/A A-Yout Digital Vin 8 Adaptive filter operation 8 D-Yout D/A A-Cout Logic operation 8 D-Cout Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95418-ST CXD2044Q Pin Configuration XYOE CONT TEST DVDD DVss CVss C1 C2 C3 C4 C5 C6 C7 C8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 CIRF CVRF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TEST 65 TEST 66 XCOE 67 APCN 68 RATI 69 NTPL 70 YOT 71 DVss 72 40 CVG 39 ACO 38 XACO 37 CVDD 36 VB 35 YVss 34 YIRF 33 YVRF 32 YVG 31 AYO 30 XAYO 29 YVDD 28 ADVD 27 RT 26 AAVD 25 ADIN DVDD 73 DTR 74 TEST 75 PMN 76 TEST 77 TEST 78 BPF 79 TEST 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol VI8 VI7 VI6 VI5 VI4 VI3 VI2 VI1 I/O I I I I I I I I Description Digital input (MSB). Connect to DVDD or DVss when not in use. Digital input. Connect to DVDD or DVss when not in use. Digital input. Connect to DVDD or DVss when not in use. Digital input. Connect to DVDD or DVss when not in use. Digital input. Connect to DVDD or DVss when not in use. Digital input. Connect to DVDD or DVss when not in use. Digital input. Connect to DVDD or DVss when not in use. Digital input (LSB). Connect to DVDD or DVss when not in use. A/D converter output through mode. High: Video signals taken into the A/D converter (input pin: ADIN) are output without change from the Y output pins as 8-bit digital data with a 3.5 clock delay. Low: Standard mode Input switching. Switches the input data fed to the comb filter. High: Digital input Low: Analog input Clock amplifier input. Input 0.8Vp-p or more, eliminating the DC components with a capacitor. –2– 9 ADCO I 10 INSL I 11 OCLK I XCPON ADCO ADCK OCLK CLKO ADVS AAVS DVss DVDD INSL CLPI MCK CRV ICP VI8 VI7 VI6 VI5 VI4 VI3 VI2 VI1 GR RB CXD2044Q Pin No. 12 13 14 15 Symbol DVSS DVDD CLKO MCK I/O — — O I Digital ground. Digital power supply. (5V) Clock amplifier output. Description Master clock input. Input the 4fsc clock locked to the color burst. Normally, connect the clock amplifier output (CLKO: Pin 14). Clock input for the A/D converter. Input the same clock as the master clock (MCK: Pin 15). Normally, connect the clock amplifier output (CLKO: Pin 14). Clamp pulse input for the A/D converter. Clamps the signal voltage during the low period of the clamp pulse signal. When the clamp function is off, connect to the digital power supply (DVDD). Clamp setting for the A/D converter. High: Clamp function is set to off, and the normal A/D converter function is only enabled. Low: Clamp function is enabled. Digital ground for the A/D converter. Clamp control voltage integral pin. Connect a capacitor of approximately 0.01µF. When not using clamp, connect to the analog ground (AAVS). Clamp reference voltage input. Operates to make the analog input voltage equal to the clamp reference voltage during the clamp period. When not using clamp, connect to the analog ground (AAVS). Reference voltage (bottom): 0.5V (typ.) Guard ring. Connect to the analog ground (AAVS). Analog ground for the A/D converter. Comb filter analog input (A/D converter input). Analog power supply for the A/D converter. (5V) Reference voltage (top): 2.6V (typ.) Digital power supply for the A/D converter. (5V) Analog power supply for the Y D/A converter. (5V) AYO inverted current output. Connect to the analog ground (YVss). Analog luminance signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. Connect a capacitor of approximately 0.1µF. Sets the full-scale value of the analog luminance output signal. Connect a resistor of “16R” (16 times the output resistor “R” of the AYO pin). Analog ground for the Y D/A converter. Connect a capacitor of approximately 0.1µF. Analog power supply for the C D/A converter. (5V) ACO inverted current output. Connect to the analog ground (CVss). –3– 16 ADCK I 17 CLPI I 18 19 20 XCPON ADVS ICP I — I 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 CRV RB GR AAVS ADIN AAVD RT ADVD YVDD XAYO AYO YVG YVRF YIRF YVss VB CVDD XACO I O — — I — O — — O O O I O — O — O CXD2044Q Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Symbol ACO CVG CVRF CIRF CVss Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 DVss DVDD TEST CONT I/O O O I O — O O O O O O O O — — I I Description Analog chroma signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. Connect a capacitor of approximately 0.1µF. Sets the full-scale value of the analog chroma output signal. Connect a resistor of “16R” (16 times the output resistor “R” of the ACO pin). Analog ground for the C D/A converter. Digital luminance signal output (MSB). Digital luminance signal output. Digital luminance signal output. Digital luminance signal output. Digital luminance signal output. Digital luminance signal output. Digital luminance signal output. Digital luminance signal output (LSB). Digital ground. Digital power supply. (5V) Test. Normally open or fix to “Low”. Normally open or fix to “High”. Digital luminance signal output control. High: High impedance Low: Standard output However, during PAL-M/N mode (Pins 70 and 76 are both “High”), the digital chroma signal output is also controlled simultaneously. See Table 1. Digital chroma signal output (MSB). Digital chroma signal output. Digital chroma signal output. Digital chroma signal output. Digital chroma signal output. Digital chroma signal output. Digital chroma signal output. Digital chroma signal output (LSB). Test. Normally open or fix to “Low”. Test. Normally open or fix to “Low”. Digital chroma signal output control. See Table 1. High: High impedance Low: Standard output Aperture compensation circuit setting. High: Compensates for the aperture-induced frequency response characteristics degradation. Even in through mode (YOT: H), aperture compensation is performed for the Y output. Low: Standard mode 56 XYOE I 57 58 59 60 61 62 63 64 65 66 67 C8 C7 C6 C5 C4 C3 C2 C1 TEST TEST XCOE O O O O O O O O I I I 68 APCN I –4– CXD2044Q Pin No. Symbol I/O Description Ratio setting. High: PAL/PAL-M/PAL-N: When DTR: H, compulsively fixed to “Low” internally. Low: NTSC NTSC/PAL/PAL-M/PAL-N mode setting. See Table 1. High: PAL/PAL-M/PAL-N Low: NTSC Y output through mode. High: Outputs the input composite video signal from the Y output. At this time, there is 1H + 15 clock delay from the digital input for NTSC, and 2H + 15 clock delay from the digital input for PAL/PAL-M/PAL-N. For C output, the Y/C separated chroma signal is output. Low: Y/C separation mode Digital ground. Digital power supply. (5V) PAL/PAL-M/PAL-N: High: Dot interference reduction mode Low: Before dot interference reduction NTSC: Fix to “Low”. Test. Normally fix to “Low”. NTSC/PAL/PAL-M/PAL-N mode selection. See Table 1. Test. Normally fix to “Low”. Test. Normally fix to “Low”. Y/C separation processing mode setting. High: Fixed to BPF separation mode Low: Adaptive processing mode Test. Normally fix to “Low”. 69 RATI I 70 NTPL I 71 YOT I 72 73 DVss DVDD — — 74 DTR I 75 76 77 78 79 80 TEST PMN TEST TEST BPF TEST I I I I I I Table 1. NTSC/PAL/PAL-M/PAL-N mode selection (Numbers in parentheses indicate the Pin No.) Mode NTSC PAL PAL-M PAL-N NTPL (70) 0 1 1 1 PMN (76) 0 0 1 1 XCOE (67)∗ 0 0 0 1 ∗ Digital Y output enable and digital C output enable are simultaneously controlled by XYOE (Pin 56) during PAL-M/PAL-N mode. –5– CXD2044Q Electrical Characteristics DC Characteristics Item Symbol VDD AAVD Supply voltage ADVD YVDD CVDD Operating temperature Input/output voltage Input voltage Input rise/fall time Topr VI, VO VIH VIL — — CMOS level input — IOH = –2mA IOH = –4mA IOL = 4mA IOL = 8mA VDD/2 — 0.7VDD 0.3VDD fmax = 50MHz sine wave VIN = Vss or VDD VIN = VSS or VDD VIH = VDD VIL = VSS — 0.8 250k –10 40 –40 3.0 100 –100 9.0 1M 2.5M 10 240 –240 18.0 ns µA V V Vp-p Ω ∗7 ∗8 ∗9 ∗5 ∗6 0.4 0 VDD–0.8 V –20 Vss 0.7VDD 0.3VDD 500 +75 VDD °C V V ns ∗2 ∗3 ∗1 ∗4 ∗5 ∗4 ∗5 — 4.75 5.0 5.25 V ∗1 Measurement conditions (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Min. Typ. Max. Unit Applicable pins tr, tf VOH Output voltage VOL Logical Vth Input voltage Input amplitude Feedback resistance value LVth VIH VIL VIN RFB IIL, IIH Input leak current IIH IIL Clock amplifier output delay ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 ∗9 All pins All pins other than ∗6 All input pins other than ∗6 All output pins other than ∗5 CLKO (Pin 14) OCLK (Pin 11) All pins other than ∗8 and ∗9 Pins 54, 65, 66 and 75 to 80 Pin 55 — –6– CXD2044Q AC Characteristics Input Interface Timing Input Data Tsu Th MCK 0.7VDD Input Characteristics Input pin VI8 to VI1 Pin No. 1 to 8 Min. Tsu 20.00 Th 10.00 Unit ns (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Remarks Rising edge of MCK is used as a reference. Output Interface Timing MCK 0.7VDD Tpd Output Data Output Characteristics Output pin Y8 to Y1 Pin No. 44 to 51 Tpd (output load capacitance 20 [pF]) Max. Min. Max. Min. 25.0 5.00 25.00 5.00 (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Unit ns Remarks Rising edge of MCK is used as a reference. Rising edge of MCK is used as a reference. C8 to C1 57 to 64 ns –7– CXD2044Q Clock Frequency Input pin OCLK, MCK, ADCK Pin No. (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Symbol f Min. — Typ. 4fsc∗1 Max. — Unit MHz 11, 15, 16 ∗1 fsc = 3.58MHz (NTSC), 4.43MHz (PAL) I/O Pin Capacitance Item Input pin capacitance Output pin capacitance Symbol CIN COUT (Ta = 25°C, f = 1MHz, VIN = VOUT = 0V) Min. — — Typ. — — Max. 9 11 Unit pF Internal 8-bit ADC Characteristics Item Resolution Max. conversion speed Analog input bandwidth Self bias Output data delay Differential linearity error Integral linearity error Clamp offset voltage n fmax BW VRB VRT–VRB –3dB Symbol Conditions (VDD = 5V, Ta = 25°C, f = 10MHz) Min. — 18 — 0.48 1.96 — –1.0 –3.0 VREF = VRB VREF = VRT –20 –30 Typ. 8 — 18 0.52 2.08 — — — 0 –10 Max. — — — 0.56 2.22 45 +1.0 +3.0 +20 +10 Unit bit MSPS MHz V V ns LSB LSB mV mV tpd ED EL EOC Internal 8-bit DAC Characteristics Item Resolution Max. conversion speed Differential linearity error Integral linearity error Output full-scale voltage Output full-scale current Output offset voltage Glitch energy ∗2 R = 75Ω, 1Vp-p output n (VDD = 5V, VRF = 2V, RIRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz) Symbol Conditions Min. — 18 –0.8 –2.0 1.805 — — ∗2 — Typ. 8 — — — 1.90 9.5 — 30 Max. — — +0.8 +2.0 1.995 15 1.0 — Unit bit MSPS LSB LSB V mA mV pV-s fmax ED EL VFS IFS VOS GE –8– CXD2044Q Application Circuit for the A/D Converter Block (1) When inputting the clamp pulse directly 0.01µ ADC input 10µ 75 27 RT 25 ADIN CLPI 17 XCLP 18 ADCK 16 Clamp pulse 10p 0.01µ 22 RB 21 CRV 20 ICP 0.01µ 23 GR 26 AAVD 0.1µ 24 AAVS ADVD 28 ADVS 19 ADC clock 20k 0.1µ (2) When not using the internal clamp circuit 0.01µ ADC input 75 27 RT 25 ADIN CLPI 17 XCLP 18 ADCK 16 ADC clock 10p 0.01µ 22 RB 21 CRV 20 ICP 23 GR 26 AAVD 0.1µ 24 AAVS ADVD 28 ADVS 19 0.1µ –9– CXD2044Q Application Circuit for the D/A Converter Block AYO 31 0.1µ 29 YVDD 35 XAYO 30 0.1µ YVSS YVG 32 Y OUTPUT 200 (R) YVRF 33 CLOCK 15 MCK 1K YIRF 34 3.3k (R') VB 36 0.1µ C OUTPUT 200 (R) XACO 38 DVDD DVSS ACO 39 0.1µ 37 CVDD 43 CVSS CVG 40 0.1µ CVRF 41 1K CIRF 42 3.3k (R') • Method of selecting the output resistor The CXD2044Q has a built-in current output type D/A converter. To obtain the output voltages, connect resistors to the AYO and ACO pins. The specs are as follows: output full-scale voltage VFS = 0.5 to 2.0 [V], output full-scale current IFS = 0 to 15 [mA]. Calculate the output resistance value using the relationship VFS = IFS × R. In addition, connect a resistor of 16 times the output resistor to the reference current pin (YIRF, CIRF). In case this results in a non-existent value, use a resistance value as close to the calculated value as possible. Note that, at this time, VFS = VRF × 16R/R' (VRF: Pin voltage of YVRF and CVRF). Here, R is the resistor connected to AYO/ACO, and R' is the resistor connected to YIRF/CIRF. Power consumption can be reduced by using higher resistance values for the R, but the glitch energy and data settling time increase contrastingly. Set the optimum values according to the system applications. • VDD, Vss Separate the analog and digital systems around the device to reduce the effects of noise. YVDD and CVDD are by-passed to YVss and CVss, respectively, as close to each other as possible through ceramic capacitors of approximately 0.1µF. – 10 – Application Circuit : Analog power supply (5V) : Analog ground : Digital power supply (5V) : Digital ground 0.1µ 3.3k 1k Y1 to 8: High impedance Y1 to 8: Standard output TEST DVDD DVss CVss CIRF CVRF CVG 40 0.1µ LPF 0.1µ 200 0.1µ ACO 39 XACO 38 CVDD 37 VB 36 YVss 35 YIRF 34 YVRF 33 YVG 32 0.1µ LPF 0.1µ 200 AYO 31 XAYO 30 YVDD 29 ADVD 28 RT 27 AAVD 26 ADIN 25 75 10p 0.1µ 0.01µ 1k 3.3k XYOE Aperture ON 66 TEST 67 XCOE CONT 65 TEST C1 C2 C3 C4 C5 C6 C7 C8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 (∗1) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 68 APCN C OUT PAL OFF 69 RATI 70 NTPL NTSC Through 71 YOT 72 DVss Normal 73 DVDD 0.1µ 74 DTR 75 TEST DVDD DVss OCLK INSL ADCO VI8 VI7 VI6 VI5 VI4 1 7 8 2 3 4 5 6 9 VI3 VI2 VI1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (∗1) 0.1µ 0.01µ VIDEO IN 0.01µ 10µ 20k 1000p Clock input Clamp pulse input CLKO XCOE (pin67) PAL-N PAL-M PMN (pin76) Digital power supply (5V) Digital ground C1 to 8: High Impedance C1 to 8: Standard output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Digital power supply (5V) CXD2044Q Digital ground MCK ADCK CLPI XCPON ADVS ICP CRV RB GR AAVS – 11 – 76 PMN Y OUT 77 TEST BPF 78 TEST 79 BPF Normal 80 TEST CXD2044Q Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE ∗QFP080-P-1420-A – 12 – 0.8 ± 0.2 1 24 16.3