CXD2131Q

CXD2131Q Video Aspect Ratio Identification Signal Encoder/Decoder For the availability of this product, please contact the sales office. Description The CXD2131Q is an IC that encodes and decodes video aspect ratio identification signal (conforming to EIAJ Standard CPX-1204) in the vertical blanking interval of an NTSC video signal. Features • The processing formerly carried out by the two chips CXA1727Q and CXD2122AQ has been consolidated into this one chip. • Both microcomputer serial interface and I2C interface functions are built in. Applications Wide-screen converters 32 pin QFP (Plastic) televisions, VCRs, MUSE-NTSC Structure Silicon gate CMOS IC Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 • Input voltage VI VSS – 0.5 to VDD + 0.5 • Output voltage VO VSS – 0.5 to VDD + 0.5 • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +70 V V V °C V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Z26-ST CXD2131Q Block Diagram 16 Sync Separator Chip Clamp VIN11 27 CSYC Timing Signal Generator 21 O164 VIN12 28 Pedestal Clamp Data Slicer 14 Decoder 20 2 OLBX 14 VIN21 29 Sync Separator Chip Clamp CRCC Check VIN22 30 Pedestal Clamp Data Slicer Data Validity Criterion CRCC-OK 15 CRCO 10 SROT VALID VCR 4-line Serial Interface 11 XCS 12 SCLK VIN3 31 13 17 14 12 2 2 14 I2C Bus Interface 18 SRIN SCL SDA VOUT 32 Encoder 9 MCON Internal clock 6 7 2 1/4 Frequency Divider 3 4 PRTC/ILBX I164 –2– SELXT XO XI CXD2131Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol AVSS SELXT XO XI VSS I164 PRTC [ILBX] VDD MCON SROT XCS [OE] SCLK [ISEL] SRIN [LNJ1] XRST CRCO CSYC SCL SDA VSS OLBX O164 (DTHI) TST1 TST2 ISET1 ISET2 AVDD VIN11 VIN12 VIN21 VIN22 VIN3 VOUT I/O — I O I — I I — I I/O I I I I O O I I/O — O O I I I I — I I I I I O I/O level ANALOG TTL CMOS CMOS — TTL TTL — TTL TTL∗1 TTL TTL TTL TTL∗2 CMOS CMOS CMOS∗2 CMOS∗2, 4 — CMOS CMOS TTL∗3 TTL∗3 ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG Analog ground. Clock fsc/4 fsc switching; 4 fsc at 1. Oscillator connection (fsc or 4 fsc). Oscillator connection or clock input. Digital ground. Encoder input; 16:9 at 1, 4:3 at 0. Fixed to 0 when not used. Microcomputer interface switching; 0 = I2C, 1 = serial. [Encoder input; 1 = letter-box, 0 = normal]. Digital system power supply. Microcomputer interface exists; 1 = yes, 0 = no. Serial interface output to microcomputer [fixed to 0]. Select from microcomputer [encoding exists; 1 = yes]. Clock from microcomputer [decoder input channel switching]. Data from microcomputer [decoder line ±1 existence]. Standby and reset at 0. CRCC check monitor output. Composite Sync monitor output. I2C bus clock. I2C bus data. Digital ground. Decoder output; 1 = letter-box, 0 = normal. Decoder output; 16:9 at 1, 4:3 at 0 (decode slicer output). Test input; normally connected to Vss; when 1, Pin 21 switches to the function in parentheses ( ). Test input; connect to Vss. Analog bias current setting. Analog bias current setting. Analog system power supply. Sync separation input. Decoder data slicer input. Sync separation input. Decoder data slicer input. Encoder input. Encoder output. Description ∗2 Schmitt input ∗3 With pull-down resistor ∗4 Open drain ∗1 Three-state Note 1) In microcomputer-free mode when MCON = 0, Pin 7 and Pins 10 to 13 switch to the functions in parentheses [ ]. At this time connect SROT (Pin 10) to Vss. Note 2) When TST1 = 1, Pin 21 switches to the function in parentheses ( ). –3– CXD2131Q Electrical Characteristics DC Characteristics (Logic Section) Item Output voltage Symbol VOH VOL VOH VOL VOL VIH VIL VIH VIL VIH VIL II IOZ IDD VIN = either VSS or VDD VIN = either VSS or VDD –10 –40 15 0.8 × VDD 0.2 × VDD +10 +40 0.7 × VDD 0.3 × VDD Condition IOH = –2mA IOL = 4mA IOH = –3mA IOL = 3mA IOL = 4mA 2.2 0.8 VDD/2 VDD/2 0.4 Min. VDD – 0.8 0.4 Typ. (VDD = 5.0V, VSS = 0V, Ta = 25°C) Max. Unit V V V V V V V V V V V µA µA mA Pins 17 and 18 only Except for Pins 4, 10, 22 and 23 Pin 10 only Sum of Pins 8 and 26 Pin 18 only Except for Pins 4, 17 and 18 Pin 4 only Remarks Except for Pins 3 and 18 Pin 3 only Output voltage Output voltage Input voltage Input voltage Input voltage Input leak current Output leak current Current consumption AC Characteristics Item Symbol Condition SELXT (Pin 2) = VSS SELXT (Pin 2) = VDD MCON (Pin 9) = VDD PRTC (Pin 7) = VDD Min. Typ. 3.58 14.3 (VDD = 5.0V, VSS = 0V, Ta = 25°C) Max. 5.0 20.0 10 Unit MHz MHz MHz Remarks Pin 4 input, or oscillator between Pins 3 and 4 Pin 12 Duty ratio = 50% Clock frequency fxi Serial transmission clock frequency fsclk I/O Pin Capacitance Item Input pin Output pin Input/output pins Symbol CIN COUT CI/O Condition VDD = VI = 0V, f = 1MHz VDD = VI = 0V, f = 1MHz VDD = VI = 0V, f = 1MHz Min. Typ. Max. 9 11 11 Unit pF pF pF Remarks –4– CXD2131Q Description of Pins and Electrical Characteristics Analog Section Pin No. Symbol Equivalent circuit AVDD (VDD = 5.0V, VSS = 0V, Ta = 25°C) Description 24 ISET1 24 25 Bias setting pins. Connect to AVDD with 33kΩ. 25 ISET2 AVSS AVDD AVDD Chip clamp, sync separation input. 27 VIN11 27 29 29 VIN21 AVSS AVDD AVSS clamp voltage 1.5V Pedestal clamp, data slicer input. 28 VIN12 28 30 30 VIN22 AVSS AVDD clamp voltage 1.5V 31 31 VIN3 AVSS AVDD Input/output pins for encoder. ON resistance value between Pins 31 and 32: max. 350Ω. 32 32 VOUT AVSS 26 AVDD Not connected to digital power supply (Pin 8) inside the IC. Not connected to digital ground (Pins 5 and 19) inside the IC. –5– 1 AVSS Analog power supply. Connect power supply low in noise from the digital system. Analog ground. Connect to same potential as digital ground (Pins 5 and 19). CXD2131Q 1. Description of video aspect ratio identification signal transfer method (aspect ratio identification) As shown in the table below, video aspect ratio identification signal consists of 14-bit data, to which a 6-bit CRCC is appended for a total of 20 bits. On an NTSC video signal, this information is carried on lines 20 and 283 of the vertical blanking interval. bit-No. 1 2 3 4 5 6 4-bit width 4-bit width Description “1” A WORD0 B WORD1 WORD2 Transfer aspect ratio Pictorial representation format Undefined Full mode (16 : 9) Letter-box “0” 4:3 Normal Discrimination information about the video signal and any other signal (audio signal, etc.) incident to the video and transferred simultaneously. Word 0 dependent discrimination signal Word 0 dependent discrimination signal, information, etc. (From Provisional Standard of EIAJ, CPX-1204) 2. Decoding The CXD2131Q has a decoding function which extracts video aspect ratio identification signals from the video signal. A 1Vp-p video signal is input. There are two video signal input systems, CH1 (Pins 27 and 28) and CH2 (Pins 29 and 30). These are switched and decoded one at a time. As shown below, the decoding circuit and CRCC check circuit are in one system, but there are two systems for the data validity criterion circuit and decoding result, for each channel. This means that even when one channel is being decoded, the decoding result for the other channel is held. ISEL performs channel switching. ISEL is set by microcomputer transmission or by pins. For CH1, ISEL = “0”, and for CH2, ISEL = “1”. CH1/CH2 switching Sync Separator Data Slicer CH1 input Timing Signal Generator 14 Latch 14 Latch Decoding Result Output CH2 input Sync Separator Data Slicer Decode Circuit CRCC Check Data Validity Criterion Data validity Criterion Output Data Validity Criterion CRCC Check Output Further, the composite sync signal of the channel being decoded can be monitored at CSYC (Pin 16) and the CRCC check result can be monitored at CRCO (Pin 15), even during decoding. Also, when TST1 (Pin 22) is held at high level, the data slice result for decoding can be monitored at O164 (Pin 21). For the decoding operation, the range of the scanning lines to be decoded on the video signal can be switched by LNJ1. LNJ1 can be set by microcomputer control or by pins. When LNJ1 is “1”, only lines 20 and 283 are decoded, and when LNJ1 is “0”, one line on each side of lines 20 and 283 are decoded in addition. –6– CXD2131Q 3. Encoding The CXD2131Q has an encoding function which adds video aspect ratio identification signals to the video signal. A 1Vp-p video signal is encoded. An encoded video signal is output on VOUT (Pin 32) by inputting the video signal input to the decoding function CH2 side to VIN3 (Pin 31) as well. When this encoding function is used, decoding input must be switched to CH2. Encoding is controlled by OE, which is set by microcomputer control or by pins. Encoding is off when OE is “0”, and the input video signal is output as it is from VOUT (Pin 32). For example, even when CH1 is decoding, the video signal input to CH2 can be obtained as it is at VOUT if OE is set to “0”. 4. Clock The CXD2131Q requires an fsc (= 3.579545MHz) or 4 fsc clock. When SELXT (Pin 2) is “0” the clock is fsc; when it is “1”, the clock is 4 fsc. Connect XI (Pin 4) and XO (Pin 3) when using a crystal oscillator. Input to XI for external input. 5. Settings and data input/output There are three methods of performing the CXD2131Q settings and data input/output: direct setting by pins without using a microcomputer, the 4-line microcomputer serial interfaces, and I2C bus interface. 5-1. Microcomputer-free mode Direct input/output by pins, without using a microcomputer, can be carried out by setting MCON (Pin 9) to“0”. In this case, only the first 2 bits of the total 14 bits of video aspect ratio identification signals are input or output. The decoding result is obtained at O164 (Pin 21) and OLBX (Pin 20). The data for encoding is input to I164 (Pin 6) and PRTC/ILBX (Pin 7). For the various settings, decode channel switching ISEL is input to SCLK (Pin 12), decode scanning line range switching LNJ1 to SRIN (Pin 13) and encode operation existence OE to XCS (Pin 11). Connect SROT (Pin 10), SCL (Pin 17) and SDA (Pin 18), which are unused, to Vss. 5-2. 4-line serial interface Setting and data input/output can be carried out by microcomputer serial interface when MCON (Pin 9) is set at “1” and PRTC (Pin 7) is set at “1”. In this case, all 14 bits of video aspect ratio identification signals are input or output. Serial data from the microcomputer of serial transmission connects to SRIN (Pin 13), the serial clock to SCLK (Pin 12), and select to XCS (Pin 11). Serial data to the microcomputer is output at SROT (Pin 10). Connect SCL (Pin 17) and SDA (Pin 18), which are unused, to Vss. Serial interface bit configuration is shown in the following figures. –7– CXD2131Q µCOM → CXD2131 2bit 2bit 4bit 4bit 4bit 1bit 1bit 1bit 1bit 1bit 2bit 1bit Total 24 bits WORD0 bit1, bit2 don’t care WORD0 bit3 to bit6 WORD1 WORD2 ISEL IRES OE TEST LNJ1 don’t care SIEN Video aspect ratio identification signals carried on video signal (encoded) Decode input switching Encode ON/OFF Existence of 1 line before and after decode range Validity/invalidity of all setting data; "1" = valid Decode/encode; "1" = circuit reset, not standby Normally "0" CXD2131 → µCOM 2bit 1bit 1bit 4bit 4bit 4bit Total 16 bits WORD0 bit1, bit2 CRCC VALID WORD0 bit3 to bit6 WORD1 WORD2 Video aspect ratio identification signals extracted from video signal (decoded) "1" when CRCC result is correct Video aspect ratio identification signals extracted from video signal (decoded) "1" when data validity criterion result is correct Fig. 1 (a). Bit configuration of 4-line serial interface tzsro XCS tzsro SCLK don’t care SRIN HI-Z HI-Z tsusc thdsc SROT tdsot Item Set-up to SRIN SCLK rising edge Hold to SRIN SCLK rising edge Delay from SROT SCLK falling edge Three-state control delay by SROT XCS Symbol Condition Min. 10 10 Typ. Max. Unit ns ns tsusc thdsc tdsot tzsro Cload = 20pF Rload = 2kΩ 40 40 ns ns Fig. 1 (b). 4-line serial interface timing –8– CXD2131Q 5-3. I2C bus interface Setting and data input/output can be carried out by microcomputer I2C bus interface when MCON (Pin 9) is set at “1” and PRTC (Pin 7) is set at “0”. In this case, all 14 bits of video aspect ratio identification signals are input or output. This I2C bus corresponds to standard mode. I2C address is 40H. I2C bus data connects to SDA (Pin 18) and I2C bus clock to SCL (Pin 17). Connect SRIN (Pin 13), SCLK (Pin 12) and XCS (Pin 11), which are unused, to Vss. And leave SROT (Pin 10) open. I2C bus interface bit configuration is shown in Fig. 2. µCOM → CXD2131 2bit 2bit 4bit 4bit 4bit 1bit 1bit 1bit 1bit 1bit 3bit Total 24 bits WORD0 bit1, bit2 don’t care WORD0 bit2 to bit6 WORD1 WORD2 ISEL IRES OE TEST LNJ1 don’t care Video aspect ratio identification signals carried on video signal (encoded) Decode input switching Encode ON/OFF Existence of 1 line before and after decode range Normally "0" Decode/encode; "1" = circuit reset, not standby CXD2131 → µCOM 2bit 1bit 1bit 4bit 4bit 4bit Total 16 bits WORD0 bit1, bit2 CRCC VALID WORD0 bit3 to bit6 WORD1 WORD2 Video aspect ratio identification signals extracted from video signal (decoded) "1" when CRCC result is correct Video aspect ratio identification signals extracted from video signal (decoded) "1" when data validity criterion result is correct Fig. 2. Bit configuration of I2C bus interface –9– CXD2131Q The CXD2131Q I2C bus interface has a subaddress function. With the subaddress function, only the bytes after setting has started are set. There is no subaddress function at the read side. When subaddress = 0 during setting I2C address Subaddress WORD0 byte 0 WORD1, 2 SEL to LNJ1 byte 1 byte 2 When subaddress = 2 during setting I 2C address Subaddress SEL to LNJ1 byte 2 No subaddress during read I 2C address WORD0 crcc, valid WORD1, 2 Fig. 3. Description of I2C bus and subaddress – 10 – Application Circuit (4-line microcomputer I/F for VCR, with encoder) 39µH 0.1µ 47/16 33k 10k 23 22 JP1 26 25 24 1µ 100 27 1500p 1µ 28 Pedestal Clamp Data Slicer Timing Signal Generator 21 20 19 1µ 100 29 1500p 1µ 30 220 CXD2131Q 31 Encoder Pedestal Clamp Data Slicer Decoder Sync Separator Chip Clamp Sync Separator Chip Clamp 33k VDD = 5.0V 10k 10/16 Vin1 82 15k 510 10k 10/16 18 I2C Bus Interface 17 16 15 14 13 12 VCR 4-line Interface 11 10 To microcomputer SRIN SCLK XCS SROT Vin2 – 11 – 32 5.1k 1 2 510k 22p 22p 3 3.58M 4 5 82 15k 510 33/16 6 7 8 9 Vout 1.1k 110 0.1µ 47/16 Note) JP1 in the figure above normally is not connected. It is only connected when monitoring slicer output from Pin 21, when checking the circuit or the like. CXD2131Q Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Application Circuit (With I2C bus, no encoder) 39µH VDD = 5.0V 0.1µ 47/16 33k 10k 23 22 JP1 26 25 24 1µ 100 27 1500p 1µ 28 Pedestal Clamp Data Slicer Timing Signal Generator 21 20 19 1µ 100 29 1500p 1µ 30 CXD2131Q 31 Encoder Decoder Pedestal Clamp Data Slicer Sync Separator Chip Clamp Sync Separator Chip Clamp 33k 22k 10/16 Vin1 82 33k 1k 22k 10/16 18 I2C Bus Interface 17 16 15 14 13 12 VCR 4-line Interface 11 10 I2C-bus data clock Vin2 – 12 – 32 1 2 3 3.58M 22p 22p 4 5 82 33k 1k 6 7 8 9 0.1µ 47/16 Note) JP1 in the figure above normally is not connected. It is only connected when monitoring slicer output from Pin 21, when checking the circuit or the like. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2131Q CXD2131Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0.1 24 17 + 0.35 1.5 – 0.15 0.1 25 16 32 9 + 0.2 0.1 – 0.1 1 0.8 + 0.15 0.3 – 0.1 8 + 0.1 0.127 – 0.05 0° to 10° 0.24 M PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g – 13 – 0.50 (8.0)