CXD2308Q

CXD2308Q 10-bit 50MSPS RGB 3-channel D/A Converter Description The CXD2308Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel I/O. This is ideal for use in high-definition TVs and high-resolution displays. Features • Resolution 10-bit • Maximum conversion speed 50MSPS • RGB 3-channel I/O • Differential linearity error ±0.5LSB • Low power consumption 500 mW (Typ.) • Single +5 V power supply • Low glitch • Stand-by function Structure Silicon gate CMOS IC 64 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD+0.5 to VSS–0.5 V • Output current (for each channel) IOUT 0 to 30 mA • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V • Reference input voltage VREF 1.8 to 2.0 V • Clock pulse width TPW1,TPW0 9 ns (min.) to 1.1 µs (max.) • Operating temperature Topr –20 to +75 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E92929D01 CXD2308Q Block Diagram 64 DVDD (LSB) R0 R1 R2 1 2 3 6MSB'S CURRENT CELLS LATCHES DECODER CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) 4LSB'S CURRENT CELLS 33 RCK 45 ROR 42 VRR 39 IRR 58 AVDD 59 AVDD 48 VGG 6MSB'S CURRENT CELLS LATCHES DECODER CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) 4LSB'S CURRENT CELLS 34 GCK 47 ROG 43 VRG 40 IRG 54 AVDD 55 AVDD 50 VGB 6MSB'S CURRENT CELLS 60 BO 61 BO 56 GO 57 GO 4LSB'S CURRENT CELLS 62 AVDD 63 AVDD 46 VGR 52 RO 53 RO R3 4 R4 R5 5 6 R6 7 R7 8 R8 9 (MSB) R9 10 (LSB) G0 11 G1 12 G2 13 G3 14 G4 15 G5 16 G6 17 G7 18 G8 19 (MSB)G9 20 (LSB) B0 21 B1 22 B2 23 B3 24 B4 25 B5 26 B6 27 B7 28 B8 29 (MSB) B9 30 DECODER DECODER LATCHES 35 BCK CLOCK GENERATOR CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR 49 ROB 44 VRB 41 IRB 37 VB 38 AVSS BLK 31 CE 32 51 AVSS 36 DVSS —2— CXD2308Q AVss ROR AVss VGG ROB VRG VRR DVss ROG Pin Configuration VGR GCK VGB 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RO 52 RO 53 AVDD 54 AVDD 55 GO 56 GO 57 AVDD 58 AVDD 59 BO 60 BO 61 AVDD 62 AVDD 63 DVDD 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 32 CE 31 BLK 30 B9 (MSB) 29 B8 28 B7 27 B6 26 B5 25 B4 24 B3 23 B2 22 B1 21 B0 (LSB) 20 G9 (MSB) R8 BCK IRG IRR G2 G1 (LSB) G0 (LSB) R0 (MSB) R9 G4 G5 G6 R1 R5 G7 R3 R2 R6 R7 Pin Description and Equivalent Circuit Pin No. 1 to 10 11 to 20 21 to 30 Symbol R0 to R9 G0 to G9 B0 to B9 I/O Equivalent circuit Description Digital input. R0 (LSB) to R9 (MSB) G0 (LSB) to G9 (MSB) B0 (LSB) to B9 (MSB) Blanking input. This is synchronized with the clock input signal for each channel. No signal for High (0 V output). Output generated for Low. Chip enable input. This is not synchronized with the clock input signal. No signal at for High (0 V output) to minimize power consumption. 31 BLK 1 DVDD I to 35 32 CE DVSS 33 34 35 36 RCK GCK BCK DVSS — G3 Clock inputs. Digital ground. —3— G8 R4 RCK VRB IRB VB CXD2308Q Pin No. Symbol I/O Equivalent circuit DVDD Description DVDD 37 VB 37 Connect to DVSS with a capacitor of approximately 0.1 µF. DVSS 38, 51 AVSS — AVDD 45 Analog grounds. 45 47 49 ROR ROG ROB 47 O 49 AVSS Connect to VGR, VGG, and VGB with the control method of output amplitude. See Application Circuit. AVDD 46 48 50 VGR VGG VGB 46 I 48 50 AVSS Connect a capacitor of approximately 0.1 µF. AVDD 39 40 41 IRR IRG IRB 39 O 40 41 AVSS Reference current output. Connect to AVSS with a resistance of 1.2 kΩ. AVDD 42 43 44 VRR VRG VRB I 42 43 44 AVSS Reference voltage input. Set output full-scale value (2.0 V). —4— CXD2308Q Pin No. 52 56 60 53 57 61 54, 55, 58, 59, 62, 63 64 Symbol RO I/O Equivalent circuit AVDD 52 Description Current output. Output can be retrieved by connecting a resistance of 75 Ω to AVSS. GO BO RO 56 60 AVSS AVDD 53 GO BO AVDD DVDD — 57 61 AVSS Reverse current output. Normally connected to AVSS. Analog VDD. Digital VDD. Description of Operation Timing Chart tPW1 tPW0 CLK 1.5V ts th ts th ts th DATA tPD 100% D/A OUT tPD tPD 50% 0% I/O Correspondence Table (output full-scale voltage: 2.00 V) Input code MSB LSB 1111111111 : 1000000000 : 0000000000 Output voltage 2.0 V 1.0 V 0V —5— CXD2308Q Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale ratio ∗1 Output full-scale current Output offset voltage Glitch energy Crosstalk Supply current Analog input resistance Input capacitance Output capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time ∗2 CE disable time ∗2 ∗1 ∗2 Output full-scale ratio = Symbol n FCLK EL ED VOC VFS FSR IFS VOS GE CT IDD ISTB RIN CI CO VIH VIL IIH IIL ts th tPD tE tD (FCLK=50 MHz, AVDD=DVDD=5 V, ROUT=75 Ω, VREF=2.0 V, Ta=25 °C) Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C Endpoint Min. Typ. 10 Max. Unit bit MSPS LSB LSB V V % mA mV pV•s dB mA MΩ 9 RO, GO, BO AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C 50 2.15 0.85 –5 7 3 CE=H→L CE=L→H 10 1 1 2 2 × 100 (%) 5 pF pF V µA ns ns ns ms ms 0.5 –2.0 –0.5 1.8 1.8 1.9 1.9 1.5 27 50 2.0 0.5 2.0 2.0 3 30 1 For the same gain (See the Application Circuit) When data “0000000000” input When 1 kHz sine wave input CE= “L” CE= “H” VGR, VGG, VGB, VRR, VRG, VRB 0 50 54 100 110 1 1 Full-scale voltage for each channel Full-scale voltage average value for each channel When the external capacitors for the VGR, VGG and VGB pins are 0.1 µF. –1 Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current } +5.25V AVDD, DVDD A CXD2308Q V AVSS, DVSS —6— CXD2308Q Maximum Conversion Speed Measurement Circuit 10 bit COUNTER WITH LATCH R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 31 BLK 32 CE 37 VB 0.1µ DVss CLK 50MHZ SQUARE WAVE RO 52 RO 53 GO 56 GO 57 BO 60 BO 61 AVDD 0.1µ 2V 75 AVss 75 AVss 75 AVss OSCILLO SCOPE VGR to VGB 46, 48, 50 ROR to ROB 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 1.2k Setup Time Hold Time Glitch Energy } Measurement Circuit 10 bit COUNTER WITH LATCH R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 31 BLK 32 CE 37 VB RO 52 RO 53 GO 56 GO 57 BO 60 BO 61 AVDD 0.1µ 2V 75 AVss 75 AVss 75 AVss OSCILLO SCOPE DELAY CONTROLLER CLK 50MHZ SQUARE WAVE DELAY CONTROLLER VGR to VGB 0.1µ 46, 48, 50 ROR to ROB DVss 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 1.2k Cross Talk Measurement Circuit ALL “1” DIGITAL WAVEFORM GENERATOR R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 31 BLK 32 CE 37 VB RO 52 RO 53 GO 56 GO 57 BO 60 BO 61 AVDD 75 AVss 75 AVss 75 AVss 0.1µ 2V SPECTRUM ANALYZER CLK 50MHZ SQUARE WAVE VGR to VGB 0.1µ 46, 48, 50 ROR to ROB DVss 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 1.2k —7— CXD2308Q DC Characteristics Measurement Circuit CONTROLLER R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 31 BLK 32 CE 37 VB RO 52 RO 53 GO 56 GO 57 BO 60 BO 61 AVDD 75 AVss 75 AVss 75 AVss 0.1µ 2V DVM CLK 50MHZ SQUARE WAVE VGR to VGB 0.1µ 46, 48, 50 DVss ROR to ROB 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 1.2k Propagation Delay Time Measurement Circuit FREQUENCY DEMULTIPLIER R0 to R9 1 to 10 G0 to G9 11 to 20 B0 to B9 21 to 30 31 BLK 32 CE 37 VB RO 52 RO 53 GO 56 GO 57 BO 60 BO 61 AVDD 75 AVss 75 AVss 75 AVss 0.1µ 2V OSCILLO SCOPE CLK 50MHZ SQUARE WAVE VGR to VGB 0.1µ 46, 48, 50 DVss ROR to ROB 45, 47, 49 33 RCK VRR to VRB 34 GCK 42 to 44 35 BCK IRR to IRB 39 to 41 1.2k —8— CXD2308Q Application Circuit 1.2kΩ (Gain equal) 0.1µF 1kΩ Clock input 0.1µF NC NC NC NC 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ROUT 75Ω 52 53 54 55 GOUT 75Ω 56 57 58 59 BOUT 75Ω 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 32 31 30 29 28 27 26 25 24 23 22 21 20 AVDD AVSS DVDD DVSS B channel input R channel input G channel input (Gain independently) 0.1µF 0.1µF 0.1µF 1kΩ 1.2kΩ 0.1µF Clock input 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ROUT 75Ω 52 53 54 55 GOUT 75Ω 56 57 58 59 BOUT 75Ω 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 32 31 30 29 28 27 26 25 24 23 22 21 20 AVDD AVSS DVDD DVSS B channel input R channel input G channel input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —9— CXD2308Q Notes on Operation • How to select the output resistance The CXD2308Q is a D/A converter of the current output type. To obtain the output voltage connect the resistance to RO, GO and BO pin. For specifications we have: Output full scale voltage VFS=1.8 to 2.0 [V] Output full scale current IFS=less than 30 [mA] Calculate the output resistance value from the relation of VFS=IFS × ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IRR, IRG and IRB. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS=VREF × 16ROUT/RIR. VREF is the voltage set at the VRR, VRG and VRB pins and ROUT is the resistance connected to RO, GO and BO while RIR is connected to IRR, IRG and IRB. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • Power supply and ground To reduce noise effects separate analog and digital systems in the device periphery. For power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as possible to the pin. • Latch up Analog and digital power supply have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. • RO, GO and BO pins The RO, GO and BO pins are the inverted current output pins described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output from RO and RO b) The sum of the currents output from GO and GO c) The sum of the currents output from BO and BO However, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. • Output full-scale voltage For the applications using the RGB signal, the color balance may be broken up when the no-adjusted output full-scale voltage of RO, GO and BO are used. —10— CXD2308Q Latch Up Prevention The CXD2308Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD and DVDD, when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD AVDD +5V +5V C CXD2308Q DVDD C DIGITAL IC AVSS AVSS DVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD AVDD +5V C CXD2308Q DVDD C DIGITAL IC AVSS AVSS DVSS DVSS (ii) DVDD AVDD +5V C CXD2308Q DVDD C DIGITAL IC AVSS AVSS DVSS DVSS —11— CXD2308Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD AVDD +5V +5V C CXD2308Q DVDD C DIGITAL IC AVSS AVSS DVSS DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD AVDD +5V C CXD2308Q DVDD C DIGITAL IC AVSS AVSS DVSS DVSS (ii) DVDD AVDD AVDD +5V CXD2308Q DVDD C DIGITAL IC AVSS AVSS DVSS DVSS —12— CXD2308Q Example of Representative Characteristics 80 70 Crosstalk CT [dB] 60 50 40 AVDD=DVDD=5.0V FCLK=50MSPS VREF=2.0V Ta=25°C ROUT=75Ω RIR=1.2kΩ 100k 1M Output frequency FO [HZ] Output frequency vs. Crosstalk 10M 110 Current consumption IDD [mA] 1.9 AVDD=DVDD=5.0V FCLK=50MSPS VREF=2.0V ROUT=75 Ω RIR=1.2k Ω 100 Full-scale voltage VFS [V] AVDD=DVDD=5.0V FCLK=50MSPS VREF=2.0V ROUT=75Ω RIR=1.2kΩ 1.8 –20 0 25 50 75 –20 0 25 50 70 Ambient temperature Ta [°C] Ambient temperature vs. Current consumption Ambient temperature Ta [°C] Ambient temperature vs. Full-scale voltage —13— CXD2308Q Package Outline Unit : mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 51 33 + 0.1 0.15 – 0.05 0.15 52 32 17.9 ± 0.4 + 0.4 14.0 – 0.1 64 20 + 0.2 0.1 – 0.05 1 1.0 + 0.15 0.4 – 0.1 + 0.35 2.75 – 0.15 0.2 M 0° to10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g —14— 0.8 ± 0.2 19 16.3