CXD2400R

CXD2400R Timing Controller for CCD cameras Description The CXD2400R is a timing controller for CCD camera systems which use the ICX044/045, ICX054/055 or other black/white CCD image sensors. Features • Supports EIA/CCIR standards • Electronic iris (electronic shutter) function • Sync signal generation function • Supports external synchronization • Supports non-interlacing • Supports field/frame∗ accumulation • Oscillator frequency: 1212 fh (EIA: 19.0699MHz; CCIR: 18.9375MHz) ∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation. Absolute Maximum Ratings (Ta = 25°C) Vss – 0.5 to +7.5 V • Supply voltage VDD • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage Vo Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage 5.0V ± 0.25 • Operating temperature –20 to +75 48 pin LQFP (Plastic) Applications CCD cameras Structure Silicon gate CMOS IC V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93308D75-PS Block Diagram LPF ESYNC HPLL VR/SYNC EXT HD 34 44 42 41 33 27 28 19 43 31 6 18 LSEL NIL VD EIA FL/FR VDD1 VDD2 Vss1 Vss2 Vss3 TEST 39 HCOMP LCIN 45 37 40 38 L 46 LCOUT SYNC SEP VR1 TEST CIRCUIT RESET GEN O/E Field/ Frame IRIS/SHUTTER CK GEN GATE 13 XSUB 1/2 1/606 47 12 12fH HD1 CKI 48 1/525 1/625 AVSS 4 H1 CK 2 14 ENB COUNTER TG/SSG D SELECTOR 15 IRENB –2– UP/DOWN ADDER 36 30 29 CLP1 CLP2 FLD CBLK 32 16 24 PS CVss 22 SPDNV /ED2 H2 3 AVDD 1 GATE RG 5 SHP 25 SHD 26 XV1 8 P/S DECODE ED0 ED1 ED2 XV2 7 XV3 10 XV4 12 17 IRIN /ED1 9 11 35 23 21 SPUPV /ED0 CVDD 20 Vreg XSG1 XSG2 SYNC CXD2400R LPF VIDEO SIG. CXD2400R SYNC FL/FR CBLK CLP1 VSS3 CLP2 36 35 34 33 32 31 30 VD 29 28 27 26 SHD FLD EIA HD 25 SHP Pin Configuration (Top View) EXT 37 24 CVSS 23 22 SPUPV/ED0 SPDNV/ED2 HPLL 38 VR/SYNC 39 ESYNC 40 NIL 41 LSEL 42 VDD2 43 TEST 44 HCOMP 45 LCIN 46 LCOUT 47 CKI 48 21 CVDD 20 19 18 17 16 15 Vreg VDD1 VSS2 IRIN/ED1 PS IRENB 14 ENB 13 XSUB 1 2 3 4 5 6 7 8 9 10 11 12 AVDD VSS1 XV1 H1 RG H2 XSG1 XSG2 XV3 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol AVDD H1 H2 AVss RG Vss1 XV2 XV1 XSG1 XV3 XSG2 XV4 XSUB ENB IRENB PS IRIN/ED1 Vss2 VDD1 I/O — O∗2 O∗2 — O∗5 — O O O O O O O I I I I∗1 — — Power supply (for H1, H2) H1 clock output for CCD horizontal register drive H2 clock output for CCD horizontal register drive GND (for H1, H2) Reset gate pulse output GND XV2 clock output for CCD vertical register drive XV1 clock output for CCD vertical register drive CCD sensor charge readout pulse output XV3 clock output for CCD vertical register drive CCD sensor charge readout pulse output XV4 clock output for CCD vertical register drive CCD discharge pulse output XSUB pulse output ON/OFF control (with pull-up resistance) Low: XSUB pulse output stop; high: XSUB pulse output Low: Electronic shutter mode; high: electronic iris mode (with pull-up resistance) Electronic shutter speed input switchover (with pull-up resistance) Low: Serial input; high: parallel input Iris signal input/shutter speed setting; clock input in serial mode. GND Power supply –3– Description AVSS XV2 XV4 CXD2400R Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol Vreg CVDD SPDNV /ED2 SPUPV /ED0 CVss SHP SHD EIA FL/FR CLP2 CLP1 Vss3 FLD VD HD SYNC CBLK EXT HPLL VR/SYNC ESYNC NIL LSEL VDD2 TEST HCOMP LCIN LCOUT CKI I/O — — I∗1 I∗1 — O∗1 O∗1 I I O O — O O O O O O I I I I I — I O∗4 I∗2 O∗3 I∗3 Bias current supply for comparator Power supply (for comparator) Description Shutter speed down reference voltage/ Shutter speed setting; data input in serial mode Shutter speed up reference voltage/ Shutter speed setting; strobe input in serial mode GND (for comparator) Precharge level sample-and-hold pulse Data sample-and-hold pulse Low: EIA; high: CCIR (with pull-down resistance) Field accumulation/frame accumulation, odd field/even field switchover (with pull-down resistance) Pulse output for clamp Pulse output for clamp GND Field identification signal output High: odd field; low: even field Vertical drive output Horizontal drive output Composite sync output Composite blanking output External sync/internal sync identification signal High: external sync; Low: internal sync Horizontal drive signal input (with pull-up resistance) Vertical drive signal input/composite sync input (with pull-up resistance) Low: SYNC sync or internal sync; high: VD/HD sync (with pull-down resistance) Low: interlace mode; high: non-interlace mode (with pull-down resistance) Line number selection pin (with pull-down resistance) Low: EIA 262H/CCIR 312H; high: EIA 263H/CCIR 313H Power supply Fixed to low level (with pull-down resistance) H comparator output LC oscillation (crystal oscillator) inverter input LC oscillation (crystal oscillator) inverter output Clock input I∗1 → Comparater Input I∗2 → OSCILLATOR Cell I∗3 → Input cell with feedback resistance O∗1 → POWERED BUFFER O∗2 → Hdriver Cell O∗3 → OSCILLATOR Cell O∗4 → Phase Comparater O∗5 → RGdriver Cell –4– CXD2400R Electrical Characteristics 1) DC Characteristics Item Supply voltage Symbol VDD Conditions (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Min. 4.75 0.7VDD 0.3VDD 2.0 VDD Typ. 5.0 Max. 5.25 Unit V V V V VIH1 Input voltage 1 (All input pins except those below) VIL1 Input voltage 2 (Pins 22, 23 only in electronic iris mode) Input voltage 3 (Pin 17 only in electronic iris mode) Output voltage 1 (All output pins except those below) Output voltage 2 (Pins 25, 26) Output voltage 3 (Pin 5) Output voltage 4 (Pins 2, 3) Output voltage 5 (Pin 47) Output voltage 6 (Pin 45) Feedback resistance Pull-up resistance Pull-down resistance Current consumption VIN2 VIN3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 RFB RPU RPD IDD IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –8mA IOL = 8mA ICH = –20mA ICL = 20mA IOH = –3mA IOL = 3mA IOH = –4mA IOL = 4mA VIN = Vss or VDD VIL = 0V VIH = VDD VDD = 5V ICX054AL in normal operating state VSS VDD – 0.8 VDD V V 0.4 VDD – 0.8 0.4 VDD – 0.8 0.4 VDD – 0.8 0.4 VDD/2 VDD/2 VDD – 0.8 0.4 250k 25k 25k 1M 50k 50k 36 2.5M 75k 75k V V V V V V V V V V V Ω Ω Ω mA ∗ Power consumption: 180mW typ., ICX054AL load (in normal operating state) 2) Input/output capacitance Item Input pin capacitance Output pin capacitance Input/output pin capacitance Symbol CIN COUT CI/O Min. (VDD = V1 = 0V, fM = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF –5– CXD2400R 3) Comparator characteristics Item Input offest voltage Indefinite region (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Min. Typ. Max. 50 ± 10 5.0V Indefinite region 10mV 10mV Pins 22 and 23 (SPDNV and SPUPV) 10mV 10mV Indefinite region GND Symbol VOS Vf Unit mV mV Note) 1. Input offset voltage and indefinite region Input offset voltage and indefintie region are existed in the comparator which builds in this IC as shown right figure. Note that this when designing external circuit. 2. Pins 22 and 23 for electronic iris mode Use it in this state of Pin 22 (SPDNV) > Pin 23 (SPUPV). 50mV 50mV Input offset voltage Input offset voltage Mode Control Symbol ENB IRENB PS IRIN/ED1 SPDNV/ED2 SPUPV/ED0 EIA FL/FR Pin No. 14 15 16 17 22 23 27 28 I/O I I I I I I I I Field accumulation ESYNC 40 I SYNC sync Internal sync Internal sync HPLL 38 I SYNC sync VR/SYNC NIL LSEL 39 41 42 I I I VD/HD sync Interlace EIA CCIR : : 262H 312H : : : Low XSUB stop Electronic shutter Serial input High XSUB output Electronic iris Parallel input Valid only when ENB is high. Valid only when ENB is high and IRENB is low. Valid only when ENB is high. Remarks Electronic iris control signal input pin (IRENB = high) Shutter speed setting pin (IRENB = Low) EIA Odd field CCIR Even field Frame accumulation∗ VD/HD sync HPLL (Open) VR/SYNC (Open) HPLL (Open) VR/SYNC (SYNC input) HPLL (HD input) VR/SYNC (VD input) Non-interlace EIA CCIR : : 263H 313H Valid only when NIL is high and EXT is low. All other modes. Valid only when EXT is low. Valid only when EXT is low and NIL is high. Switchover between internal and external sync is autonatically identified by input state at Pins 38, 39 and 40. EXT 37 O Internal sync External sync ∗ The characteristics of CCD image sensors are quaranteed for field acccumulation operation. –6– CXD2400R Mode Tables 1) Internal sync mode HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : Open ESYNC pin (Pin 40) : Open Interlace Field readout XSUB pulse OFF∗1 Electronic shutter ON Electronic iris ON O O O Frame readout∗3 O O O Non-interlace Odd field∗2 Field readout O O O Frame readout∗3 × × × Even field∗2 Field readout O O O Frame readout∗3 × × × ∗1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used. ∗2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. ×: Cannot be used. ∗3 The characteristics of CCD image sensors are guaranteed for field accumulation operation. 2) SYNC sync (external sync) mode HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : SYNC input ESYNC pin (Pin 40) : Open Non-interlace Odd field∗2 Field readout × × × Frame readout∗3 × × × Even field∗2 Field readout × × × Frame readout∗3 × × × Interlace Field readout XSUB pulse OFF∗1 Electronic shutter ON Electronic iris ON O O O Frame readout∗3 O O O ∗1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation ∗2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. O: Can be used. ×: Cannot be used. ∗3 The characteristics of CCD image sensors are guaranteed for field accumulation operation. –7– CXD2400R 3) VD/HD sync (external sync) mode HPLL pin (Pin 38) : HD input VR/SYNC pin (Pin 39) : VD input ESYNC pin (Pin 40) : VDD (power supply) VD input with normal cycle Non-interlace VD input with longer cycle than normal interlace Frame Field readout readout∗3 O × × × × × × × Interlace Frame Field readout readout∗3 XSUB pulse OFF∗1 Serial input electronic shutter ON Parallel input electronic shutter ON Electronic iris ON O O O O O O O O Odd field∗2 Frame Field readout readout∗3 O O ∆ O × × × × Even field∗2 Frame Field readout readout∗3 O O ∆ O × × × × ∗1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation ∗2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. ∗3 The characteristics of CCD image sensors are guaranteed for field accumulation operation. O: Can be used. ∆: The shutter speed may change from its value in the interlace mode. ×: Cannot be used. Note) Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than normal are input to the VR/SYNC pin. –8– CXD2400R Electronic Shutter/Iris By setting ENB pin (Pin 14) high, the XSUB pulse is output for a specific period to activate the electronic shutter and electronic iris. 1) Electronic iris (IRENB = high, PS = any level) Symbol IRIN/ED1 SPDNV/ED2 SPUPV/ED0 Pin No. 17 22 23 Iris signal input Shutter speed down reference voltage Shutter speed up reference voltage Function 2) Parallel input electronic shutter (IRENB = low, PS = high) Symbol SPUPV/ED0 IRIN/ED1 SPDNV/ED2 Pin No. 23 17 22 H H H EIA: 1/100 CCIR: 1/120 L H H H L H L L H Mode H H L L H L H L L L L L Shutter speed 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/100000 –9– CXD2400R 3) Serial input electonic shutter (IRENB = low, PS = high) Serial input data format SPDNV/ED2 D7 D6 D5 D4 D3 D2 D1 D0 IRIN/ED1 SPUPV/ED0 The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise. Typical shutter speed EIA Load value 00h 4Eh 6Ah 87h 9Ch ACh CAh EDh shutter speed 1/100000 1/10000 1/5000 1/2000 1/1000 1/500 1/250 1/100 Load value 00h 4Ah 65h 82h 97h A7h C5h E1h CCIR shutter speed 1/80000 1/10000 1/5000 1/2000 1/1000 1/500 1/250 1/120 AC Characteristics SPDNV/ED2 ts2 th2 IRIN/ED1 ts1 ts0 SPUPV/ED0 tw0 Symbol ts2 th2 ts1 tw0 ts0 SPDNV (ED2) setup time for IRIN (ED1) rise SPDNV (ED2) hold time for IRIN (ED1) rise IRIN (ED1) setup time for SPUPV (ED0) rise SPUPV (ED0) pulse width SPUPV (ED0) setup time for IRIN (ED1) rise Min. 20ns 20ns 20ns 20ns 20ns Max. — — — 50µs — – 10 – CXD2400R External Synchronization 1) External/internal sync selection External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. Input pattern EXT pin output Sync state VR/SYNC pin: SYNC signal VR/SYNC pin: VD signal VR/SYNC pin: Open HPLL pin: Open HPLL pin: HD signal HPLL pin: Open ESYNC pin: Open ESYNC pin: VDD (power supply) ESYNC pin: Open High External sync High External sync Low Internal sync Note) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization. 2) Modes for external synchronization Field accumulation Interlace SYNC synchronization O × (Cannot be accomplished since interlace operation is the prior condition.) O O Frame accumulation∗ O × (Cannot be accomplished since interlace operation is the prior condition.) O × (Not practically applicable since the sensitivity is halved.) Non-interlace Interlace VD/HD synchronization Non-interlace ∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation. 3) Reset operation SYNC synchronization The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA, V reset is performed so that the VDO pulse falls at the count of 259H (262.5 – 3.5H) from the fall of the VR1 pulse. For CCIR, it is reset in such a way that the VDO pulse falls at the count of 309H (312.5 – 3.5H). For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. VD/HD synchronization V reset is performed so that the VDO pulse falls 1H later after detecting the fall of the VD (VDR) pulse supplied externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference between the VDR pulse and HDO pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.) – 11 – External Synchronization Reset Operation FIELD. O EIA 9H FIELD. E HDO VDO SYNC HD1 VR1 VDR FIELD. E 9H FIELD. O HDO VDO SYNC HD1 VR1 VDR – 12 – FIELD. O CCIR 7.5H FIELD. E HDO VDO SYNC HD1 VR1 VDR FIELD. E 7.5H FIELD. O HDO VDO SYNC HD1 VR1 CXD2400R VDR TG+SG Timing Chart V derection, EIA FIELD. O 9H 20H FIELD. E HDO VDO SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 493 1 2 3 XV4 491 CCD. OUT 492 CLP1 – 13 – FIELD. E 9H 20H CLP2 FIELD. O HDO VDO SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 1 2 3 4 XV4 492 CCD. OUT 493 CLP1 CXD2400R CLP2 TG+SG Timing Chart V derection, CCIR FIELD. O 7.5H FIELD. E HDO VDO 25H SYNC BLKO 14.5H FLD XSG1 XSG2 XV1 XV2 XV3 2 583 1 3 XV4 581 CCD. OUT CLP1 582 – 14 – FIELD. E 7.5H 25H 14H CLP2 FIELD. O HDO VDO SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 1 2 XV4 582 CCD. OUT 583 CLP1 CXD2400R CLP2 TG+SG Timing Chart H derection, EIA MCK = 104.87ns 104 20 30 40 50 60 70 80 90 100 HD/BLK 10 MCK H1 H2 RG SHP SHD 23 80 32 44 26 38 55 59 36 56 68 73 62 50 94 103 CLP1 7 CLP2 – 15 – XV1 XV2 XV3 XV4 XSUB HSYNC 14 EQ 14 VSYNC 14 FLD 14 VD CXD2400R Black areas show OB output timing of CCD (ICX044/ICX054). TG+SG Timing Chart H derection, CCIR MCK = 105.6ns 59 20 30 40 50 60 70 80 90 100 114 HD/BLK 10 MCK H1 H2 RG SHP SHD 23 84 37 49 31 43 60 59 36 61 73 77 67 55 98 107 CLP1 7 CLP2 – 16 – XV1 XV2 XV3 XV4 XSUB HSYNC 14 EQ 14 VSYNC 14 FLD 14 VD CXD2400R Black areas show OB output timing of CCD (ICX045/ICX055). TG+SG Timing Chart Charge Readout Timing Field accumulation E: EIA 1CK = 104.87ns E: 2.51µs (24CK) C: 2.53µs C: CCIR 1CK = 105.6ns HD XSG1 (12CK) E: 1.26µs C: 1.27µs XSG2 E: 38.38µs (366CK) C: 38.65µs E: 1.57µs (15CK) C: 1.58µs ODD XV1 – 17 – (3CK) E: 0.315µs C: 0.317µs XV2 XV3 XV4 E: 1.99µs (19CK) C: 2.0µs EVEN XV1 XV2 XV3 XV4 CXD2400R TG+SG Timing Chart Charge Readout Timing Frame accumulation E: EIA 1CK = 104.87ns E: 2.51µs (24CK) C: 2.53µs C: CCIR 1CK = 105.6ns HD XSG1 XSG2 E: 39.64µs C: 39.92µs (378CK) ODD XV1 – 18 – (3CK) E: 0.315µs C: 0.317µs XV2 XV3 XV4 EVEN XV1 XV2 XV3 XV4 ∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation. CXD2400R CXD2400R TG+SG Timing Chart ICX054AL 52.4ns (EIA) 52.8ns (CCIR) CK H1 26.2ns (EIA) 26.4ns (CCIR) RG CCD OUT SHP SHD – 19 – TG+SG High-Speed Phase Timing Chart H effective period 1/2H EIA 1.468µs (14CK) 1CK = 104.87ns 1.468µs (14CK) HDO 6.187µs (59CK) BLKO 10.9µs (104CK) HSYNC 4.72µs (45CK) EQ 4.72µs (45CK) 2.3µs (22CK) VSYNC VD FLD – 20 – 1/2H CCIR 1.478µs (14CK) 4.75µs (45CK) 1.478µs (14CK) 1CK = 105.6ns HDO 6.23µs (59CK) BLKO 12.04µs (114CK) HSYNC 4.75µs (45CK) EQ 2.3µs (22CK) VSYNC VD CXD2400R FLD Application 2.2k 47p 100 2.2k 47p 24 50k 37 20 6.8µ /6.3V 2.2k 47p 47p 100 21 25 30 4 29 2.2k 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 CXD2400R 19 /6.3V 38 39 40 0.1µ 42 43 0.1µ 2SC3355 10k 0.15µ 6.8µ /6.3V 44 45 46 1000p 48 33p 1 2 3 4 5 8 9 10 11 12 6 7 13 47 14 15 16 17 18 41 0.1µ 36k 6.8µ 150k 2SC945 270k 50k SYNC IN CXA1310AQ 27 IRIS 3.9k – 21 – 0.1µ 6.8µ/6.3V RG ADJ VSUB ADJ 250K-pixel B/W CCD CXD1250M/N 10k 100k 0.01µ 2.7µH 270p 470 2.2k 1.5µ/25V 7p 7p 0.01µ 1T33C 10p VIDEO OUT CCD OUT CXD2400R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2400R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 (8.0) A 48 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 0.1 ± 0.1 + 0.2 1.5 – 0.1 12 13 (0.22) + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g – 22 – 0.5 ± 0.2