CXD2403AR

CXD2403AR Timing Generator for Color Liquid Crystal Panel Description The CXD2403AR is a timing signal generator for color liquid crystal panel drivers. Features • Generates the LCX003, LCX004 and LCX005 drive pulses • Supports line inversion and field inversion • AC drive for liquid crystal panel during no signal (NTSC/PAL) • Generates timing signal of external sample-andhold circuit • AFC circuit supporting static and dynamic fluctuations • Pulse driver for liquid crystal panel driver (12.0V) Applications Color liquid crystal viewfinders Structure Silicon gate CMOS IC 48 pin LQFP (Plastic) Absolute Maximum Ratings (5V system) (Ta = +25°C, VSS1 = 0V) • Supply voltage VCC –0.3 to +7.0 V • Input voltage VI –0.3 to VDD +0.3 V • Output voltage VO –0.3 to VDD +0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +125 °C Absolute Maximum Ratings (12V system) (Ta = +25°C, VSS3 = 0V) • Supply voltage VEE –0.3 to +20.0 V • Output voltage VO –0.3 to VEE +0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +125 °C Recommended Operating Conditions (5V system) • Supply voltage VDD 2.7 to 5.5 V • Operating temperature Topr –20 to +75 °C Recommended Operating Conditions (12V system) 11.5 to 12.5 V • Supply voltage VEE • Operating temperature Topr –20 to +75 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94421-TE CXD2403AR Block Diagram CKO 39 Master CK 7 8 9 TST0 TST1 TST2 CKI 40 XCLR PLNT SLCK 3 2 6 H-SYNC Detector H-SKEW Detector PLL Phase Comparator 37 RPD 35 XCLP 36 HD Half-H Killer PLL Counter SYNC 27 38 VDD1 41 VSS1 1 N.C. VDD2 5 25 VSS2 13 VEE 24 VSS3 V-SYNC Separator (Noise Shape) N.C. 10 N.C. 11 N.C. 12 N.C. 14 N.C. 15 45 HP1 46 HP2 47 HP3 48 HP4 16 CLR 21 HST 23 HCK1 22 HCK2 31 SH1 32 SH2 N.C. 26 FLDI 28 N.C. 42 N.C. 43 N.C. 44 EN 17 VST 18 VCK1 19 VCK2 20 FLDO 29 VD 30 PAL Pulse Eliminator V-Timing Pulse Generator H-Timing Pulse Generator 33 SH3 Field & Line Controller 4 SLFR 34 FRP –2– CXD2403AR Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VDD2 PLNT XCLR SLFR N.C. SLCK TST0 TST1 TST2 N.C. N.C. N.C. VEE N.C. N.C. CLR EN VST VCK1 VCK2 HST HCK2 HCK1 VSS3 VSS2 N.C. SYNC FLDI FLDO VD SH1 SH2 SH3 FRP XCLP HD RPD VDD1 CKO CKI I/O I I I I — I I I I — — — I — — O O O O O O O O I I — I I O O O O O O O O O I O I Description (H: Pull Up, L: Pull Down) Input Pin for Open Status L H L — L L L L — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 5V system power supply Switches between PAL (High) and NTSC (Low) Reset at 0V Switches between field inversion (High) and line inversion (Low) No connected Switches between LCX003/004 (Low) and LCX005 (High) Test Test Test No connected No connected No connected 12V system power supply No connected No connected CLR pulse output (positive polarity) EN pulse output (negative polarity) V start pulse output (positive polarity) V clock pulse 1 output (positive polarity) V clock pulse 2 output (positive polarity) H start pulse output (positive polarity) H clock pulse 2 output (positive polarity) H clock pulse 1 output (positive polarity) 12V system GND 5V system GND No connected Composite sync input (positive polarity) Field identification signal input ODD (High)/EVEN (Low) Field identification signal output VD pulse output (positive polarity) Sample-and-hold pulse output (positive polarity) Sample-and-hold pulse output (positive polarity) Sample-and-hold pulse output (positive polarity) AC drive timing pulse output Burst position clamp pulse output (negative polarity) HD pulse output (positive polarity) Phase comparator output 5V system power supply Oscillation cell (output) Oscillation cell (input) –3– CXD2403AR Pin No. 41 42 43 44 45 46 47 48 Symbol VSS1 N.C. N.C. N.C. HP1 HP2 HP3 HP4 I/O I — — — I I I I Description 5V system GND No connected No connected No connected Switches for the horizontal display start position Switches for the horizontal display start position Switches for the horizontal display start position Switches for the horizontal display start position Input Pin for Open Status — — — H L L H Electrical Characteristics 1 DC Characteristics (VDD = 5.0V ± 10%) Item Input Applicable Pins SYNC Other than CKO and RPD Symbol VIH VIL IOH IOL IOH IOL IOH IOL II IIL IIH IO2 Measurement Conditions Min. 0.7*VDD VSS Typ. Max. 5.5 0.3*VDD –2.0 –2 Unit V voltage Output current RPD CKO Input leak current Normal input pins Pull-up resistor connected Pull-down resistor connected Output leak RPD (at high imedance state) current VOH = VDD–0.8V VOL = 0.4V VOH = VDD–0.8V VOL = 0.4V VOH = VDD/2 VOL = VDD/2 VIN = VSS or VDD VIN = VSS VIN = VDD VIN = VSS or VDD 4 2 –18 3.0 –2 –240 10 –40 mA –3.0 18 2 –10 240 40 µA Output voltage Output current 12V system output pins 12V system output pins VOH VOL IOH IOUT = –20µA IOUT = 20µA VOH = 11.5V (VEE= 12V) 11.9 — 12.0 0.0 — 0.1 –1.0 V mA Item Current consumption 5V system 12V system Symbol IDD IEE Measurement Conditions Note 1) Note 1) Min. Typ. Max. 25.0 2.0 Unit mA Note: 1. Master clock frequency FCKI = 12MHz, input conditions VIH = VDD, VIL = VSS, no output load. –4– CXD2403AR AC Characteristics (VDD = 5.0V ± 10%) 5V System Applicable Item Pins Clock input cycle High level pulse width Low level pulse width Clock rise time Clock fall time Output rise time Output fall time Output rise delay time Output fall delay time Symbol tck tw (H) tw (L) tr (ck) tf (ck) tr tf tpr tpf Measurement Conditions Min. Typ. Max. Unit 83 30 30 10 10 20 20 70 70 ns CKI Note 4) SH1, SH2 SH3 5V system output pins CL = 10pF CL = 10pF CL = 20pF CL = 20pF 12V System Output rise time Output fall time Cross point time difference Note 2) Output rise delay time Output fall delay time HCK1, SH1 delay time difference HCK2, SH2 delay time difference HCK delay time difference 12V system all Output pins Note 3) VCK1, 2 HCK1, 2 12V system all ouput pins Note 3) HCK1 SH1 HCK2 SH1 HCK1 HCK2 tr tf ∆t ∆t tpLH tpHL dt1 dt2 tH–tL CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 40pF (HCK1, HCK2) CL = 20pF (SH1) Note 5) CL = 40pF 50 80 50 80 15 15 160 180 160 180 125 130 40 ns 80 90 –30 Notes: 2. Applicable to the relationships between HCK1 and HCK2, and VCK1 and VCK2. 3. 12V system output pins : HST, HCK1, HCK2, VST, VCK1, VCK2, EN, CLR. 4. CKI input voltage conditions : The input signal must have the full swing amplitude. 5. Master clock frequency fCKI=8MHz. –5– CXD2403AR Electrical Characteristics 2 DC Characteristics (VDD = 2.7V to 3.6V) Item Input voltSYNC age Note) 4 Output current Other than CKO CKO Normal input pins Pull-up resistor connected Pull-down resistor connected Applicable Pins Symbol VIH VIL IOH IOL IOH IOL II IIL IIH IO2 Measurement Conditions Min. 0.7*VDD VSS VOH = VDD–0.8V VOL = 0.4V VOH = VDD/2 VOL = VDD/2 VIN = VSS or VDD VIN = VSS VIN = VDD VIN = VSS or VDD 1.0 –8.0 0.75 –2 –240 5 –40 Typ. Max. 5.5 0.3*VDD –1.1 –0.7 8.0 2 –3 240 40 Unit V mA Input leak current µA Output leak RPD (at high imedance state) current Output voltage Output current 12V system output pins 12V system output pins VOH VOL IOH IOL IOUT = –20µA IOUT = 20µA VOH = 11.5V (VEE= VOL = 0.5V 12V) 11.9 — 1.0 12.0 0.0 — 0.1 –1.0 V mA Item Current consumption 5V system 12V system Symbol IDD IEE Measurement Conditions Note 1) Note 1) Min. Typ. Max. 25.0 2.0 Unit mA Notes: 1. Master clock frequency FCKI = 12MHz, input conditions VIH = VDD, VIL = Vss, no output load. 4. CKI input voltage conditions : The input signal must have the full swing amplitude. –6– CXD2403AR AC Characteristics (VDD = 2.7V to 3.6V) 5V System Item Clock input cycle High level pulse width Low level pulse width Clock rise time Clock fall time Output rise time Output fall time Output rise delay time Output fall delay time Applicable Pins Symbol tck tw (H) tw (L) tr (ck) tf (ck) tr tf tpr tpf Measurement Conditions Min. Typ. Max. Unit 83 30 30 10 10 30 30 200 200 ns CKI Note 4) SH1, SH2 SH3 5V system output pins CL = 10pF CL = 10pF CL = 20pF CL = 20pF 12V System Output rise time Output fall time Cross point time difference Note 2) Output rise delay time Output fall delay time HCK1, SH1 delay time difference HCK2, SH2 delay time difference HCK delay time difference 12V system all Output pins Note 3) VCK1, 2 HCK1, 2 12V system all ouput pins Note 3) HCK1 SH1 HCK2 SH1 HCK1 HCK2 tr tf ∆t ∆t tpLH tpHL dt1 dt2 tH–tL CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 10pF CL = 40pF CL = 40pF (HCK1, HCK2) CL = 20pF (SH1) Note 5) CL = 40pF 50 80 50 80 15 15 200 250 200 250 145 145 40 ns 80 90 –30 Notes: 2. Applicable to the relationships between HCK1 and HCK2, and VCK1 and VCK2. 3. 12V system output pins : HST, HCK1, HCK2, VST, VCK1, VCK2, EN, CLR. 4. CKI input voltage conditions : The input signal must have the full swing amplitude. 5. Master clock frequency fCKI = 8MHz. –7– CXD2403AR Timing Definition for 5V System Pins VDD Data input 0V tCK tW (H) 100% CKI 100% 100% VDD 0% 0% tW (L) 0% 0V tr (CK) tf (CK) VDD 90% 5V system output 10% tr tpr 0V VDD 90% 5V system output tf tpf 10% 0V –8– CXD2403AR Timing Definition for 12V System Pins VDD CKI 0V 90% 12V system output 10% tPLH tr VEE 0V 90% 12V system output 10% tPHL tf VEE 0V VEE 50% VCK1 (HCK1) VCK2 (HCK2) 50% 50% 0V Dt Dt 50% 0V VEE t CKI t t – tL = 2(t – t1) tH = t – t1 + t2 tL = t – t2 + t1 tH – tL = 2(t2 – t1) 50% HCK1 (HCK2) t1 tH t2 50% 50% tL SH1 50% 50% dt1 dt2 –9– CXD2403AR Description of Functions The structure of liquid crystal panel driven by this IC is shown below. Liquid Crystal Panel Structure Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW B R B R B R B R B R B R G G G G G G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G 480 R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R 218 10 2 B R B R B R B 2 473 5 LCX003 Basic Specifications Total number of horizontal pixels Number of horizontal display pixels Total number of vertical pixels Number of vertical display pixels Total number of pixels Number of display pixels (A line) (B line) (A line) (B line) : : : : : : : : 479H 480H 473H 473H 230H 218H 110285 103114 –10– 230 CXD2403AR Liquid Crystal Panel Structure Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW B R B R B R B R B R B R G G G G G G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G 480 R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R 260 6 2 B R B R B R B 2 473 5 LCX004 Basic Specifications Total number of horizontal pixels Number of horizontal display pixels Total number of vertical pixels Number of vertical display pixels Total number of pixels Number of display pixels (A line) (B line) (A line) (B line) : : : : : : : : 479H 480H 473H 473H 268H 260H 128506 122980 –11– 268 CXD2403AR Liquid Crystal Panel Structure Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW G B G B G B G B G B R R R R R B G B G B G B G B G R B R B R B R B R B G R G R G R G R G R B G B G B G B G B G R B R B R B R B R B G R G R G R G R G R B G B G B G B G B G R B R B R B R B R B G R G R G R G R G R B G B G B G B G B G R B R B R B R B R B G R G R G R G R G R B G B G B G B G B G R B R B R B R B R B G R G R G R G R G R B G B G B G B G B G R 2 R R 218 222 R R 2 1 525 3 521 LCX005 Basic Specifications Total number of horizontal pixels : Number of horizontal display pixels : Total number of vertical pixels Number of vertical display pixels Total number of pixels Number of display pixels : : : : 525H 521H 222H 218H 116550 113578 –12– CXD2403AR Horizontal Direction Output Pulse The picture display timing of horizontal direction is as follows. The horizontal start position is offset by two clocks in 16 different ways with the HP1 to 4 pins. Effective Pixel Display Timing (for the LCX003) 10.9µs (110fH) 52.6 (528fH) 63.5µs (638fH) SYNC BLK 1.5µs (15fH) HST 4.76µs (48fH) Effective interval 9µs (90.5fH) Picture display interval 47.1µs 2.75µs (27.5fH) (473fH) 2.75µs (27.5fH) Horizontal Start Position Concept Horizontal scan interval 63.5µs = 638ffH Blanking and SYNC SYNC BLK 47.6µs (48fH) 10.9µs 110fH 1.5µs (15fH) Picture display interval 47.1µs = 473fH 2 2 473 Display interval 10 218 4 BLK 110fH Interval from sync signal to picture display Picture display starts (528–473)/2 = 27.5fH later from the end of BLK. Therefore, picture display starts 11 – 15 + 27.5 = 122.5fH later. 473fH (Picture display interval) 27.5fH 27.5fH Interval from HST to picture display First two bits are masked. 5fH HST HCK1 HCK2 Therefore, the interval between HST and display start is 6 clocks. Interval from the center of sync signal to HST. Add time delayed four bits of sync separation circuit. 110-15-26+27.5-6-4=90.5fH ( 9.0µs)µs Black mask –13– CXD2403AR Variable Range from the Center of Sync Signal to Hst Rise Timing HP4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HP3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HP2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HP1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 108CLK (10.7µs) 106CLK 104CLK 102CLK 100CLK 98CLK 96CLK 94CLK (9.4µs) 92CLK 90CLK 88CLK 86CLK 84CLK 82CLK 80CLK 78CLK (7.8µs) HP1 to HP4 pins can be used to vary the interval from the center of sync signal to HST rise as shown in the left table. Internal preset: NTSC (typ.): PAL (typ.): 1001 (90CLK) 1001 (90CLK) 1000 (92CLK) Liquid Crystal Panel Driving Pulse Generation HST, HCK1, HCK2, VST, VCK1, and VCK2 (EN, CLR in LCX005 mode only) are generated for the liquid crystal panel driver. Low. Polarity is not specified for each field. The point is changed from VCK1 and VCK2 pulse change points after 1 clock. HD-Clamp Pulse Generation HD pulse is output during horizontal BLK in order to drive the backlight (fluorescent tube). Even during no signal, raster screen with no screen noise can be created synchronizing to the free running frequency. XCLP is output for BF timing clamp pulse. External Sample-and-Hold Pulse Generation Timing pulses of external sample-and-hold circuit SH1, SH2, and SH3 are generated. AC Driving Pulse Generation FRP is output for liquid crystal AC driving. Field inverts when F/H input pin is High and line inverts when SYNC BLK 1.5µs 4.7µs 10.9µs 2.7µs HD XCLP 6.1µs 1.4µs 1.3µs 6.5µs 2µs –14– CXD2403AR Pulse Timing Chart (for the LCX003) Clock (638fH) Display start HST HCK1 HCK2 VCK1,2 SH1 SH2 SH3 RESET position FRP * In accordance with the layout of picture elements on LCD panel, timings between the adjacent lines and fields are offset accordingly. 1.5 bit offset pulse → HST, HCK1, HCK2, SH1, SH2, SH3, CLR 1 bit offset pulse → VCK1,VCK2, FRP, EN –15– 589 31 51 81 599 609 619 629 1 11 21 41 61 71 91 CLK 638 SYNC HD XCLP RPO FPO ODD LINE HST HCK 1 HCK 2 SH3 SH1 SH2 FRP 1st FIELD* 2nd FIELD* VCK 1 VCK 2 HRST 2 (Internal clock2) LCX003/004 Horizontal Direction Timing Chart — NTSC, PAL (HPOS-1001) –16– HRST 2 (Internal clock2) HRST 1 (Internal clock1) EVEN LINE HST HCK 1 HCK 2 SH3 SH1 SH2 FRP 2nd FIELD* 1st FIELD* VCK 1 VCK 2 HRST 1 (Internal clock1) *FRP polarity is not specified for each field. Notes ) Signals for the timing interval from input SYNC changes with HST according to horizontal start position settings (HP1 to HP4) : HCK1, HCK2, SH1, SH2, SH3, FRP, VCK1, VCK2 Constant signals regardless of the horizontal start position settings (HP1 to HP4) : SYNC, HD, XCLP CXD2403AR CXD2403AR LCX003 Vertical Direction Timing Chart — NTSC 123 4 1 23 4 (Field inversed mode) (Output pulse) SYNC VCK2 VCK1 XCLP HST FRP FRP VRST (Internal pulse) FLO VST BLK Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins. HD VD –17– VD CXD2403AR LCX004 Vertical Direction Timing Chart — PAL 1 234 1 23 4 (Field inversed mode) (Output pulse) SYNC VCK2 VCK1 XCLP HST VRST (Internal pulse) FLO VST FRP FRP BLK HD Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins. VD –18– VD 653 31 51 81 702 633 693 673 683 1 11 21 41 61 71 91 101 CLK SYNC BLK HD XCLP ODD LINE HST HCK 1 HCK 2 SH1 SH2 SH3 ODD FIELD EVEN FIELD FRP VCK 1 VCK 2 LCX005 Holizontal Direction Timing Chart — NTSC, PAL (HP=1001) –19– ODD FIELD CLR EN (PAL) 1.5fh EVEN LINE HST HCK 1 HCK 2 SH1 SH2 SH3 FRP EVEN FIELD VCK 1 VCK 2 CLR EN (PAL) CXD2403AR CXD2403AR CXD2403AR LCX005 Vertical Direction Timing Chart — NTSC 1234 1234 (Field Inversed mode) (Output pulse) (Internal pulse) SYNC VCK1 XCLP VRST VCK2 FRP HST FRP VST BLK Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins. –20– FLO HD VD VD CLR EN (H) LCX005 Vertical Direction Timing Chart — PAL HD 2.5H 2.5H 1 22 25H 288 15 314 14H 2.5H 15 VD 2.5H 2.5H 2.5H SYNC BLK 25H 4.5H 1 1 2 3 4 5 6 7 8 1 2 3 4 5 61 2 3 4 5 6 7 8 12345678 234 VST 600 Display start Display start 1234 1 2 3 4 5 6 7 81 2 3 4 5 6 1 2 3 VCK1 VCK2 12345678 FRP –21– ODD FIELD HST EN CLR FRP (1F inversed) FLD VD (Output pulse) VRST (Internal pulse) EVEN FIELD Note) The second row of the timing chart 'VD' is a pulse indicated as a reference and is not a pulse output from pins. CXD2403AR CXD2403AR Driving for No Signal HST, HCK1, HCK2, FRP, VCK1, VCK2, XCLP, HD, VD, and VST are made to run free so that the liquid crystal panel is AC driven even when there is no composite sync from the SYNC pin. The PLL counter is made to run free because the HSYNC separation circuit stops. In addition, the auxiliary V counter is used to create the reference pulse for generating VD and VST because the VSYNC separation circuit is also stopped. The period of the V counter is 269H for NTSC and 321H for PAL, and if there is no VSYNC during 269H/321H, it is assumed to be a no signal state. The RPD pin is kept at high impedance so that the AFC circuit does not cause phase errors by phase comparison. AFC Circuit (638/702 fh clock generation) A fully synchronized AFC circuit is built in. PLL error detection signal is generated at the following timing. SYNC RPD 2.5V 0V 4.7µs 5V Center of SYNC The phase comparison output of the entire bottom of SYNC and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter. Then the outputs change the vari-cap capacitance and the oscillating frequency is stabilized at 638 fh in LCX003/1004 or 702 fh in LCX005. Example of PLL Related Peripheral Circuit 1k 37 RPD 3.3µ 10k + 3300pF +12V 10k 100k 0.01µ 100pF L value LCX003/004 → 8.2µ LCX005 → 6.8µ 33k 1000pF 40 CKI 1T369 L *The parameters of the elements are reference. 39 CKO Parts : Vari-cap 1T369 (Sony), MA365 (Matsushita) Adjustment Method 1. Adjust the voltage for vari-cap with the variable resistor connected to 12V power supply while checking HSYNC and RPD waveforms with an oscilloscope. Concretely, adjust so that the RPD rise is at the center of HSYNC. 2. When PLL is still not locked, change the L of the LC oscillations. –22– CXD2403AR HSYNC Separation HSYNC is separated from the composite sync input. Noise is eliminated with the counter and equivalent pulse is eliminated with the half H killer. HSYNC jumping detection and address management when jumping occurs frequently (matching the number of H in a field) are also performed. PLL SYNC H-DET Noise Elimination Half H-Kill H Counter H Control Circuit AFH (Internal pulse) (Matching the number of H) SKEW DET V. SYNC Separation Noise Shape V-RESET Pulse Generate V-Reset pulse (internal pulse) SYNC V-SYNC Separation Circuit V. sync is separated from the composite sync input connected to SYNC connector. The serration pulses are removed as noise. When considerable pulse width is detected, the V reset pulse is output to notify V sync input and to synchronize timing of output signals. When a V sync having different pulse width from normal one is input, it can be separated when the width of serration pulse is narrower than 2~3 µsec or less which is positioned right after the V sync having 0.5H width during A~F period. V-SYNC Period 190µs A SYNC NOISE SHAPE START Tolerance ± 0 to 1.0µs NOISE SHAPED PULSE NOISE SHAPE END NOISE SHAPE MODE Recovery period 15µs B C D E F V-SYNC Decision Period 125µs When the pulse enters in this period, twice the pulse time width is added. V-RESET PULSE V-SYNC Input Time Axis Specification –23– CXD2403AR Application Circuit (for driving the liquid crystal panel LCX003) Backlight driver circuit AC conversion circuit (R, G, B driver) Sample-and-hold circuit (R, G, B driver) R, G, B driver RGB decoder HD 36 XCLP 35 FRP 34 SH3 33 SH2 32 SH1 31 VD 30 3.3µ 10k + 1k 3300pF 0.01µ 10k 100k 100pF 37 RPD 38 VDD 33k 1000pF 39 CKO 40 CKI 41 VSS N.C. 42 N.C. N.C. 43 N.C. N.C. 44 N.C. 45 HP1 46 HP2 47 HP3 48 HP4 N.C. 26 VSS 25 VSS2 24 HCK1 23 HCK2 22 HST 21 VCK2 VCK1 VST EN CLR N.C. 20 19 18 17 16 N.C. N.C. N.C. N.C. + FLDO 29 29 FLDI 28 SYNC 27 N.C. +5.0V LCD panel 8.2µ 3 XCLR 4 SLFR 15 N.C. 14 VDD2 13 5 N.C. 6 SLCK N.C. 7 TST0 N.C. 8 TST1 N.C. 9 TST2 N.C. 10 N.C. N.C. 11 N.C. 1 VDD 2 PLNT N.C. 12 N.C. +12V +5.0V N.C. N.C. + PAL NT Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. –24– N.C. +12V + + 5.0V CXD2403AR Package Outline Unit : mm 48PI LQ FP ( N PLASTI ) C 9. 0}0. 2 * 7. 0}0. 1 +0. 2 1. 0. 5- 1 0. 1 36 25 37 24 i8. 0j A 48 13 1 0. 5}0. 1 +0. 08 0. 0. 18- 03 0. 08 M 12 0 +0. 5 1 0 02 0. 27- . 0. 1}0. 1 0K- 10K D ETAI A L 5}0. 2 0. N O TED i m ensi g on hdoes not i ude m ol pr r on. ncl d otusi PAC KAG E STR U C TU R E PAC KAG E M ATER I AL EPO XY R ESI N SO LD ER PLATI G N 42 ALLO Y 0. 2 SO N Y C O D E EI C O D E AJ JED EC C O D E LQ FP48PL121 LQ FP048- 0707PAX LEAD TR EATM EN T LEAD M ATER I AL PAC KAG E W EI H T G –25– 5}0. 2 0.