CXD2422R

CXD2422R CCD Camera Timing Generator Description The CXD2422R generates the timing pulses required for driving and signal processing CCDs with 480,000 pixels (EIA, effective pixels) and CCDs with 570,000 pixels (CCIR, effective pixels). Features • EIA and CCIR compatible • Compatible with component digital and composite digital recording format • Compatible with field/frame accumulation modes Applications CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX062/063AL 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +75 V °C Block Diagram SDO D1 D2 D3 VD 5 51 1 SD 30 SC 31 LD 32 9 Shift Register 13 Latch 4 2 3 4 HD 6 39 XSG1 D0 V latch 38 XSG2 44 XV1 43 XV2 Shutter data HTSG 58 FLD/FRM 61 EIA/CCIR 62 MODE 63 Reset High-speed Pulse Generation Circuit 42 XV3 Output F.F. 41 XV4 Latch Pulse Generation Circuit 35 XSUB 26 HCLP1 22 HCLP2 21 VCLP XH gate Internal clock CLKI 33 28 PBLK Delay Delay 27 PBLKON 34 14 15 16 18 19 20 54 53 52 37 36 7 CLKO SHP XRG BCO BAO SHD Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. BBO –1– XH1 XH2 CLK BAI BBI BCI E94Y30-ST CXD2422R Pin Configuration TEST11 TEST10 TEST9 TEST8 XSG2 XSUB XSG1 CLKO 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 CLKI VSS XH1 XV3 XH2 XV1 XV2 XV4 NC NC SDO BCO BCI XRG VSS VDD NC HTSG 49 50 51 52 53 54 55 56 57 58 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LD SC SD TEST7 PBLK PBLKON HCLP1 TEST6 VDD VSS HCLP2 VCLP BBO BBI SHD NC RST 59 TEST12 FLD/FRM 60 61 EIA/CCIR 62 MODE 63 TEST13 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D3 TEST2 TEST4 TEST1 TEST3 SHP CLK BAI D0 –2– TEST5 BAO D1 VD VSS D2 HD CXD2422R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol D0 D1 D2 D3 VD HD CLK VSS TEST1 TEST2 TEST3 TEST4 TEST5 SHP BAI BAO (NC) SHD BBI BBO VCLP HCLP2 VSS VDD TEST6 HCLP1 PBLKON PBLK TEST7 SD SC LD CLKI CLKO XSUB XH2 XH1 I/O O O O O I I O — I I I I I O I O — O I O O O — — I O I O I I I I I O O O O Test input (normally High). (With pull-up resistor) Horizontal (OPB block) clamp pulse output. Output ON/OFF of PBLK. (High: ON) (With pull-up resistor). Preblanking pulse output. Test input (normally High). (With pull-up resistor) Serial data input for electronic shutter control. (With pull-up resistor) Clock input for electronic shutter control. (With pull-up resistor) Latch pulse input for electronic shutter control. (With pull-up resistor) Clock input. Inversed output of CLKI. Substrate pulse output for electronic shutter. Clock output for horizontal register drive. Clock output for horizontal register drive. –3– CCD output signal level sampling pulse output. Buffer input (for phase adjustment of SHD). (With pull-up resistor) Non-inversed output of BBI. Vertical clamp pulse output. Horizontal (dummy bit block) clamp pulse output. Test input (normally Low). (With pull-down resistor) Test input (normally Low). (With pull-down resistor) Test input (normally Low). (With pull-down resistor) Test input (normally Low). (With pull-down resistor) Test input (normally Low). (With pull-down resistor) CCD output precharge level sampling pulse output. Buffer input (for phase adjustment of SHP). (With pull-up resistor) Non-inversed output of BAI. Extended I/O output. Extended I/O output. Extended I/O output. Extended I/O output. Vertical sync signal input. (With pull-up resistor) Horizontal sync signal input. (With pull-up resistor) Two frequency divider output of Pin 33. Description CXD2422R Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol XSG2 XSG1 VSS XV4 XV3 XV2 XV1 TEST8 TEST9 TEST10 TEST11 (NC) (NC) SDO BCO BCI XRG VSS VDD (NC) HTSG RST TEST12 FLD/FRM EIA/CCIR MODE TEST13 I/O O O — O O O O O O O O — — O O I O — — — I I I I I I I Description Sensor charge readout pulse output. Sensor charge readout pulse output. Clock output for vertical register drive. Clock output for vertical register drive. Clock output for vertical register drive. Clock output for vertical register drive. Test output (normally open). Test output (normally open). Test output (normally open). Test output (normally open). Serial data output for electronic shutter control. Non-inversed output of BCI. Buffer input (for phase adjustment of XRG). (With pull-up resistor) Reset gate pulse output of output block. Readout pulse (XSG1, 2) ON/OFF. (High: OFF) (With pull-down resistor) Test input (normally High). (With pull-up resistor) Test input (normally Low). (With pull-up resistor) High: Field accumulation mode, Low: Frame accumulation mode. (With pull-up resistor) High: EIA, Low: CCIR. (With pull-up resistor) High: Component digital mode, Low: Composite digital mode. (With pull-up resistor) Test input (normally Low). (With pull-up resistor) Note) TEST12 and TEST13 have a built-in pull-up resistor. Be sure to fix them at Low. –4– CXD2422R Electrical Characteristics 1) DC characteristics Item Supply voltage Symbol VDD Conditions (VDD = 4.5 to 5.5V, Topr = –20 to +75°C) Min. 4.5 VSS 0.7VDD 0.3VDD IOH = –2mA IOL = 4mA VIL = 0V, VIH = VDD 40k 100k VDD – 0.8 0.4 250k Typ. 5.0 Max. 5.5 VDD Unit V V V V V V Ω Input/Output voltages VI, VO Input voltage VIH VIL VOH VOL RPU, RPD Output voltage Pull-up/ Pull-down resistors 2) AC characteristics 2)-1. Pulses for electronic shutter control (SD, SC, LD) SD ts1 tH1 SC tw1 ts2 t H2 LD tw2 Symbol Item SD set-up time, activated by the rising edge of SC SD hold time, activated by the rising edge of SC SC pulse width SC set-up time, activated by the rising edge of LD SC hold time, activated by the rising edge of LD LD pulse width Min. 20ns 20ns 20ns 20ns 20ns 20ns ts1 tH1 tw1 ts2 tH2 tw2 –5– CXD2422R 2)-2. HD/VD take-in characteristics HD, VD 1.6V 1.6V CLK 0.7VDD ts3 th3 (VDD = 4.5 to 5.5V, Topr = –20 to +75°C) Symbol Definition HD/VD set-up time, activated by CLK HD/VD hold time, activated by CLK Min. 4 0 Typ. Max. Unit ns ns ts3 th3 2)-3. Field discrimination characteristics VD 1.6V VD 1.6V tpd1 HD HD tpd1 When the HD logic level is Low tpd1 after VD falls, the field is discriminated as an ODD (EVEN with CCIR) field. When the HD logic level is High tpd1 after VD falls, the field is discriminated as an EVEN (ODD with CCIR) field. (VDD = 4.5 to 5.5V, Topr = –20 to +75°C) Symbol Definition Field discriminating clock phase, activated by the falling edge of VD Min. 890 Typ. Max. Unit ns tpd1 –6– CXD2422R 2)-4. CLKO, CLK, XH1, XH2, XRG, SHP, SHD phase characteristics CLKI tpd3 tpd2 CLK tpd4 tpd7 XH1 tpd6 tpd8 tpd9 tpd11 XRG tpd10 tpd12 SHP tpd13 tpd15 tpd14 tpd5 CLKO XH2 SHD (VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF) Symbol Definition CLKO falling delay time against CLKI CLKO rising delay time against CLKI CLK2 falling delay time against CLKI CLK2 rising delay time against CLKI XH1 falling delay time against CLKI XH1 rising delay time against CLKI XH2 rising delay time against CLKI XH2 falling delay time against CLKI XRG falling delay time against CLKI XRG rising delay time against CLKI SHP rising delay time against CLKI SHP falling delay time against CLKI SHD falling delay time against CLKI SHD rising delay time against CLKI Min. 3.5 4.0 5.2 6.5 5.2 6.4 5.7 5.3 4.7 5.2 8.1 7.9 7.9 8.6 Typ. 6.2 7.2 9.3 11.6 8.8 11.4 10.2 9.4 8.4 9.2 14.4 14.1 14.1 15.2 Max. 12.1 14.1 18.3 22.8 17.2 22.4 20.3 18.5 16.5 18.1 28.3 27.6 27.6 29.8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 tpd15 –7– CXD2422R Phases of SHP, SHD, and XRG pulses can be adjusted using on-chip buffers. Internal CXD2422R SHP 15 R C BAI 16 BAO 17 SHP Delay times of SHP, SHD, and XRG can be adjusted with C and R. Delay characteristics of on-chip buffers (VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF) Symbol Definition Rising delay time from BAI to BAO Falling delay time from BAI to BAO Rising delay time from BBI to BBO Falling delay time from BBI to BBO Rising delay time from BCI to BCO Falling delay time from BCI to BCO Min. 4.0 2.8 4.0 3.0 4.3 3.4 Typ. 7.1 5.5 7.0 5.4 7.6 6.0 Max. 13.9 10.7 13.8 10.7 15.0 11.7 Unit ns ns ns ns ns ns tpd16 tpd17 tpd18 tpd19 tpd20 tpd21 3) I/O pin capacitances Item Input pin capacitance Output pin capacitance Symbol CIN COUT Min. (VDD = VI = 0V, f = 1MHz) Typ. Max. 9 11 Unit pF pF –8– CXD2422R Description of Operation 1) Mode setting Symbol EIA/CCIR Pin No. 62 Low CCIR Composite digital mode Clock (CLKI) input EIA 35.79545MHz (2275fH = 10fsc) CCIR 35.46895MHz (2270+8/625fH = 8fsc) Frame accumulation XSG1 and XSG2 pulses are output. PBLK is fixed at High. High EIA Component digital mode Clock (CLKI) input EIA 36MHz (2288fH) CCIR 36MHz (2304fH) Field accumulation XSG1 and XSG2 pulses are fixed at High. (Readout suspended) PBLK pulse is output. MODE 63 FLD/FRM HTSG PBLKON 61 58 27 –9– CXD2422R 2) Inputting serial data The accumulation time of the electronic shutter is controlled by external serial data. Input pins (SD, SC, and LD) are used to input serial data. SD: Serial data input SC: Clock input LD: Latch pulse input The following is the serial data timing chart. SD D3 D2 D1 D0 S8 S7 S6 S5 S4 S3 S2 S1 S0 SC LD D3 to D0: Not related to the accumulation time of the electronic shutter. Data are output to D3 to D0 pins after converted into parallel data and being latched at LD. S8 to S0: Sdata is set in 9-bit binary with S8 as MSB (High: 1, Low: 0). ON/OFF of the electronic shutter and the accumulation time are determined by Sdata. The calculation on the next page is for the accumulation time in each mode. The data for SD are input to the internal 13-bit shift register, and the data can be retrieved as serial data at SDO pin. Note) The electronic shutter might operate from turning power on to inputting serial data. To prevent this operation, process RST and LD pins as shown in the following figures. Be careful, however, as serial data cannot be received before the voltage at RST rises. VDD RST 59 (with pull-up resistor) 1000p LD 32 (with pull-up resistor) 4.7k – 10 – CXD2422R Accumulation time of electronic shutter EIA/ CCIR Sdata 0 to 261 EIA 262 263 to 511 0 to 311 CCIR 312 313 to 511 Accumulation time (s) {(261 – Sdata)/15734} + 1/25678 (Component digital mode) {(261 – Sdata)/15734} + 1/25532 (Composite digital mode) Input prohibited Electronic shutter OFF {(311 – Sdata)/15625} + 1/25678 (Component digital mode) {(311 – Sdata)/15625} + 1/25299 (Composite digital mode) Input prohibited Electronic shutter OFF The Sdata values corresponding to representative shutter speeds are listed below. Shutter speed 1/100 1/125 1/250 1/500 1/1000 1/2000 Sdata EIA 104 (068h) 136 (088h) 199 (0C7h) 230 (0E6h) 246 (0F6h) 254 (0FEh) CCIR 155 (09Bh) 187 (0BBh) 249 (0F9h) 280 (118h) 296 (128h) 304 (130h) – 11 – CXD2422R 3) Latch pulse timing Various mode switchings and shutter data are taken in by field. The latch pulse timing is as follows (The broken lines show timing in the EVEN FIELD.): EIA VD HD VLT1 VLT2 IT VLT3 XSG1,2 CCIR VD HD VLT1 VLT2 IT VLT3 XSG1,2 Latch pulse VLT1 VLT2 VLT3 Latched data EIA/CCIR, MODE, HTSG Shutter data (S8 to S0) FLD/FRM – 12 – CXD2422R Example of System Configuration Phase Comparator LPF VCO 36MHz (Component digital) 35.79545MHz (Composite digital, EIA) 35.56895MHz (Composite digital, CCIR) EXTfH External sync signal SYNC HD VD MODE1 15 14 13 26 INTfH Electronic shutter serial data Separation of fV fH and fV fH 19 20 33 XH1, 2 1/2 Frequency Division Pulse Generation Circuit XRG XSUB XV1 to 4 XSG1, 2 SHP, SHD HCLP1, 2 VCLP PBLK CXD2422R (TG) To signal processing circuit To each driver CLK 38 Frequency Division/ Pulse Generation Circuit HD 41 VD 42 5 6 7 CXD8302Q Note) 1. Either SYNC or VD/HD is used as external sync signal. When SYNC is used (SYNC synchronous mode), fix MODE1 to High; when VD/HD is used (VD/HD Synchronous mode), fix MODE1 to Low. 2. Be sure to do phase comparison of the falling edge of EXTfH and INTfH for SYNC synchronous mode. – 13 – Timing Chart (1) EIA vertical direction VD BLK HD 5 10 15 20 270 265 275 280 520 XV1 XV2 XV3 XV4 – 14 – ∗1 ∗2 2468 13579 XSG1 (525) 0 260 ∗1 XSG2 XSUB 285 ∗2 VCLP HCLP1 HCLP2 PBLK 494 493 1357 2468 CCD OUT 491 493 494 492 ∗1 These pulses are not output during frame accumulation. CXD2422R ∗2 These pulses are output at the position determined by shutter data. Timing Chart (2) CCIR vertical direction VD BLK HD 5 15 10 20 25 310 320 325 620 315 330 XV1 XV2 XV3 XV4 XSG1 ∗1 XSG2 (625) 0 1 ∗1 ∗2 ∗2 XSUB VCLP HCLP1 HCLP2 PBLK CCD OUT 1357 24 68 580 582 581 581 582 CXD2422R ∗1 These pulses are not output during frame accumulation. ∗2 These pulses are output at the position determined by shutter data. 335 2468 13579 – 15 – Timing Chart (3) EIA horizontal direction, Component digital mode fH = 1144 128 HD 0 BLK 0 130 150 20 50 100 0 (1144) 40 70 60 110 120 90 140 CLK 10 30 XV1 75 70 85 55 90 130 95 80 60 XV2 XV3 65 XV4 XSUB 80 – 16 – 47 53 55 VCLP 2 HCLP1 15 HCLP2 138 160 164 PBLK XH1 136 XH2 XRG SHP CXD2422R SHD 160 164 170 Timing Chart (4) EIA horizontal direction, Composite digital mode fH = 1137.5 128 HD 0 BLK 0 120 0 (1137.5) 40 160.5 60 110 90 130 10 30 20 50 80 CLK XV1 75 70 85 80 90 60 XV2 55 XV3 65 95 XV4 XSUB 70 100 130 157.5 – 17 – 47 53 55 VCLP 2 HCLP1 15 HCLP2 131 140.5 153.5 PBLK 150.5 157.5 XH1 129 XH2 XRG SHP CXD2422R SHD 170.5 Timing Chart (5) CCIR horizontal direction, Component digital mode fH = 1152 128 HD 0 BLK 0 0 (1152) 110 140 80 10 30 20 50 100 120 130 150 160 40 60 70 CLK XV1 75 70 85 80 90 130 60 XV2 55 XV3 65 95 XV4 XSUB – 18 – 47 53 55 VCLP 2 90 172 HCLP1 15 HCLP2 146 168 PBLK 172 XH1 144 XH2 XRG SHP CXD2422R SHD 170 Timing Chart (6) CCIR horizontal direction, Composite digital mode fH = 1135 128 HD 0 BLK 0 120 0 (1135) 40 70 60 110 90 140 80 10 30 20 50 CLK XV1 75 70 85 80 90 60 XV2 55 XV3 65 95 XV4 – 19 – 47 53 55 XSUB 100 130 130 155 VCLP 2 HCLP1 15 HCLP2 129 151 PBLK 150 155 XH1 127 XH2 XRG SHP CXD2422R SHD 160 170 Timing Chart (7) Readout interval 0 850 0 50 900 950 50 100 750 800 CLK = 1144 1152 1135 100 (EIA, Component digital) (CCIR, Component digital) (CCIR, Composite digital) 1137.5 (EIA, Composite digital) HD 128 128 XSG1 786 921 831 XSG2 876 – 20 – 60 75 70 759 759 65 90 80 85 60 75 70 80 759 65 759 XV1 60 75 XV2 966 70 85 80 EIA: ODD CCIR: EVEN 55 XV3 65 90 XV4 XV1 XV2 85 80 EIA: EVEN CCIR: ODD 55 XV3 90 966 XV4 CXD2422R CXD2422R Timing Chart (8) High-speed pulse timing CLK XH1 XH2 XRG SHP SHD – 21 – CXD2422R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 48 49 10.0 ± 0.1 33 32 A 64 1 0.5 ± 0.08 16 + 0.2 1.5 – 0.1 17 (0.22) + 0.08 0.18 – 0.03 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 ∗QFP064-P-1010-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.3g – 22 – 0.5 ± 0.2 (11.0)