CXD2424R

CXD2424R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2424R is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features • CCIR support • Electronic shutter function • Random trigger shutter function • Sync signal generator • Supports external synchronization • Supports non-interlaced operation • Base oscillation 1888fh (29.5MHz) Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX075AL, ICX075AK 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 • Operating temperature Topr –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95306-PS CXD2424R Block Diagram XCPOB XCPDM REND REVH SYNC OCTL WEN RDM VDO HDO O2FH PBLK EXT BLK HDI VDI FLD RM CLD 47 46 45 44 43 42 41 39 38 37 36 59 58 61 60 57 54 53 51 50 49 ID CL RG 11 XH1 13 XH2 14 XSHP 28 XSHD 29 XRS 30 XV1 26 XV2 25 G A T E TG OUTPUT CONTROL 63 62 VRI HRI V-CONTROL PULSE GENERATOR H-DECODER 1/472 V-DECODER 1/625 20 TEST1 XV3 22 XSG 27 XHHG1A 15 XHHG1B 16 XHHG2 17 XVOG 18 XVHOLD 19 DECODE TEST CIRCUIT 1/2 COUNTER 21 TEST2 31 TEST3 32 48 35 TEST4 TEST8 TEST7 34 TEST6 33 TEST5 NC GATE 52 64 1 2 8 10 3 4 5 6 7 9 12 23 24 40 55 56 CKI OSCO SMD1 Vss PS OSCI TRIG XSUB ED0 ED1 Vss VDD Vss Vss 29.5MHz –2– SMD2 ED2 VDD CXD2424R Pin Configuration XCPDM XCPOB TEST8 48 CL CLD O2FH 49 50 51 47 46 45 44 43 42 41 40 39 38 37 36 35 TEST7 34 33 32 TEST4 31 TEST3 30 XRS 29 XSHD 28 XSHP 27 XSG 26 XV1 NC 52 FLD BLK 53 54 VSS 55 VDD 56 CXD2424R (G/A) TEST6 REND OCTL RM TEST5 25 XV2 24 VDD 23 VSS 22 XV3 21 TEST2 20 TEST1 19 XVHOLD 18 XVOG 17 XHHG2 16 PBLK RDM REVH WEN SYNC 57 HDI 58 VDI 59 HDO VDO 60 61 HRI 62 VRI CKI 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS ID SMD1 XSUB TRIG EXT XH1 OSCO SMD2 XH2 PS –3– XHHG1A XHHG1B ED1 OSCI ED0 ED2 Vss RG CXD2424R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol OSCO OSCI PS ED0 ED1 ED2 SMD1 Vss SMD2 TRIG RG XSUB XH1 XH2 XHHG1A XHHG1B XHHG2 XVOG XVHOLD TEST1 TEST2 XV3 Vss VDD XV2 XV1 XSG XSHP XSHD XRS TEST3 TEST4 TEST5 TEST6 TEST7 I/O O I I I I I I — I I O O O O O O O O O O O O — — O O O O O O O O O O I Inverter output for oscillation. Inverter input for oscillation. Switching for electronic shutter speed input method. (With pull-down resistor) Low: Parallel input, High: Serial input Shutter speed setting. Strobe input for serial mode. (With pull-up resistor) Shutter speed setting. Clock input for serial input. (With pull-up resistor) Shutter speed setting. Data input for serial input. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) GND Shutter mode setting. (With pull-up resistor) Trigger input for random trigger shutter. Reset gate pulse output. CCD discharge pulse output. Clock output for CCD horizontal register drive. Clock output for CCD horizontal register drive. Clock output for transfer between CCD horizontal registers. Clock output for transfer between CCD horizontal registers. Clock output for transfer between CCD horizontal registers. Clock output for transfer from CCD vertical register to CCD horizontal register. Clock output for adjusting timing of transfer to CCD horizontal register. Test output. Normally open. Test output. Normally open. Clock output for CCD vertical register drive. GND Power supply. Clock output for CCD vertical register drive. Clock output for CCD vertical register drive. CCD sensor charge readout pulse output. Precharge level sample-and-hold pulse. Data sample-and-hold pulse. Sample-and-hold pulse. Test output. Normally open. Test output. Normally open. Test output. Normally open. Test output. Normally open. Test input. Set at Low in normal operation. (With pull-down resistor) Description –4– CXD2424R Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol EXT REND REVH OCTL Vss RDM RM XCPDM XCPOB PBLK ID WEN TEST8 CL CLD O2FH NC FLD BLK Vss VDD SYNC HDI VDI HDO VDO HRI VRI CKI I/O I I I I — I I O O O O O I O O O — O O — — O I I O O I I I Field pulse output. Composite blanking output. GND Power supply. Composite sync output. Horizontal sync signal input. Vertical sync signal input. Horizontal sync signal output. Vertical sync signal output. Horizontal reset signal input. Vertical reset signal input. 2 fck clock input. Description Internal synchronization/external synchronization switching. (With pull-down resistor) Low: Internal synchronization, High: External synchronization Normal reset/direct reset switching. (With pull-down resistor) Low: Normal reset, High: Direct reset V reset/HV reset switching. (With pull-down resistor) Low: V reset, High: HV reset O2FH output control. (With pull-down resistor) Low: No output, High: Output GND Normal operation/random trigger shutter switching. (With pull-down resistor) Low: Normal operation, High: Random trigger shutter Switching for output mode. (With pull-down resistor) Low: Non-interlaced, High: Interlaced Clamp pulse output. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Write enable output. Test input. (With pull-down resistor) fck clock output. (0°) fck clock output. (180°) 2 fH output. –5– CXD2424R Electrical Characteristics DC Characteristics Item Supply voltage Input voltage 1 (Input pins other than those below) Input voltage 2 (Pins 7, 9, 10, 58, 59, 62, 63, and 64) Output voltage 1 (Output pins other than those below) Output voltage 2 (Pins 28, 29, 30, 31, 32, 33, 34, 49 and 50) Output voltage 3 (Pins 11, 13, and 14) Output voltage 4 (Pin 1) Feedback resistor Pull-up resistor Pull-down resistor Current consumption Symbol VDD VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RFB RPU RPD IDD IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –12mA IOL = 12mA IOH = –12mA IOL = 12mA VIN = Vss or VDD VIL = 0V VIN = VDD Conditions (VDD = 4.75 to 5.25V, Topr = –20 to +75°C) Min. 4.75 0.7VDD 0.3VDD 0.7VDD 0.3VDD –0.8 0.4 –0.8 0.4 VDD – 0.8 0.4 VDD/2 VDD/2 250k 1M 50k 50k 40 2.5M Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V V V Ω Ω Ω mA VDD = 5V ICX075AL in normal operating state I/O Pin Capacitances Item Input pin capacitance Output pin capacitance Symbol CIN COUT Min. — — (VDD = V = 0V, fM = 1MHz) Typ. — — Max. 9 11 Unit pF pF –6– CXD2424R AC Characteristics 1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD tCK CK Vpp/2 tpd1 tpd2 0.7VDD 0.3VDD tpd3 tpd4 0.7VDD tpd6 0.7VDD tpd7 tpd8 XH1 RG 0.3VDD tpd5 XSHP 0.3VDD XSHD 0.3VDD tpd9 0.7VDD tpd10 0.7VDD XRS tpd11 0.3VDD tpd12 CL 0.7VDD 0.3VDD tpd14 tpd13 CLD 0.3VDD 0.7VDD (VDD = 5.0V, Topr = 25°C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF) Symbol Definition CK cycle XH1 rising delay, activated by the falling edge of CK XH1 falling delay, activated by the falling edge of CK RG falling delay, activated by the rising edge of CK RG rising delay, activated by the falling edge of CK XSHP falling delay, activated by the rising edge of CK XSHP rising delay, activated by the falling edge of CK XSHD falling delay, activated by the rising edge of CK XSHD rising delay, activated by the falling edge of CK XRS falling delay, activated by the falling edge of CK XRS rising delay, activated by the rising edge of CK CL falling delay, activated by the rising edge of CK CL rising delay, activated by the rising edge of CK CLD falling delay, activated by the rising edge of CK CLD rising delay, activated by the falling edge of CK –7– Typ. 35 8 9 11 15 18 18 20 11 17 15 32 0 26 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tpd1 tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 CXD2424R Waveform Characteristics of XH1 and RG 0.9VDD XH1 0.1VDD tfH1 trH1 0.9VDD RG 0.1VDD trRG tfRG (VDD = 5.0V, Topr = 25°C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF) Symbol Definition XH1 rise time XH1 fall time RG rise time RG fall time Typ. 2 3 2 2 Unit ns ns ns ns trH1 tfH1 trRG tfRG –8– CXD2424R • In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp2 tp3 tp1 fH tp4 tp5 fH L: ODD H: EVEN VDO 1 309.5H ODD VDO 2 309.5H EVEN Symbol Definition Range of resetting to ODD Range of resetting to EVEN Range of resetting to ODD Prohibited area Prohibited area Specified value 22.0 31.8 9.8 200 200 Unit µs µs µs ns ns tp1 tp2 tp3 tp4 tp5 –9– CXD2424R • In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp2 tp3 tp1 fH tp4 tp5 fH L: ODD H: EVEN VDO 1 EVEN VDO 2 ODD Symbol Definition Range of resetting to ODD Range of resetting to EVEN Range of resetting to ODD Prohibited area Prohibited area Specified value 22.0 31.8 — 200 200 Unit µs µs µs ns ns tp1 tp2 tp3∗1 tp4 tp5 ∗1 In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified. – 10 – CXD2424R Description of Operation 1. Mode Control Symbol RM RDM PS EXT REND REVH Pin No. 42 41 3 36 37 38 L 1/25s non-interlaced Normal operation Parallel Internal synchronization Normal reset V reset H 1/50s interlaced Random trigger shutter Serial External synchronization Direct reset HV reset Electronic shutter speed input method Remarks 2. Mode Relationships RM L Internal synchronization L RDM Normal operation H Random trigger shutter Normal operation L 1/25s non-interlaced H External synchronization L Internal synchronization L Normal operation H Random trigger shutter Normal operation L REND Direct reset L REVH V reset : Disabled H HV reset Normal reset H Direct reset L V reset H HV reset H 1/50s interlaced H External synchronization EXT – 11 – CXD2424R 3. Electronic Shutter SMD1 SMD2 L L L H H L H H Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/50 Low-speed shutter: Shutter speed slower than 1/50 No shutter operation PS = Low : Parallel input; set by ED0 to ED2, SMD1, and SMD2. PS = High : Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin. 3-1. Parallel input Shutter Speed Compatibility Chart Mode OFF Flickerless PS L L L L L High-speed shutter L L L L L L L L Low-speed shutter L L L L L SMD1 H L L L L L L L L L H H H H H H H H SMD2 H L H H H H H H H H L L L L L L L L ED0 X X H L H L H L H L H L H L H L H L ED1 X X H H L L H H L L H H L L H H L L ED2 X X H H H H L L L L H H H H L L L L Shutter speed Shutter off 1/120 (s) 1/50 (s) 1/125 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) 2FLD 4FLD 6FLD 8FLD 10FLD 12FLD 14FLD 16FLD – 12 – CXD2424R 3-2. Serial input • For serial input (PS = High), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within at the rise of ED0. AC Characteristics ED2 ts2 th2 ED1 tw1 ED0 tw0 ts1 ts0 Symbol Definition ED2 set-up time, activated by the falling edge of ED1 ED2 hold time, activated by the rising edge of ED1 ED1 rising set-up time, activated by the rising edge of ED0 ED0 pulse width ED0 rising set-up time, activated by the rising edge of ED1 ED1 pulse width (serial input) Min. 20ns 20ns 20ns 20ns 20ns 20ns Max. — — — 50µs — — ts2 th2 ts1 tw0 ts0 tw1 – 13 – CXD2424R 3-3. Shutter speed calculation formula High-speed shutter T = [31210 – (1FF16 – L16)] × 64 + 35.6 (µs) (∗L16 = Load value) Load value 0C816 0CA16 0CE16 0D616 0E616 10516 14316 14916 Shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/120 Calculated value 1/10040 1/4394 1/2068 1/1004 1/495 1/250 1/125 1/120 Low-speed shutter N = 2 × (1FF16 – L16) FLD However, “FF” cannot be used as the load value. Load value Shutter speed (FLD) 1FE16 1FD16 : 10116 10016 2 4 : 508 510 Note) In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range of specification after power is turned on, and then use it. – 14 – CXD2424R 4. Random Trigger Shutter The random trigger shutter is different from the conventional electronic shutter in that the exposure beginning can be freely set. The exposure period (shutter speed) can be set as with the conventional electronic shutter. In this mode, XSUB rises for each 1H, and the charge stored in the sensor is discharged. Because the V clock (XV1 to XV3) is continuously operating, any unneeded charge in the vertical CCD is eliminated. XSG pulse is stopped until the external trigger is detected. The image cannot be monitored until the external trigger is detected and the signal is read out. When an external trigger is input in this state, HD is forcibly reset when the trigger falls, and XSUB falls once to clear the charge and then halts. XV1 to XV3, XCPDM, XCPOB, and PBLK are reset with HD. From this point, exposure begins, and after the preset exposure period has passed, the XSG pulse falls, the charge is transferred from the sensor to the vertical CCD, and exposure ends. The XSG pulse falls with the time set as in conventional electronic shutters, regardless of VD. Because HD is reset, the exposure period is accurate in 1H units. The WEN pulse is generated synchronously with the XSG pulse. As the WEN pulse specifies the signal start, it can be used as the sync signal for writing image data into the frame memory. In the random trigger shutter mode, V-direction functions of a sync signal generator are halted. As a result, sync signals VD and FLD are also halted. TRIG HD reset HD XSG XSUB reset XSUB Shutter speed XV1 XV2 XV3 WEN – 15 – CXD2424R 5. External Synchronization - Reset HD and VD are reset to synchronize with the external sync signal. Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same. There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The CXD2424R has two reset modes: normal reset and direct reset. Details of the reset modes are described in the following pages. In the 1/25s non-interlaced readout mode, the normal reset mode is not supported, and although the direct reset mode is supported, the field is not identified. – 16 – CXD2424R 5-1. Normal reset In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from that time. Only the mode which resets both HD and VD (HV reset) is supported, and the mode which does not accept the HD reset (V reset) is not supported. When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (136ns) on the internal clock. In other words, the HRI input jitter is absorbed when it is up to 136 ns. The HRI minimum reset pulse width is 0.3µs. In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 312.5 – 3 = 309.5H. The VRI minimum reset pulse width is 2H. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics. FIELD.E HRI FIELD.O HDO VRI 7.5H VDO 309.5H FIELD.O HRI FIELD.E HDO VRI 7.5H VDO 309.5H H reset 57.6 to 57.7µs (850 to 851bit) HRI HD OUT Reset 6.3 to 6.37µs – 17 – CXD2424R 5-2. Direct reset In the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no continuous output. There are two direct reset modes: one to direct reset VD only, and one to reset both HD and VD. (However, note that even for V reset, the HD signal is acceptable and the reset timing is the same as in normal reset mode.) In both modes, the VD reset timing is the same. When the external input V reset signal VRI fall is detected, a judgment is made as to ODD or EVEN. If ODD, V is reset to cause VDO to fall simultaneously in the middle of HD, and if EVEN, V is reset to cause VDO to fall simultaneously with HD fall. VRI requires a minimum pulse width of 2H. H direct reset detects the fall of H reset signal HRI, and resets H so that HDO falls at the next CL falling edge. The minimum HRI reset pulse width is 0.3µs. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics. 5-2-1. V reset FIELD.E HRI FIELD.O HDO VRI 7.5H VDO FIELD.O HRI HDO FIELD.E VRI 7.5H VDO – 18 – CXD2424R 5-2-2. HV reset (1/50s interlaced readout mode) FIELD.E HDO HRI 7.5H VDO VRI FIELD.O XSG ID FIELD.O HDO FIELD.E HRI 7.5H VDO VRI XSG ID CL HRI HDO – 19 – CXD2424R 5-2-3. HV reset (1/25s non-interlaced readout mode) HDO HRI 7.5H VDO VRI XSG ID HDO HRI 7.5H VDO VRI XSG ID CL HRI HDO – 20 – XCPDM XV3 XV2 XV1 XVOG VDO BLK FLD XHHG2 OUT2 OUT1 PBLK HDO XSG XHHG1B XHHG1A XVHOLD XCPOB ID WEN 581 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 582 1 3 5 7 1 3 5 7 9 11 13 15 Timing Chart (1) 1/50s interlaced readout (RM = High) – 21 – 581 582 1 3 5 7 1 3 5 7 9 11 13 15 2 4 6 8 2 4 6 8 10 12 14 16 2 4 6 8 2 4 6 8 10 12 14 16 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 335 CXD2424R CXD2424R Timing Chart (2) 1/25s non-interlaced readout (RM = Low) FLD VDO BLK HDO 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 581 582 1 2 3 4 5 6 7 8 1 2 3 4 XV1 XV2 XV3 581 582 OUT1 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 22 – 1 2 3 4 5 6 7 8 1 2 3 Timing Chart (3) 1/50s interlaced readout (RM = High) 30 70 80 100 110 102 177 0 40 90 120 130 140 150 160 170 180 50 60 10 20 BLK/HD CL 44 68 92 116 XV1 52 76 124 100 XV2 60 84 132 124 108 XV3 60 84 108 XVHOLD 46 102 116 66 XVOG 44 76 100 124 82 132 100 XHHG1A 44 XHHG1B 60 98 XHHG2 80 90 OPB (38 bits) 130 1 71 96 – 23 – 93 44 124 39 122 122 Dummy (19 bits) OPB (3 bits) XH1 19 XH2 RG XSHP XSHD XSUB PBLK 155 XCPOB 17 144 154 XCPDM ID CXD2424R WEN Timing Chart (4) 1/25s non-interlaced readout (RM = Low) 30 70 80 100 110 102 177 0 40 90 120 130 140 150 160 170 180 50 60 10 20 BLK/HD CL 44 84 XV1 60 100 XV2 76 116 XV3 76 116 84 44 XVHOLD XVOG 44 132 124 XHHG1A 44 XHHG1B – 24 – 130 93 44 124 39 122 122 XHHG2 OPB (38 bits) Dummy (19 bits) OPB (3 bits) XH1 1 19 XH2 RG XSHP XSHD XSUB PBLK 155 XCPOB 17 144 154 XCPDM ID CXD2424R WEN CXD2424R Timing Chart (5) 1/50s interlaced (RM = High) HD 2.58µs (38 bits) 43.25µs (638 bits) 2.58µs (38 bits) 15.59µs (230 bits) 3.25µs (48 bits) ODD Field XV1 XV2 XV3 XSG EVEN Field XV1 XV2 XV3 XSG Timing Chart (6) 1/25s non-interlaced (RM = Low) HD 2.58µs (38 bits) 43.25µs (638 bits) 2.58µs (38 bits) 15.59µs (230 bits) 3.25µs (48 bits) ODD Field XV1 XV2 XV3 XSG – 25 – CXD2424R Timing Chart (7) HD CKI CL XH1 XH2 RG XSHP XSHD XRS CLD – 26 – CXD2424R Timing Chart (8) O: ODD E: EVEN Field E HDO 7.5H VDO Field O SYNC 25H BLK FLD Field O HDO 7.5H VDO Field E SYNC 25H BLK FLD – 27 – CXD2424R Timing Chart (9) HDO 6.92µs (102 bits) BLK 12.0µs (177 bits) HSYNC 1.48µs (22 bits) 4.93µs (73 bits) EQ 2.47µs (36 bits) VSYNC 27.07µs (399 bits) 4.93µs (73 bits) VDO FLD ODD EVEN O2FH 9.87µs (145 bits) 11.91µs (176 bits) 10.22µs (151 bits) 64.0µs (944 bits) 1/2H 32.0µs (472 bits) FH 9.87µs (146 bits) 22.13µs (326 bits) – 28 – CXD2424R Setting Up during Power ON During power on, after setting random trigger shutter mode once, switch to normal operation mode, and then use it. To be concrete, control supply voltage of two pins as shown below. The period to set random trigger shutter mode must be 1 clock (68ns) or more. Pin No. 7 41 Symbol SMD1 (with pull-up resistor) RDM (with pull-down resistor) Supply voltage of pin → High → Low (normal operation) during power on Low High (random trigger shutter) +5V power supply (TG power supply) SMD1 pin voltage Low 0.3VDD 0.7VDD High RDM pin voltage High Low 68ns or more – 29 – Application Circuit (1/60s interlaced, internal synchronization, normal continuous operation) 47p 47p 47p 47p 47p Refer to setting up during power on. 2.2K 2.2K 2.2K 2.2K N.C. 2.2K N.C. N.C. 13 15 24 14 22 21 CXA1690Q 22 CXD2311AR 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 N.C. 31 N.C. 30 29 28 27 26 CXD2424R 0.01 10/10V 13 15 24 14 22 21 CXA1690Q 24 23 22 21 N.C. 20 N.C. 19 18 17 6 7 8 9 10 11 12 13 14 15 16 25 50 N.C. 51 47p 2.2K 53 54 47p 2.2K 55 10/10V 0.01 56 ANALOG OUT1 N.C. 52 DIGITAL OUT1 (10 bit) 47p 2.2K 57 58 59 64 1000p 1 2 3 4 5 ANALOG OUT2 – 30 – CXD1250M CXD1268M 74HC04 VSUB ADJ. CCD OUT1 ICX075AL CCD OUT2 47p 2.2K 60 22 CXD2311AR 47p 61 2.2K N.C. 62 N.C. 63 DIGITAL OUT2 (10 bit) 12p 20p +5V Refer to setting up during power on. Input only for random trigger shutter mode. To MEMORY CONTROLLER CXD2424R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2424R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 48 49 10.0 ± 0.1 33 32 A 64 1 0.5 ± 0.08 16 + 0.2 1.5 – 0.1 17 (0.22) + 0.08 0.18 – 0.03 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g – 31 – 0.5 ± 0.2 (11.0)