CXD2437TQ

CXD2437TQ Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2437TQ is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features • External trigger function • Electronic shutter function • Supports non-interlaced operation • 12 frames/s. Double-speed readout (24 frames/s) is also possible by mixing two vertical pixels. • Base oscillation 40.490496MHz Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX085AK, ICX085AL 64 pin TQFP (Plastic) Absolute Maximum Ratings Vss – 0.5 to +7.0 • Supply voltage VDD • Input voltage VI Vss – 0.5 to VDD + 0.5 • Output voltage VO Vss – 0.5 to VDD + 0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 • Operating temperature Topr –20 to +75 V V V °C °C V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96319A95-PS CXD2437TQ XCPDM XCPOB BUSY WEN ESG TRIG STDBY PBLK XGRST Block Diagram ID 48 47 46 36 35 34 59 58 57 56 62 61 RG 27 XH1 25 XH2 26 XSHP1 30 XSHD1 31 XRS1 32 XSHP2 38 XSHD2 39 XRS2 40 XV1 23 XV2 22 XV3 21 XSG 18 CLD1 52 CLD2 49 CL 51 CKO 53 INT 4 64 1 2 11 13 14 3 9 24 29 37 41 50 55 60 1/2 10 20 28 33 42 54 63 VDD GATE COUNTER TG PULSE GENERATOR REGISTER 6 7 8 5 DECODE STRB DCLK DATA TEST1 VD HD 12 TEST2 15 TEST3 16 TEST4 19 XSUB CKI OSCO OSCI SMDE FSE RM Pin Configuration (Top View) XCPDM XSHD2 XSHP2 BUSY XRS2 VDD PBLK WEN XCPOB VDD 32 XRS1 31 XSHD1 30 XSHP1 29 VSS 28 VDD 27 RG 26 XH2 25 XH1 24 VSS 23 XV1 22 XV2 21 XV3 20 VDD 19 XSUB 18 XSG 17 CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CLD2 49 VSS 50 CL 51 CLD1 52 CKO 53 VDD 54 VSS 55 XGRST 56 STDBY 57 TRIG 58 ESG 59 VSS 60 HD 61 VD 62 VDD 63 CKI 64 INT NC NC VSS ID NC VSS TEST1 TEST2 TEST3 VSS VSS OSCO SMDE DATA OSCI STRB DCLK FSE RM –2– TEST4 VDD CXD2437TQ Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol OSCO OSCI VSS INT TEST1 STRB DCLK DATA VSS VDD RM TEST2 FSE SMDE TEST3 TEST4 CH XSG XSUB VDD XV3 XV2 XV1 VSS XH1 XH2 RG VDD VSS XSHP1 XSHD1 XRS1 VDD XCPOB I/O O I — I I I I I — — I I I I I I — O O — O O O — O O O — — O O O — O Inverter output for oscillation. Inverter input for oscillation. GND Switching for base oscillation input (with pull-up resistor). High: Oscillation provided by the internal oscillation cell, Low: CKI input valid Test (with pull-up resistor). Fix to high. Shutter speed setting (with pull-up resistor). Shutter speed setting (with pull-up resistor). Shutter speed setting (with pull-up resistor). GND Power supply. Switching for frame rate (with pull-up resistor). High: Normal readout mode, Low: Double-speed readout mode Test (with pull-up resistor). Fix to high. Switching for external trigger discharge operation (with pull-up resistor). High: High-speed discharge, Low: No high-speed discharge Switching for readout timing (with pull-up resistor). High: ESG setting invalid, Low: ESG input valid Test (with pull-up resistor). Fix to high. Test (with pull-up resistor). Fix to high. Switching for color separated pulse output (with pull-up resistor). High: Normal pulse output mode, Low: Color separated pulse output mode Sensor charge readout pulse output. CCD discharge pulse output. Power supply. Clock output for vertical CCD drive. Clock output for vertical CCD drive. Clock output for vertical CCD drive. GND Clock output for horizontal CCD drive. Clock output for horizontal CCD drive. Reset gate pulse output. Power supply. GND Sample-and-hold pulse output. Sample-and-hold pulse output. Sample-and-hold pulse output. Power supply. Clamp pulse output. –3– Description CXD2437TQ Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol XCPDM PBLK VSS XSHP2 XSHD2 XRS2 VSS VDD NC NC NC ID WEN BUSY CLD2 VSS CL CLD1 CKO VDD VSS XGRST STDBY TRIG ESG VSS HD VD VDD CKI I/O O O — O O O — — Clamp pulse output. Blanking cleaning pulse output. GND Sample-and-hold pulse output. Sample-and-hold pulse output. Sample-and-hold pulse output. GND Power supply. Description O O O O — O O O — — I I I I — I I — I Line identification output. Write enable output. Trigger mode flag. AD conversion pulse output. GND Clock output (1616fH). AD conversion pulse output. Clock output (3232fH). Power supply. GND Resets all internal FF. Low: Reset (with pull-up resistor). Always input one reset pulse after power–on. Standby (with pull-up resistor). High: Normal, Low: Internal clock supply stopped External trigger input (with pull-up resistor). External readout input (with pull-up resistor). GND Horizontal sync signal input. Vertical sync signal input. Power supply. Clock input (valid when INT = low). –4– CXD2437TQ Electrical Characteristics 1. DC Characteristics Item Supply voltage Input voltage 1 (Input pins other than those listed below) Input voltage 2 (Pin 2) Output voltage 1 (Output pins other than those listed below) Output voltage 2 (Pins 30, 31, 32, 38, 39, 40, 49, 51, 52 and 53) Output voltage 3 (Pins 25, 26 and 27) Output voltage 4 (Pin 1) Feedback resistor Pull-up resistor Pull-down resistor Current consumption Symbol VDD VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RFB RPU RPD IDD VIN = VSS or VDD VIL = 0V VIH = VDD VDD = 5V 1M 50k 50k 60 100k 100k IOH = –2.5mA IOL = 4.5mA IOH = –5.0mA IOL = 9.0mA IOH = –7.5mA IOL = 13.5mA VDD/2 VDD/2 VDD – 0.4 0.4 VDD – 0.4 0.4 VDD – 0.4 0.4 0.7VDD 0.3VDD (VDD = 4.75 to 5.25V, Topr = –20 to +75°C) Conditions Min. 4.75 0.7VDD 0.3VDD Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V V V Ω Ω Ω mA –5– CXD2437TQ 2. AC Characteristics 1) Waveform characteristics of XH1, XH2 and RG 0.9VDD XH1 0.1VDD tFH1 tWH1 tRH1 0.9VDD XH2 0.1VDD tRH2 tWH2 tFH2 0.9VDD RG 0.1VDD tRRG tWRG tFRG (VDD = 5.0V, Topr = 25°C, load capacitance of XH1 and XH2 = 30pF, load capacitance of RG = 10pF) Symbol Definition XH1 rise time XH1 fall time XH1 low level time XH2 rise time XH2 fall time XH2 high level time RG rise time RG fall time RG high level time Min. Typ. 3 3 25 3 3 25 2 2 12 Max. Unit ns ns ns ns ns ns ns ns ns tRH1 tFH1 tWH1 tRH2 tFH2 tWH2 tRRG tFRG tWRG –6– CXD2437TQ 2) Phase characteristics of XH1, XH2, RG, XSHP, XSHD, XRS, CL, CLD and CKO tH1 XH1 0.5VDD 0.5VDD 0.5VDD XH2 tPD3 RG 0.5VDD tPD4 XSHP 0.5VDD 0.5VDD 0.5VDD tPD1 0.5VDD tPD2 tW1 tPD5 0.5VDD tW2 tPD6 XSHD 0.5VDD 0.5VDD tPD7 XRS 0.5VDD tPD8 tPD9 0.5VDD CLD tPD10 CL 0.5VDD 0.5VDD tW3 0.5VDD tW4 0.5VDD tW5 CKO 0.5VDD tPD11 0.5VDD (VDD = 5.0V, Topr = 25°C, load capacitance of CL and CKO = 30pF, load capacitance of CLD, XSHP, XSHD, XRS and RG = 10pF) Symbol Definition XH1 cycle XH2 falling delay, activated by the rising edge of XH1 XH2 rising delay, activated by the falling edge of XH1 XH1 falling delay, activated by the rising edge of RG XSHP falling delay, activated by the falling edge of RG XSHP rising delay, activated by the rising edge of XH1 XH1 falling delay, activated by the rising edge of XSHD CLD falling delay, activated by the falling edge of XSHD CLD falling delay, activated by the rising edge of XRS XRS falling delay, activated by the falling edge of CLD CL rising delay, activated by the falling edge of CLD –7– Min. Typ. 49.4 0 0 4 4.5 9 3 23 21.5 9 2.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns tH1 tPD1 tPD2 tPD3 tPD4 tPD5 tPD6 tPD7 tPD8 tPD9 tPD10 CXD2437TQ Symbol Definition CKO rising delay, activated by the falling (rising) edge of XH1 XSHP pulse width XSHD pulse width CLD pulse width CL pulse width CKO pulse width Min. Typ. 2.5 21 20 21 25 11.5 Max. Unit ns ns ns ns ns ns tPD11 tW1 tW2 tW3 tW4 tW5 3) Phase conditions of HD, VD, TRIG and ESG CL 0.5VDD tSETUP tHOLD HD, VD, TRIG, ESG 0.5VDD 0.5VDD (VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF) Symbol Definition HD, VD, TRIG and ESG setup time, activated by CL HD, VD, TRIG and ESG hold time, activated by CL Min. 6 6 Typ. Max. Unit ns ns tSETUP tHOLD 3) Phase conditions of HD, VD, TRIG and ESG tWRST XGRST 0.3VDD 0.3VDD (Within the recommended operating condition) Symbol Definition XGRST pulse width Min. 50 Typ. Max. Unit ns tWRST –8– CXD2437TQ 5) Phase characteristics of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID CL 0.5VDD 0.5VDD tPDCL1 XV1, XV2, XV3 tPDCL2 0.5VDD BUSY, WEN, ID tPDCL3 0.5VDD XSG, XSUB, PBLK, XCPDM, XCPOB 0.5VDD (VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF, load capacitance of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID = 10pF) Symbol Definition XV1, XV2 and XV3 delay, activated by the falling edge of CL BUSY, WEN and ID delay, activated by the rising edge of CL XSG, XSUB, PBLK, XCPDM and XCPOB delay, activated by the rising edge of CL Min. 20 20 15 Typ. Max. 30 35 30 Unit ns ns ns tPDCL1 tPDCL2 tPDCL3 –9– CXD2437TQ Description of Functions 1. Progressive Scan CCD drive pulse generation • Combining this IC with a crystal oscillator generates a fundamental frequency of 40.49MHz. • CCD drive pulse generation is synchronized with the HD and VD inputs. • Setting the RM pin to low sets the frame rate to double-speed readout mode (24 frames/s). However, the CCD vertical resolution is halved. • fCL = 1616fHD, fHD = 1044fVD (normal readout mode: RM = high) • fCL = 1616fHD, fHD = 522fVD (double-speed readout mode: RM = low) • The various operations are performed by the TRIG and ESG inputs. (See the following items.) CL 1 HD 65 68 XH1 Detection timing for VD, RM, TRIG and ESG After HD input is detected, VD, RM, TRIG and ESG are detected at the rising edge of the 65th CL pulse. However, the low level period for each pulse should be set to 1H or longer to prevent misoperation. 2. Electronic shutter The electronic shutter has the following four shutter modes. • Electronic shutter off: Exposure time is 1/12s (RM = high) or 1/24s (RM = low) • High-speed electronic shutter: Exposure time is shorter than 1/12s (RM = high) or 1/24s (RM = low) • Low-speed electronic shutter: Exposure time is longer than 1/12s (RM = high) or 1/24s (RM = low) The shutter speed is set serially using the STRB, DCLK and DATA pins. The electronic shutter mode and the meanings of the numbers indicated by D0 to 10 vary according to the SMD1 and SMD2 settings of the internal register. STRB DCLK DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 SMD1 SMD2 – 10 – CXD2437TQ SMD1 H L H L SMD2 H H L L Mode Electronic shutter off (1/12s accumulation∗1) High-speed electronic shutter Low-speed electronic shutter Electronic shutter off (1/12s accumulation∗1) D0 to 10 — Number of exposed lines∗2 Number of exposed frames∗3 — ∗1 When RM = high. 1/24s accumulation when RM = low. ∗2 Relationship between the number of exposed lines and the exposure time The relationship between the number of exposed lines and the exposure time is as follows. (Exposure time) = (Number of exposed lines) × (One horizontal scan period) + (Accumulation time for the readout lines) In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for the readout lines is the time from the rising edge of XSUB to the falling edge of XSG (510 bits). Also, the number of exposed lines should be set to greater than 1 but less than 1043. ∗3 The number of exposed frames should be set to greater than 1 but less than 120. During external trigger mode, the number of exposed frames should be set to greater than 2. Timing Chart STRB tWD DCLK tSDD DATA tHDD tSDS tWS AC characteristics for serial input Symbol Definition DATA setup time, activated by the rising edge of DCLK DATA hold time, activated by the rising edge of DCLK DCLK setup time, activated by the falling edge of STRB STRB pulse width DCLK pulse width Min. 10 10 30 82 82 Max. — — — — — Unit ns ns ns ns ns tSDD tHDD tSDS tWS tWD – 11 – CXD2437TQ 3. External trigger mode External trigger mode starts exposure in sync with the external trigger input. No special pins are required to set this mode. Note that during external trigger mode, normal readout mode results regardless of the RM status. The IC prepares to shift to external trigger mode with the rising edge of the TRIG pin.∗1 The timing to shift to external trigger mode varies according to the mode setting. (See the table.) The BUSY pin maintains high status during external trigger mode. Whether or not to discharge the vertical CCD charge is set by FSE just after shifting to external trigger mode. ∗1 See the detection timing for VD, TRIG and ESG. Mode settings during external trigger SMD1 L L H H SMD2 L H L H Description of operation Trigger input is not accepted. Fix SMDE to high. The IC is shifted to external trigger mode by HD, exposure is finished after the set time, and XSG is output.∗2 The IC is shifted to external trigger mode by VD and exposure is finished in sync with VD after the set time.∗2 Trigger input is not accepted. Fix SMDE to high ∗2 The exposure time setting method is the same as the exposure time setting for the electronic shutter. During external trigger mode, the previously exposed signal charge sometimes remains in the vertical CCD when exposure finishes. In this case, the image shot with external trigger mode is output overlapped with the previously shot image. Setting FSE to high performs discharge operation for signal charges remaining in the vertical CCD after trigger input. Discharge operation is not performed when FSE is low. This setting is only valid when using the highspeed shutter. During external trigger mode, exposure can be finished in sync with the falling edge of ESG.∗3 If SMDE is set to low, the XSG pulse is output regardless of the electronic shutter setting, when the falling edge of ESG is detected. ESG should be fixed to high status at all times other than during external trigger mode. ∗3 See the detection timing for VD, TRIG and ESG. After high-speed external trigger mode is finished, the exposure time differs from that performed by the electronic shutter setting. This is because the start and finish of external trigger mode are not synchronized to VD input. 4. Internal logic stop (standby mode) When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output from the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status of each output pin when STDBY is low is shown below. High: XSUB, XSG Low: RG, XH1, XH2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN, BUSY, CLD Not stopped: OSCO, CL, CKO – 12 – CXD2437TQ 5. Color separated pulse output mode • CDS/AGC can be supported to the system which performs with 2-channel by setting CH pin to low. When using CH pin at high, leave XSHP2, XSHD2, XRS2 and CLD2 pins open, respectivery. • XSHP, XSHD, XRS and CLD pins operate as shown in the figure below. Note) XSHP = XSHP1 and XSHP2, XSHD = XSHD1 and XSHD2 XRS = XRS1 and XRS2, CLD = CLD1 and CLD2 High-speed pulse when CH = low XH1 and 2 stop. XH1 XH2 RG ID = H XSHP1 XSHD1 XRS1 CLD1 XSHP2 XSHD2 XRS2 CLD2 XH1 and 2 operations start. R and Gr lines when ID = high ID = L Gb and B lines when ID = low XSHP1 XSHD1 XRS1 CLD1 XSHP2 XSHD2 XRS2 CLD2 – 13 – CXD2437TQ 6. Mode settings 6-1. VD input-related BUSY SMD1 L H H L SMD2 H SMDE X L H Invalid Exposure is started from the first VD input. Readout operation or the number of accumulated frames is counted. VD input L L H L H H L X Readout operation is performed. Notes) 1. SMD1 and SMD2 indicate the corresponding internal register values. 2. See "2. Electronic shutter". 6-2. TRIG and ESG input-related BUSY Discharge period∗1 H Exposure period Signal output period Before TRIG input L After TRIG input∗2,∗3 ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 SMDE X H L X H L H L Prohibited IC shifted to external trigger mode∗3 Prohibited Readout operation∗5 Prohibited∗5 TRIG∗4 ESG Prohibited∗5 Prohibited∗6 Only when FSE is high. Valid only during low-speed shutter. See "3. External trigger mode". Do not re-input the TRIG pulse until BUSY goes low. ESG input is valid only one time after TRIG input. Do not input ESG two times or more. Lock ESG to high status when BUSY is low. – 14 – CXD2437TQ 6-3. List of Timing Charts SMD1 SMD2 RM H FSE SMDE BUSY L X L X X X Timing chart Chart-1 Chart-2 Chart-3 Chart-4 Chart-5 Chart-6 L H→L H L L H X H L H H L L H L H X Chart-14 H L Chart-15 Vertical Vertical L H H H Chart-7 Chart-8 Chart-9 Vertical Vertical Vertical Vertical/ Horizontal Vertical Normal readout Operation Horizontal Normal readout Vertical Double-speed readout L X X X L→H Horizontal Double-speed readout Horizontal Readout operation Vertical Shifting from normal readout to double-speed readout Shifting from double-speed readout to normal readout During external trigger input, discharge During external trigger input, discharge, double-speed During external trigger input, (discharge operation) During external trigger input, no discharge During external trigger input, no discharge, double-speed During external trigger input, low-speed shutter During external trigger input, low-speed shutter, double-speed During external trigger input, ESG Chart-10 Horizontal Chart-11 Chart-12 Chart-13 Vertical Vertical Vertical – 15 – Chart-1 Normal Operation: Vertical synchronization VD HD 1 3 6 OUT 12312345678 XV1 XV2 XV3 XSG XSUB See "2. Electronic shutter" for the number of XSUB pulses. PBLK XCPOB XCPDM ID WEN BUSY CXD2437TQ 1036 1037 1030 – 16 – Chart-2 Normal Operation: Horizontal synchronization 0 HD 68 CL 125 87 106 163 144 1616 1 XV1 1 68 XV2 1 XV3 1 1 234 276 XSG (= High) XSUB 1 XH1 – 17 – XH2 RG XSHP XSHD XRS 322 PBLK 1 67 XCPOB 1 22 59 286 306 321 XCPDM 1 ID WEN CXD2437TQ BUSY 300 Chart-3 Normal Operation, Double-speed Mode (RM = low): Vertical synchronization VD HD 1 2 4 21357 1030 OUT 1 324 68 XV1 XV2 XV3 XSG XSUB See "2. Electronic shutter" for the number of XSUB pulses. PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 519 520 1029 – 18 – Chart-4 Normal Operation, Double-speed Mode (RM = low): Horizontal synchronization 0 HD CL 125 87 106 277 163 220 144 201 258 182 239 1616 1 XV1 1 XV2 1 XV3 1 XSG (= High) 234 276 1 XSUB 1 XH1 – 19 – XH2 RG XSHP XSHD XRS 322 PBLK 1 67 XCPOB 1 22 59 286 306 321 XCPDM 1 ID WEN CXD2437TQ BUSY 68 68 300 Chart-5 Readout Operation: Horizontal synchronization HD 68 1 CL Normal readout 1 XSG 684 125 68 87 125 1 1 786 XV1 87 144 868 1 106 1 1 68 XV2 1 68 144 163 – 20 – 106 1 684 125 182 201 258 868 239 786 1 1 87 144 163 220 1 1 106 1 XV3 1 PBLK 1 67 322 Double-speed readout XSG 1 XV1 1 68 68 125 182 87 144 163 106 239 XV2 201 258 277 220 1 XV3 1 CXD2437TQ PBLK 1 67 322 Chart-6 Switching from Normal Mode (RM = high) to Double-speed Mode (RM = low) RM is reflected from the next VD. RM VD HD 1 2 21357 1 324 68 OUT XV1 XV2 – 21 – XV3 XSG See "2. Electronic shutter" for the number of XSUB pulses. XSUB PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 4 Chart-7 Switching from Double-speed Mode (RM = low) to Normal Mode (RM = high) RM is reflected from the next VD. RM VD HD 1 3 12312345678 OUT XV1 XV2 – 22 – XV3 XSG See "2. Electronic shutter" for the number of XSUB pulses. XSUB PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 6 Chart-8 External Trigger Mode: High-speed electronic shutter, discharge, normal readout (FSE = high, SMDE = high, RM = high) TRIG This VD is ignored. VD HD 1 1 76 5 OUT 1 2 31 2 3 4 5 6 7 8 1037 1 2 31 2 3 4 5 6 7 RG XV1 XV2 1 PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 9 – 23 – See "2. Electronic shutter" for the XSG output position. XV3 XSG The number of XSUB pulses here conforms to normal operation. XSUB Chart-9 External Trigger Mode: High-speed electronic shutter, discharge, double-speed mode (FSE = high, SMDE = high, RM = low) TRIG This VD is ignored. VD HD 1 1 76 6 1037 21357 1 32 4 68 OUT 1 2 31 2 3 4 5 6 7 8 RG XV1 XV2 1 PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 9 – 24 – See "2. Electronic shutter" for the XSG output position. The number of XSUB pulses here conforms to normal operation. XV3 XSG XSUB Chart-10 External Trigger Mode: High-speed electronic shutter, when discharge starts (FSE = high) 0 1 (This XV1 to XV3 operation is repeated up to 1045 times.) 2 3 HD CL 125 239 201 163 277 220 258 87 106 144 182 1616 1 XV1 1 XV2 1 XV3 1 XSG (= High) 234 276 1 XSUB 1 XH1 – 25 – XH2 RG XSHP XSHD XRS PBLK 1 XCPOB 1 22 59 286 XCPDM 1 ID WEN CXD2437TQ BUSY 68 68 67 298 Chart-11 External Trigger Mode: High-speed electronic shutter, no discharge (FSE = low, SMDE = high) TRIG This VD is ignored. VD HD 1 6 OUT 1231234 56 78 1 2312 34 5 67 RG XV1 XV2 – 26 – See "2. Electronic shutter" for the XSG output position. The number of XSUB pulses here conforms to normal operation. XV3 XSG XSUB PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 1037 Chart-12 External Trigger Mode: High-speed electronic shutter, no discharge, double-speed mode (FSE = low, SMDE = high, RM = low) TRIG This VD is ignored. VD HD 1 6 1037 21357 1 3246 8 OUT 1 23 12 345 67 8 RG XV1 XV2 – 27 – See "2. Electronic shutter" for the XSG output position. The number of XSUB pulses here conforms to normal operation. XV3 XSG XSUB PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY Chart-13 External Trigger Mode: Low-speed electronic shutter (SMDE = high, RM = high) TRIG VD HD 1 6 1037 1 6 OUT 12 312 34 56 78 1 2 31 2 3 45 67 8 RG XV1 XV2 – 28 – XV3 XSG See "2. Electronic shutter" for the time from the XSG output after TRIG input until the next XSG output. XSUB PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 1037 Chart-14 External Trigger Mode: Low-speed electronic shutter, double-speed mode (SMDE = high, RM = low) TRIG VD HD 6 1 21357 1 324 68 1 6 1 OUT 123123456 1231 2345 6 RG XV1 XV2 – 29 – XV3 XSG See "2. Electronic shutter" for the time from the XSG output after TRIG input until the next XSG output. XSUB PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 1037 4 Chart-15 Example during ESG Input: Discharge, normal readout (FSE = high, RMDE = low, RM = high) TRIG ESG This VD is ignored. VD HD 1 76 1 6 OUT 1 2 31 2 3 4 5 6 7 8 1037 1 2 31 2 3 4 5 6 7 RG XV1 1 PBLK XCPOB XCPDM ID WEN CXD2437TQ BUSY 9 – 30 – XV2 XV3 The number of XSUB pulses here conforms to normal operation. XSG XSUB Application Circuit 1 +5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 +15V 30 29 28 27 26 CXD2437TQ 24 23 22 21 20 19 18 17 6 7 8 9 10 11 12 13 14 15 16 CXD1267AN 1/6 74AC04 × 3 CDS/AGC 25 1000p A/D Converter Digital Out 49 50 51 52 53 54 55 56 57 – 31 – 58 59 60 61 62 63 64 1 2 3 4 5 CXD1268M × 2 ICX085AL CXD2437TQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Application Circuit 2 +5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 CXD2437TQ 24 23 22 21 20 19 18 17 6 7 8 9 10 11 12 13 14 15 16 CXD1267AN 74AC04 × 3 25 1000p +15V A/D Converter CDS/AGC CDS/AGC 49 50 51 A/D Converter 52 53 54 Digital Out 55 56 – 32 – 57 58 59 60 61 62 63 64 1 2 3 4 5 CXD1268M × 2 ICX085AK/AL CXD2437TQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2437TQ Package Outline Unit: mm 64PIN TQFP (PLASTIC) 12.0 ± 0.4 10.0 ± 0.2 48 33 0.1 49 32 1.27 MAX 1.0 ± 0.1 A 64 17 1 0.5 0.2 ± 0.1 16 0.08 M 0.125 ± 0.05 0.1 ± 0.1 0.5 ± 0.2 + 7° 3° – 3° DETAIL A SONY CODE EIAJ CODE JEDEC CODE 1.0 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g TQFP-64P-L071 TQFP064-P-1010-AN – 33 –