CXD2460R

CXD2460R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2460R is an IC developed to generate the timing pulses required by Progressive Scan CCD image sensors as well as signal processing circuits. Features • Electronic shutter function • Supports non-interlaced operation • Base oscillation frequency 28.636MHz • Horizontal drive frequency switchable between 14.3/7.2MHz • Switchable between FINE (Progressive Scan) mode or DRAFT (high-speed draft) mode • Built-in vertical driver Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensor ICX205AK 48 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDDa, VDDb, VDDc, VDDd Vss – 0.5 to Vss + 7.0 • Supply voltage VSS VL – 0.5 to VL + 26.0 • Supply voltage VH VL – 0.5 to VL + 26.0 • Supply voltage VM VL – 0.5 to VL + 26.0 • Input voltage VI Vss – 0.5 to VDDa,b,c,d + 0.5 V V V V V • Output voltage VO Vss – 0.5 to VDDa,b,c,d + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage 1 VDDa, VDDb, VDDd 3.0 to 3.6 • Supply voltage 2 VDDc 3.0 to 5.25 • Supply voltage 3 VH 14.25 to 15.75 • Supply voltage 4 VL –9.0 to –5.0 • Supply voltage 5 VM 0 • Operating temperature Topr –20 to +75 V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98414-PS CXD2460R Block Diagram XSHD XSHP XRS SUB 45 RG V2A VM H1 H2 VH V2B V3 12 OSCI 5 13 9 18 V1 17 19 39 40 41 42 43 44 46 VL V-Driver OSCO CKI 4 XSGA XSGB 3 XV1 XSUB XV3 XV2 CKO 1 1/2 2MCK 27 Pulse Generator 15 XCPDM 21 PBLK 22 XCPOB 32 ID 33 EXP 28 TEST2     1/2 MCK 25 ADCLK 23 VDD0 6 AVD0 8 AVD1 14 SSG AVD2 16 VDD1 26 VSS0 2 1/1790 1/1068 1/267 VSS1 10 VSS2 11 VSS3 20 VSS4 36 35 34 HRO 37 38 HRI FRI FRO 47 DSGAT 48 PS 29 SEN Register 30 SSK 31 SSI 7 TEST1 24 RST XSGA and XSGB are readout pulses that use V2A and V2B, respectively, as the VH value. –2– CXD2460R Pin Configuration (Top View) TEST2 2MCK VDD1 26 VSS4 36 HRI FRI VM V1 V3 V2A VH V2B SUB VL DSGAT PS 37 38 39 40 41 42 43 44 45 46 47 48 1 CKO 35 34 33 32 31 30 29 28 27 25 24 RST 23 ADCLK 22 XCPOB 21 PBLK 20 VSS3 19 XRS 18 XSHD 17 XSHP 16 AVD2 15 XCPDM 14 AVD1 13 H2 2 VSS0 3 CKI 4 OSCO 5 OSCI 6 VDD0 7 TEST1 8 AVD0 9 RG 10 VSS1 11 VSS2 12 H1 The enclosed pins use separate power supplies. –3– MCK HRO FRO SEN EXP SSK SSI ID CXD2460R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol CKO Vss0 CKI OSCO OSCI VDD0 TEST1 AVD0 RG Vss1 Vss2 H1 H2 AVD1 XCPDM AVD2 XSHP XSHD XRS VSS3 PBLK XCPOB ADCLK RST MCK VDD1 2MCK TEST2 SEN SSK SSI ID EXP I/O O — I O I — I — O — — O O — O — O O O — O O O I O — O I I I I O O Oscillator output. (28.6MHz) GND Oscillator input. (28.6MHz) Inverter output for oscillation. (28.6MHz) Inverter input for oscillation. (28.6MHz) Power supply. Test. With pull-down resistor. Fix to low. Power supply. Reset gate pulse output. GND GND Clock output for horizontal CCD drive. Clock output for horizontal CCD drive. Power supply. Clamp pulse. Power supply. Sample-and-hold pulse. Sample-and-hold pulse. Sample-and-hold pulse. GND Blanking cleaning pulse. Clamp pulse. Clock output for AD conversion. Reset (Low: Reset, High: Normal operation). Always input one reset pulse during power-on. Clock output for digital circuit. Power supply. Clock output for digital circuit. Test. Fix to high. PS = High: Drive frequency setting input. PS = Low: Serial setting strobe input. PS = High: Readout method setting input. PS = Low: Serial setting clock input. PS = High: Shutter speed setting input. PS = Low: Serial setting data input. Line identification signal output write enable pulse output or XSUB output. Pulse output indicating exposure is underway or checksum result output. –4– Description CXD2460R Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol HRO FRO VSS4 HRI FRI VM V1 V3 V2A VH V2B SUB VL DSGAT PS I/O O O — I I — O O O — O O — I I Description Horizontal sync signal (HR) output or XSGA output. Vertical sync signal (FR) output or XSGB output. GND Horizontal sync signal (HR) input. Vertical sync signal (FR) input. GND (vertical clock driver GND). Clock output for vertical CCD drive. Clock output for vertical CCD drive. Clock output for vertical CCD drive. 15V power supply (vertical clock driver power supply). Clock output for vertical CCD drive. CCD electric charge sweep pulse output. –8.0V power supply (vertical clock driver power supply). Output stop (Same operation control as SLP when low). Parallel/serial switching for mode setting input method. (High: Parallel, Low: Serial) With pull-down resistor. –5– CXD2460R Electrical Characteristics DC Characteristics Item Pins Symbol VDDa VDDb VDDc VDDd VH VM VL VIH1 CKI VIL1 VIH2 Input voltage 2 TEST1, PS VIL2 0.8VDDa 0.2VDDa Feed current where IOH = –10.0mA VDDa – 0.8 Pull-in current where IOL = 7.2mA Feed current where IOH = –3.3mA VDDb – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –36.0mA VDDc – 0.8 Pull-in current where IOL = 24.0mA Feed current where IOH = –3.3mA VDDd – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA VDDa – 0.8 Pull-in current where IOL = 4.8mA Feed current where IOH = –4.0mA VH – 0.25 Pull-in current where IOL = 5.4mA Feed current where IOH = –5.0mA VM – 0.25 Pull-in current where IOL = 10.0mA VL + 0.25 VL + 0.25 0.4 0.4 0.4 0.4 0.4 0.7VDDa 0.3VDDa (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 14.5 — –9.0 0.7VDDa 0.3VDDa Typ. 3.3 3.3 5.0 3.3 15.0 0.0 Max. 3.6 3.6 5.25 3.6 15.5 — –5.0 Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V VM + 0.25 V V VL + 0.25 V Supply voltage 1 VDD0, VDD1, Supply voltage 2 AVD0 Supply voltage 3 AVD1 Supply voltage 4 AVD2 Supply voltage 5 VH Supply voltage 6 VM Supply voltage 7 VL Input voltage 1 Input voltage 3 RST, TEST2, Vt + 1 SEN, SSK, SSI, HRI, FRI, DSGAT Vt – 1 CKO, MCK, 2MCK VOH1 VOL1 VOH2 Output voltage 1 Output voltage 2 RG VOL2 VOH3 VOL3 VOH4 VOL4 Output voltage 3 H1, H2 XCPDM, XSHP, Output voltage 4 XSHD, XRS, PBLK, XCPOB Output voltage 5 ID, EXP, HRO, VOH5 FRO VOL5 VOH6 VOL6 Output voltage 6 SUB Output voltage 7 V1, V3 VOM7 VOL7 VOM101 Feed current where IOH = –7.2mA VH – 0.25 Output voltage 8 V2A, V2B VOM102 Pull-in current where IOL = 5.0mA VOL8 VOL8 Feed current where IOH = –5.0mA VM – 0.25 Pull-in current where IOL = 10.0mA –6– CXD2460R Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL RFB f (Within the recommended operating conditions) Conditions Min. Typ. VDDa/2 0.7VDDa 0.3VDDa Max. Unit V V V V VDDa/2 500k 20 2M 5M 50 V Ω MHz Output voltage OSCO Feed current where IOH = –6.0mA VDDa/2 Pull-in current where IOL = 6.0mA VIN = VDDa or Vss Feedback resistor OSCI, OSCO Oscillator frequency OSCI, OSCO Base Oscillation Clock Input Characteristics Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN (Within the recommended operating conditions) Conditions Min. Typ. VDDa/2 0.7VDDa 0.3VDDa Max. Unit V V V Vp-p fmax 50MHz sine wave 0.3 ∗1 Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics for input through capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = –8.5V) Min. Typ. 350 450 50 250 300 50 Max. 550 700 80 400 450 80 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V ∗1 The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. ∗2 For noise and latch-up countermeasures, be sure to connect a bypass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. –7– CXD2460R Switching Waveforms TTMH 90% TTHM VH 90% TTLM V2A (V2B) 10% 90% 10% 90% TTML VM 10% TTLM 90% V1 (V3) 10% 10% TTML VL VM 90% 10% TTHL VL TTLH 90% VSUB 10% 90% VH 10% VL Waveform Noise VCMH VCML VH VCLH VCLL VL Measurement Circuit C1 R1 C2 C2 R1 V1 V3 C1 C2 C2 C1 V2A V2B R1 C1 R1 R1: 27Ω R2: 5Ω C1: 1500pF C2: 3300pF R2 –8– CXD2460R AC Characteristics 1) AC characteristics between the serial interface clocks SSI 0.8VDDa 0.2VDDa 0.8VDDa 0.2VDDa ts1 th1 SSK SEN 0.2VDDa ts3 SEN 0.8VDDa ts2 th2 (Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SSK SSI hold time, activated by the rising edge of SSK SSK setup time, activated by the rising edge of SEN SSK hold time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SSK SSK frequency Min. 20 20 20 20 20 7.15 Typ. Max. Unit ns ns ns ns ns MHZ ts1 th1 ts2 th2 ts3 fk 2) Serial interface clock internal loading characteristics V2A HRI 0.5VDDa 0.5VDDa 300ns Do not start up SEN during this period. (From 300ns from the falling edge of HRI immediately before generation of XSGA pulse to 300ns from the falling edge of HRI immediately after generation of XSGA pulse) 300ns –9– CXD2460R 3) Output timing characteristics using DSGAT and RST twRST DSGAT, RST 0.5VDDa 0.5VDDa EXP, XCPDM, XCPOB, PBLK, XSHP, XSHD, XRS, RG, H1, H2 tpRST 0.5VDDa, b, c, d H1 and H2 load = 270pF EXP, XCPDM, PBLK, XSHP, XSHD, XRS and RG load = 10pF (Within the recommended operating conditions) Symbol Definition Time until the above outputs reach the specified value after the fall of DSGAT and RST RST and DSGAT pulse width 10 Min. Typ. Max. 125 Unit ns ns tpRST twRST 4) FRI and HRI loading characteristics FRI, HRI 0.5VDDa tsSYNC thSYNC 0.5VDDa MCK 0.5VDDa MCK load = 35pF Symbol Definition (Within the recommended operating conditions) Min. 5 5 Typ. Max. Unit ns ns tsSYNC thSYNC FRI and HRI setup time, activated by the rising edge of MCK FRI and HRI hold time, activated by the rising edge of MCK – 10 – CXD2460R 5) Output variation characteristics of ID, WEN, EXP, FRO and HRO MCK 0.5VDDa EXP, ID, WEN tpdEXP 0.5VDDa FRO, HRO 0.5VDDa tpdSYNCO EXP, ID and WEN load = 10pF Symbol tpdEXP tpdSYNCO Definition (Within the recommended operating conditions) Min. 0.5 0.5 Typ. Max. 8.5 3.5 Unit ns ns Time until the WEN, ID and EXP outputs change after the fall of MCK Time until the FRO and HRO outputs change after the fall of MCK – 11 – CXD2460R Description of Operation 1. Progressive Scan CCD drive pulse generation • Combining this IC with a crystal oscillator generates a fundamental frequency of 28.636MHz. • CCD drive pulse generation is synchronized with HRI and FRI. • The CCD drive method can be changed to various modes by inputting serial data or parallel data to the CXD2460R. • The various drive methods possessed by the CXD2460R are shown in the Timing Charts A-1 to 3 (V rate) and B-1 to 6 (H rate). 2. Serial data input method • All CXD2460R operations can be controlled via the serial data. The serial data format is as follows. SSI 00 01 02 03 04 05 06 41 42 43 44 45 46 47 SSK SEN Serial data format Serial data Data D00 to D07 D08 to D11 D12 to D39 D40 to D47 CHIP Symbol Chip switching Function See D00 to D07 CHIP. See D08 to D11 CTGRY. When reset All 0 CTGRY Category switching Control data for each category The meaning of this CTGRY control data differs according to the category set by D08 to D11. Checksum bits All 0 DATA See D12 to D39 DATA. All 0 Checksum bits See D40 to D47 CHKSUM. All 0 – 12 – CXD2460R 3. Serial data and description of functions Detailed description D00 to D07 CHIP D07 1 D06 0 D05 D04 0 0 D03 0 D02 D01 0 0 D00 1 Function Loading to the CXD2460R The serial interface data is loaded to the CXD2460R when D00 and D07 are "1". However, this assumes that D40 to D47 CHKSUM is satisfied. This CTGRY data indicates the functions that the serial interface data controls. D11 D08 to D11 CTGRY 0 0 0 0 D10 0 0 0 1 D09 D08 0 1 1 0 0 0 1 0 Mode control data Electronic shutter control data High-speed phase adjustment data (Set all of D12 to D39 to "0".) System setting data Function Input of values other than those listed above is prohibited. CTGRY: Mode control data Detailed description 0: Power saving drive mode 1: High-speed drive mode When FHIGH = 0, the clock input to CKI is immediately frequency divided by 1/2 and loaded internally. Mode switching timing (5 clocks after the fall of HRI just before XSGA is generated) D12 FHIGH MCK Unstable CKI FHIGH = 1 FHIGH = 0 FHIGH = 1 Unstable The high-speed phases of H1, H2, RG, XSHP, XSHD, XRS, ADCLK and other pulses are always logically the same phase with respect to MCK. 0: DRAFT mode 1: FINE mode D13 FINE In FINE mode, image data is taken by the normal Progressive Scan method. In DRAFT mode, image data is taken by pulse elimination readout. This enables a frame rate four times that during FINE mode. The mode is switched at the fall of HRI just before XSGA. Note that the FRO output is also switched accordingly. (DRAFT mode: 267H, FINE mode: 1068H) 0: Normal operation 1: Readout prohibited mode D14 NSG In readout prohibited mode, a readout pulse is not added even at the timing when a readout pulse is added to V2A and V2B (VH value). (V1, V2 and V3 are not modulated.) The mode is normally switched at the fall of HRI just before the position where the readout pulse is added. – 13 – CXD2460R Detailed description 0: Normal operation 1: FS mode In order to increase the frame rate, a certain portion of the captured image of CCD can be cut out by performing high-speed sweep. In FS mode, high-speed sweep is performed for the V registers of the entire image (period Z) after FRI input. Next, high-speed sweep is performed again for only the desired period (period X) after generating the XSGA/XSGB pulses. Then, after performing normal V transfer and outputting the effective signal (period Y), high-speed sweep is performed for the entire image again by inputting FRI at the desired timing. This makes it possible to take only the desired portion in the V direction, thus effectively increasing the frame rate. Operation is fixed during period Z, with 20 lines swept every 1H and repeating over a 69H period. During period X, first XSGA/XSGB are generated. These pulses are dependent on serial data FINE. In other words, if FINE = 1, then both XSGA and XSGB are generated, while if FINE = 0, only XSGA is generated. Next, sweep operation starts. This period is set in serial data FVFS (system setting data: D21 to D26) in HRI units. If FINE = 1, sweeping is performed at 8 lines per 1H, and if FINE = 0, sweeping is performed at 20 lines per 1H. The operations of V1, V2 and V3 after readout during period Y differ depending on the FINE data. D15 FS • When the frame rate is increased as the vertical effective signal Y line (example) Sweep variable period (period X) Effective signal period (period Y) Sweep fixed period (period Z) X ,  , 

 ,   
, , 

 ,   Y 1068 Z Timing chart FRI Reset by FRI after normal transfer Z X Y V2A 69H (Fix) Set by FVFS

  
 

 ,  
      , 
   D16 to D17 Set to "0". – 14 – CXD2460R Detailed description Operation control settings The operating mode control bits are loaded to the CXD2460R at the rise timing of the SEN input, and control is applied immediately. D19 0 0 1 D18 0 1 X Symbol CAM SLP STN Normal operation mode Sleep mode (mode for the status where CCD drive is not required) Standby mode Control mode Pin status during operation control Pin No. 1 2 3 4 5 6 7 D17 to D18 STB 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol CKO VSS0 CKI OSCO OSCI VDD0 TEST1 AVD0 RG VSS1 VSS2 H1 H2 AVD1 XCPDM AVD2 XSHP XSHD XRS VSS3 PBLK XCPOB ADCLK RST CAM ACT — ACT ACT ACT — — — ACT — — ACT ACT — ACT — ACT ACT ACT — ACT ACT ACT ACT SLP ACT — ACT ACT ACT — — — L — — L L — L — L L L — L L L ACT STN ACT — ACT ACT ACT — — — L — — L L — L — L L L — L L L ACT RST∗ ACT — ACT ACT ACT — — — L — — L L — L — L L L — L L L ACT Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol MCK VDD1 2MCK TEST2 SEN SSK SSI ID EXP HRO FRO VSS4 HRI FRI VM V1 V3 V2A VH V2B SUB VL DSGAT PS CAM ACT — ACT — ACT ACT ACT ACT ACT ACT ACT — ACT ACT — ACT ACT ACT — ACT ACT — ACT ACT SLP ACT — ACT — ACT ACT ACT L L ACT ACT — ACT ACT — VM VM VH — VH VH — ACT ACT STN ACT — ACT — — — — L L L L — — — — VM VM VH — VH VH — L ACT RST∗ ACT — ACT — — — — L L L L — — — — VM VM VH — VH VH — L ACT ∗ See "6. RST pulse" for a detailed description of RST. Note) ACT indicates circuit operation, and L indicates "low" output level in the controlled status. For sleep mode or standby mode, stop supplying VH and VL power supplies with CCD image sensor. – 15 – CXD2460R Detailed description 0: The EXP pulse indicating the exposure period is generated (when PS = low). 1: The EXP pulse indicating the exposure period is not generated (when PS = low), and is constantly fixed to low. This bit is invalid when STATUS = 1. Note that the STB setting has priority. D20 EXPXEN D21 to D24 Invalid data D25 to D29 VSHUT Low-speed electronic shutter setting. The value set here is the number of FR during which readout operation is not performed even if there is input. The setting range is from "0" to "31". When set to "0", readout operation is performed at the first FR. When FS = 1, this bit is invalid. MSB D29 D28 D27 D26 LSB D25 Function Number of FR during which readout operation is not performed D30 to D39 Invalid data CXD2460R clock system When using a 28.636MHz crystal FHIGH Mode1 Mode2 Mode3 1 1 0 FINE 1 0 0 MCK frequency 2MCK pin output 14.3MHz 14.3MHz 7.2MHz 28.6MHz 28.6MHz 14.3MHz Frame rate 7.5Frame/s 30Frame/s 15Frame/s Basic DRAFT Power-save Note) Combinations of FHIGH and FINE other than those listed above are prohibited. – 16 – CXD2460R CTGRY: Electronic shutter control data Detailed description D12 to D22 HSHUT High-speed electronic shutter setting. The value set here is the number of SUB pulses from FR to the next FR. MSB LSB Function Number of SUB pulses setting D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D23 to D39 Input "0". High-speed and low-speed electronic shutter can be used together. Therefore, the exposure time is as follows: FR cycle × VSHUT + (fv – HSHUT) × HR cycle + 634/MCK frequency [Hz] = Exposure time [s] (fv: Number of HR in 1FR) – 17 – CXD2460R CTGRY: System setting data Detailed description 0: Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO. 1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low. Note that the STB setting has priority. Set SGXEN to "1" in the case of input of a CXD2460R sync signal from the outside. 0: Normal operation 1: XSGA and XSGB are output from the HRO and FRO pins. Note that the output pulse amplitude is VSS to VDDa. These bits select the pulse output from the ID pin. D15 D14 to D15 IDSEL D14 0 1 0 ID pulse output XSUB pulse output 1 WEN pulse output ID pulse output D12 SGXEN D13 EXSG XSUB: Inverted SUB pulse output at the amplitude of VSS to VDDa 0: VT (readout clock) is added to V2A, V2B and V3 as normal. 1: VT is not added to V2A, V2B and V3. During readout, only the modulation necessary for readout is performed. Note that this setting has priority over mode control data NSG (D14). D16 VTXEN 0: Checksum is not performed and the checksum data is invalid. (However, dummy data must be set in the CHKSUM register.) CHKSUM 1: Checksum is performed. This data is reflected even if the checksum results are NG. D17 0: The EXP pulse is output from the EXP pin. 1: High is indicated if the checksum results from the EXP pin are OK, and low if the results are NG. This pulse is output at the rise of SEN, and reset high again at the fall of SEN. This pulse has priority over mode control data EXP. D18 STATUS D19 to D22 Input "0". These bits set the high-speed sweep period (unit: H) in FS mode. D23 to D29 FVFS MSB D29 D28 D27 D26 D25 D24 LSB D23 The high-speed sweep is perfomed for 8 lines for every 1H when FINE = 1, and 20 lines for every 1H when FINE = 0. – 18 – CXD2460R Detailed description D30 XVCK 0: Normal operation 1: V1, V2 and V3 are inverted and output as XV1, XV2 and XV3. The amplitude is from VL to VM. D31 to D39 Invalid data CHKSUM Detailed description These are the checksum bits. MSB D07 D15 D23 D31 D39 D47 LSB D01 D00 D09 D08 D17 D16 D25 D24 D33 D32 D41 D40 → CHKSUM D40 to D47 +) D06 D14 D22 D30 D38 D46 D05 D13 D21 D29 D37 D45 D04 D12 D20 D28 D36 D44 D03 D02 D11 D10 D19 D18 D27 D26 D35 D34 D43 D42 If the total = 0, the checksum results are OK. Serial data is loaded to the internal registers only when checksum is OK. Data is not reflected to the registers if checksum is NG. Also, when CHKSUM = 0, the checksum results are always OK and the data is reflected to the registers. – 19 – CXD2460R 4. Shutter speed setting specifications when PS = H When PS = H, the CXD2460R can be controlled without inputting serial data by using the SEN, SSK and SSI pins. Pin FHIGH SEN (horizontal drive frequency) SSK When L Serial register FHIGH = 0. When H Serial register FHIGH = 1. Serial register FINE = 1 and the CXD2460R operates in FINE mode. Serial register FINE = 0 and the FINE (readout method) CXD2460R operates in DRAFT mode. Number of SUB pulses when PS = H SSK L SSI HSHUT, VSHUT (exposure time) L SEN H 251 201 235 134 H 1052 1002 1034 935 Upper number: When SSI = H (1/250) Lower number: When SSI = L (1/60) Other registers hold the value input when PS = L, and assume the status indicated by STB when the RST pulse is input. – 20 – CXD2460R 5. Reflection position of each data Each serial data is reflected at the timing shown in the table below. The reflection position is the same when PS = H. When using the low-speed electronic shutter, the data is not reflected at FR where XSG is not generated (a readout pulse is not added to V2A). Table 5-1. Serial data reflection timing Data Mode control data (STB) Mode control data (EXPXEN) Mode control data (other than STB and EXPXEN) Electronic shutter control data High-speed phase adjustment data System setting data (SGXEN) System setting data (other than SGXEN) ∗1 For FS mode, 7HRI later from FRI fall. ∗2 For FS mode, 8HRI later from FRI fall. 6. RST pulse Setting Pin 30 to low resets the system. The serial data values after reset are as shown in the "Serial data" table. Also, some internal circuits stop operating when RST = L. For a description of the pin status when RST = L, see the "Pin status during operation control" table given in the detailed description of STB under "3. Serial data and description of functions". 7. DSGAT DSGAT is ON when low and the CXD2460R is set to sleep mode as with SLP of STB. Note that control is applied when either or both of DSGAT and SLP are ON. Also, when STN is ON, the CXD2460R is set to standby mode regardless of the DSGAT status. 8. EXP pulse The EXP pulse indicates the exposure period. The details are shown on the following pages. SEN rise XSGA pulse rise HRI∗1 fall just before XSGA pulse generation HRI∗2 fall just after XSGA pulse generation HRI∗1 fall just before XSGA pulse generation SEN rise HRI∗2 fall just before XSGA pulse generation Reflection position – 21 – CXD2460R (1) HSHUT ≥ MAX HSHUT value 1 to MAX 0 MAX 6 (76) 0 6 (76) 0 0 6 (76) HRI FRI V2A SUB EXP (2) HSHUT ≥ MAX (with low-speed electronic shutter) HSHUT value 1 to MAX 0 MAX 6 (76) 0 6 (76) 6 (76) 0 0 HRI FRI Location where XSG is normally generated. (However, this pulse is not actually generated.) V2A SUB EXP (3) 1 ≤ HSHUT < MAX HSHUT value 1 to MAX 0 MAX 6 (76) 0 1 to MAX 6 (76) 0 6 (76) 0 HRI FRI V2A SUB EXP Numbers in parentheses are for FS mode. – 22 – CXD2460R (4) 1 ≤ HSHUT < MAX (with low-speed electronic shutter) HSHUT value 1 to MAX 0 1 to MAX (with low-speed electronic shutter) 6 (76) 0 0 6 (76) HRI FRI V2A SUB EXP (5) HSHUT = 0 HSHUT value 1 to MAX 0 MAX 6 (76) 0 0 6 (76) 0 0 6 (76) HRI FRI V2A SUB EXP (6) HSHUT = 0 (with low-speed electronic shutter) HSHUT value 1 to MAX 0 0 (with low-speed electronic shutter) 6 (76) 0 6 (76) HRI FRI V2A SUB EXP Numbers in parentheses are for FS mode. – 23 – Chart A-1. FINE Mode (Vertical synchronization) FRI HRI 17 0/1068 1 V1 V2A V2B CXD2460R Mode FINE mode 1040 – 24 – Reset 12345678123456 XV3 XSUB PBLK XCPOB XCPDM WEN ID 1234567 OUT 0/1068 (Chart B-3) (Chart B-1) 1057 1 255 256 257 258 259 260 261 1017 1020 1025 1028 1033 1036 1 2 3 4 5 6 7 8 9 1 4 1 4 9 12 17 20 25 28 33 255 256 257 258 259 260 261 1017 1020 1025 1028 1033 1036 1 4 1 4 9 12 17 20 25 28 33 1 2 3 4 5 6 7 8 9 – 25 – XCPDM XCPOB PBLK Chart A-2. DRAFT Mode (Vertical synchronization) Mode DRAFT mode CXD2460R WEN OUT SUB V2B V2A HRI FRI V3 V1 ID 0/267 1 (Chart B-4) (Chart B-2) 5 0/267 1 5 Chart A-3. FS Mode (Vertical synchronization) FRI (Charts B-3/4) 5 0 74 75 5 Set by FVFS HRI The number of sweeps is specified by the serial data (20 × FVFS when FINE = 0, 8 × FVFS when FINE = 1). The number of sweeps is fixed (20 × 69H). V1 Chart B-2 when FINE = 0 in this period XSGB is not generated when FINE = 0 V2A V2B V3 The number of SUB pulses is specified by the serial data. – 26 – High when FINE = 1 Low when FINE = 0 FS mode SUB PBLK XCPOB XCPDM WEN ID OUT Mode FINE mode CXD2460R The mode is switched at the point where XSG is normally generated. 0 Chart B-1. FINE Mode (Horizontal synchronization) HRI 96 PBLK 0/1790 16 56 56 392 412 414 MCK 152 88 184 120 216 56 V1 V2A/B V3 – 27 – 152 216 H1 H2 SUB XCPOB 25 50 394 379 379 409 XCPDM ID/WEN EXP CXD2460R Chart B-2. DRAFT Mode (Horizontal synchronization) HRI PBLK 84 98 112 126 140 154 168 182 196 210 224 238 252 266 280 294 308 0/1790 16 56 56 70 322 336 350 364 378 392 412 414 MCK 98 112 126 252 168 210 154 196 238 280 294 140 182 224 266 308 322 336 350 364 378 V1 56 V2A/B 84 70 – 28 – 152 216 V3 H1 H2 SUB XCPOB 25 50 394 379 379 409 XCPDM ID/WEN EXP CXD2460R Chart B-3. Readout Timing (FINE mode) 2 bits 0/1270 HRI 50 bits 800 bits 0/1790 96 802 XV1 56 152 248 56 152 XV2A/XV2B 88 184 88 XV3 120 216 120 800 2 bits 51 bits 800 bits 802 850 – 29 – 248 184 216 XSGA XSGB V1 56 152 56 152 V2A/V2B 88 88 V3 120 120 CXD2460R EXP 56 70 84 112 126 154 168 196 210 238 252 280 294 322 336 364 364 392 378 322 350 336 364 280 308 294 322 238 266 252 280 196 154 112 70 98 140 182 224 84 126 168 196 210 238 112 154 70 378 800 850 802 71 85 113 127 155 169 197 211 71 113 57 99 141 84 155 197 183 225 168 – 30 – Chart B-4. Readout Timing (DRAFT mode) XV2A/B XSGB 800 850 XSGA EXP V2B V2A 950 992 126 154 196 210 XV3 140 182 224 266 308 350 392 802 50 bits 936 978 922 964 XV1 HRI V3 V1 0/1790 56 98 96 2 bits 0/1790 56 98 112 140 182 224 70 CXD2460R Chart B-5. FS Mode: V clock continuous drive (FINE = 1) 1 2 3 4 5 6 7 8 0/1790 HRI 412 0/1790 56 56 88 96 PBLK 56 MCK 440 376 472 568 664 760 856 952 1048 1144 1240 1336 1432 1528 536 632 824 1016 1208 1400 728 920 1112 1304 1496 152 184 152 248 344 V1 56 88 184 280 V2A/B 408 504 600 696 792 888 984 1080 1176 1272 1368 1464 1560 120 120 216 312 V3 – 31 – 392 392 394 409 379 56 56 H1 56 56 H2 152 216 SUB 25 50 25 50 XCPOB XCPDM ID/WEN CXD2460R 25 50 56 152 216 56 84 120 168 210 252 294 336 70 112 154 196 238 280 322 364 406 448 490 532 574 616 658 700 742 784 826 868 910 952 994 1036 1078 1120 1162 1204 1246 1288 1330 1372 1414 1456 1498 1540 1582 1624 1666 1708 56 98 140 379 392 392 394 409 25 50 56 56 84 126 154 70 112 56 98 140 – 32 – PBLK HRI Chart B-6. FS Mode: V clock continuous drive (FINE = 0) ID/WEN CXD2460R XCPDM XCPOB V2A/B MCK SUB H2 H1 V3 378 420 462 504 546 588 630 672 714 756 798 840 882 924 966 1008 1050 1092 1134 1176 1218 1260 1302 1344 1386 1428 1470 1512 1554 1596 1638 1680 1722 V1 182 224 266 308 350 392 434 476 518 560 602 644 686 728 770 812 854 896 938 980 1022 1064 1106 1148 1190 1232 1274 1316 1358 1400 1442 1484 1526 1568 1610 1652 1694 0/1790 56 1 2 3 4 412 0/1790 56 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 96 CXD2460R Logical Phase 2MCK MCK H1 H2 RG XSHP XSHD XRS ADCLK – 33 – CXD2460R Application Circuit A/D CXD2311AR DRVOUT VRT VRB D0 to D9 ADCLK XSHP XSHD XRS XCPOB XCPDM PBLK 2MCK MCK ID HRO FRO HRI FRI Signal Processor Block CDS/AGC CXA2006Q CCDOUT RG H1 H2 V1 V2A V2B V3 SUB CKI OSCO OSCI Timing Generator CXD2460R CCD Image Sensor ICX205AK SEN SSK SSI RST EXP TEST1 +3.3V TEST2 PS Controller For making FR and HR outside the CXD2460R, configure a circuit that counts MCK. (Using 2MCK, CKO, etc. is not recommended.) Also, set system setting data, SGXEN (D12) to "1" and stop a built-in SSG. Use crystal oscillator (fundamental wave) as base oscillation. Be sure to input duty 50% pulse when crystal oscillator is used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 34 – CXD2460R Notes on Turning Power ON To avoid setting VSUB pin of the CCD image sensor negative potential, the former two power supplies should be raised by the following order among three power supplies, VL and VH. VH t1 20% 0V 20% VL t2 t2 ≥ t1 – 35 – CXD2460R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 12 13 (0.22) + 0.05 0.127 – 0.02 0.13 M 0.1 ± 0.1 0.1 0.5 ± 0.2 S 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g – 36 –