CXD2492R

CXD2492R Timing Generator for Frame Readout CCD Image Sensor For the availability of this product, please contact the sales office. Description The CXD2492R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX252 CCD image sensor. Features • Base oscillation frequency 24 to 36MHz • High-speed/low-speed shutter function • Draft (sextuple speed)/AF (auto focus) drive • Horizontal driver for CCD image sensor • Vertical driver for CCD image sensor Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX252 (Type 1/1.8, 3240K pixels) Pin Configuration MCKO OSCO OSCI VDD5 VSS6 CKO SEN SCK CKI SSI HD VD 48 pin LQFP (Plastic) Absolute Maximum Ratings VSS – 0.3 to +7.0 • Supply voltage VDD VL –10.0 to VSS VH VL – 0.3 to +26.0 • Input voltage VI VSS – 0.3 to VDD + 0.3 • Output voltage VO1 VSS – 0.3 to VDD + 0.3 VO2 VO3 • Operating temperature Topr • Storage temperature Tstg VL – 0.3 to VSS + 0.3 VL – 0.3 to VH + 0.3 –20 to +75 –55 to +150 V V V V V V V °C °C 36 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 37 38 39 40 41 42 43 44 45 46 47 48 1 VSS1 35 34 33 32 31 30 29 28 27 26 25 24 VSS5 23 ADCLK 22 OBCLP 21 VSS4 20 CLPDM 19 PBLK 18 XRS 17 XSHD 16 XSHP 15 VDD4 14 VDD3 13 H2 Recommended Operating Conditions • Supply voltage VDDb 3.0 to 5.5 VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75 V V V V V °C ∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible. 2 RST 3 SNCSL 4 ID 5 WEN 6 SSGSL 7 VDD1 8 VDD2 9 RG 10 VSS2 11 VSS3 12 H1 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99730-PS CXD2492R Block Diagram XSHD VDD3 VDD2 XSHP VDD4 VSS3 VSS2 14 12 13 11 OSCI OSCO 28 27 8 9 10 15 16 17 18 21 XRS RG H1 H2 VSS4 19 PBLK 20 CLPDM 22 OBCLP 23 ADCLK 24 VSS5 4 5 ID WEN 41 V1A 43 V1B 39 V2 44 V3A 46 V3B 40 V4 47 SUB 42 VH 38 VM 45 VL CKI 26 Pulse Generator 1/2 CKO 25 MCKO 30 SNCSL 3 Selector Latch SSI 31 SCK 32 SEN 33 Selector SSGSL 6 SSG V Driver Register RST 2 TEST1 37 TEST2 48 7 VDD1 29 VDD5 1 VSS1 36 VSS6 35 HD 34 VD –2– CXD2492R Pin Description Pin No. 1 2 Symbol VSS1 RST I/O — I GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor Vertical direction line identification pulse output. Memory write timing pulse output. Internal SSG enable. High: Internal SSG valid, Low: External sync valid With pull-down resistor Description 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SNCSL ID WEN SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 CKO CKI OSCO OSCI VDD5 MCKO I O O I — — O — — O O — — O O O O O — O O — O I O I — O 3.3V power supply. (Power supply for common logic block) 3.3V power supply. (Power supply for RG) CCD reset gate pulse output. GND GND CCD horizontal register clock output. CCD horizontal register clock output. 3.3 to 5.0V power supply. (Power supply for H1/H2) 3.3V power supply. (Power supply for CDS block) CCD precharge level sample-and-hold pulse output. CCD data level sample-and-hold pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Pulse output for horizontal and vertical blanking period pulse cleaning. CCD dummy signal clamp pulse output. GND CCD optical black signal clamp pulse output. Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. GND Inverter output. Inverter input. Inverter output for oscillation. Inverter input for oscillation. 3.3V power supply. (Power supply for common logic block) System clock output for signal processing IC. –3– When not used, leave open or connect a capacitor. When not used, fix low. CXD2492R Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol SSI SCK SEN VD HD VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 I/O I I I I/O I/O — I — O O O — O O — O O I Description Serial interface data input for internal mode settings. Schmitt trigger input/No protective diode on power supply side Serial interface clock input for internal mode settings. Schmitt trigger input/No protective diode on power supply side Serial interface strobe input for internal mode settings. Schmitt trigger input/No protective diode on power supply side Vertical sync signal input/output. Horizontal sync signal input/output. GND IC test pin 1; normally fixed to GND. GND (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD vertical register clock output. –7.5V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD electronic shutter pulse output. IC test pin 2; normally fixed to GND. With pull-down resistor With pull-down resistor –4– CXD2492R Electrical Characteristics DC Characteristics Item Supply voltage 1 VDD2 Supply voltage 2 VDD3 Supply voltage 3 VDD4 Supply voltage 4 VDD1, VDD5 Input voltage 1∗1 RST SSI, SCK, Input voltage 2∗2 SEN, Input voltage 3∗3 TEST1, TEST2 Pins Symbol VDDa VDDb VDDc VDDd Vt+ Vt– Vt+ Vt– VIH1 VIL1 VIH2 VIL2 VIH3 Input/output voltage VD, HD VIL3 VOH1 VOL1 Output voltage 1 Output voltage 2 H1, H2 RG VOH2 VOL2 VOH3 VOL3 Feed current where IOH = –1.2mA Pull-in current where IOL = 2.4mA Feed current where IOH = –22.0mA VDDb – 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA V1A/B, V2, V3A/B, V4 = –8.25V V1A/B, V2, V3A/B, V4 = –0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = –8.25V SUB = 14.75V 5.4 –4.0 5.0 –7.2 10.0 –5.0 VDDd – 0.8 0.4 VDDd – 0.8 0.4 VDDc – 0.8 0.4 VDDa – 0.8 0.4 0.4 VDDd – 0.8 0.4 0.8VDDd 0.7VDDd 0.7VDDd 0.8VDDd (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.5 3.6 3.6 Unit V V V V V 0.2VDDd V V 0.2VDDd V V 0.2VDDd V V 0.3VDDd V V 0.2VDDd V V V V V V V V V V V V V mA mA mA mA mA mA SNCSL, Input voltage 4∗4 SSGSL Output voltage 3 XSHP, XSHD, VOH4 XRS, PBLK, OBCLP, CLPDM, VOL4 ADCLK CKO MCKO VOH5 VOL5 VOH6 VOL6 IOL IOM1 IOM2 IOH IOSL IOSH Output voltage 4 Output voltage 5 Output current 1 V1A, V1B, V3A, V3B, V2, V4 Output current 2 ∗1 ∗2 ∗3 ∗4 SUB This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC. These input pins are schmitt trigger inputs. These input pins are with pull-down resistor in the IC. These input pins are with pull-down resistor in the IC and they do not have protective diode of the power supply side in the IC. Note) The above table indicates the condition for 3.3V drive. –5– CXD2492R Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL RFB f Conditions (Within the recommended operating conditions) Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Max. Unit V V V V 0.4 500k 20 2M 5M 50 V Ω MHz OSCO OSCI, OSCO OSCI, OSCO Feed current where IOH = –3.6mA Pull-in current where IOL = 2.4mA VIN = VDDd or VSS VDDd – 0.8 Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = –7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –6– CXD2492R Switching Waveforms TTMH 90% TTHM VH 90% V1A (V1B, V3A, V3B) TTLM 10% 90% 10% 90% TTML VM 10% 10% VL TTLM 90% V2 (V4) 10% 90% TTML VM 10% VL TTLH 90% 90% TTHL VH SUB 10% 10% VL Waveform Noise VH VCMH VCML VCLH VCLL VL –7– CXD2492R Measurement Circuit Serial interface data CKI C6 VD HD +3.3V –7.5V +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 37 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C3 C1 C2 C2 C1 C2 C2 R1 38 39 40 41 42 43 44 R1 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 CXD2492R 24 23 22 21 20 19 18 17 16 15 14 13 C5 C6 C6 C6 C6 C6 C6 C6 C6 C2 C2 R1 C4 C5 C1 R1 3300pF 30Ω C2 R2 560pF 10Ω C3 820pF C4 30pF C5 215pF C6 10pF –8– CXD2492R AC Characteristics AC characteristics between the serial interface clocks 0.8VDDd SSI SCK SEN SEN ts2 0.2VDDd 0.8VDDd ts1 0.2VDDd ts3 0.8VDDd th1 (Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns ts1 th1 ts2 ts3 Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD V1A 0.2VDDd ts1 0.8VDDd SEN th1 0.2VDDd ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HD SEN hold time, activated by the falling edge of HD Min. 0 102 Typ. Max. Unit ns µs ts1 th1 –9– CXD2492R Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD HD 0.2VDDd ts1 SEN 0.8VDDd th1 0.2VDDd ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of VD SEN hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns ts1 th1 Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2492R at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD2492R and controlled at the rising edge of SEN. See "Description of Operation". SEN 0.8VDDd Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns tpdPULSE Output signal delay, activated by the rising edge of SEN – 10 – CXD2492R RST loading characteristics RST 0.8VDDd 0.2VDDd tw1 (Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns tw1 VD and HD loading characteristics VD, HD 0.2VDDd ts1 0.8VDDd th1 0.2VDDd MCKO MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition VD and HD setup time, activated by the rising edge of MCKO VD and HD hold time, activated by the rising edge of MCKO Min. 20 5 Typ. Max. Unit ns ns ts1 th1 Output variation characteristics MCKO 0.8VDDd WEN, ID tpd1 WEN and ID load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 20 Typ. Max. 60 Unit ns – 11 – CXD2492R Description of Operation Pulses output from the CXD2492R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS1 RST SNCSL ID WEN SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD XRS PBLK CLPDM VSS4 OBCLP ADCLK VSS5 ACT ACT L L — ACT ACT ACT ACT ACT L L L L L — L L H ACT ACT ACT L L — — L L L L L ACT ACT ACT H H ACT L — — L L ACT ACT ACT ACT ACT ACT ACT ACT ACT L L ACT — — L ACT CAM SLP — ACT ACT L L ACT L ACT L L ACT STB RST Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKO CKI OSCO OSCI VDD5 MCKO SSI SCK SEN VD∗1 HD∗1 VSS6 TEST1 VM V2 V4 V1A VH V1B V3A VL V3B SUB TEST2 ACT ACT VH VH — ACT ACT VH VH — VH VH VL VL ACT ACT ACT VM VM VH — VH VH VM VL ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L L — — — VM VM VH VM VL VM CAM ACT ACT ACT ACT SLP ACT ACT ACT ACT — L ACT ACT ACT L L ACT DIS DIS DIS H H STB L ACT ACT ACT RST ACT ACT ACT ACT ∗1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45), respectively, in the controlled status. – 12 – CXD2492R Serial Interface Control The CXD2492R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN. SSI SCK SEN 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 There are two categories of serial interface data: CXD2492R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below. – 13 – CXD2492R Control Data Data D00 to D07 D08 to D09 D10 to D12 D13 to D14 D15 D16 to D23 D24 to D33 D34 D35 D36 to D37 D38 to D39 D40 to D47 LDAD Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 0 All 0 All 0 1 0 1 ADCLK logic phase switching See D36 to D37 LDAD. 0 STB Standby control See D38 to D39 STB. All 0 All 0 10000001 → Enabled Other values → Disabled CTG Category switching See D08 to D09 CTG. MODE Drive mode switching See D10 to D12 MODE. SMD PTSG CDAT Electronic shutter mode switching Internal SSG output pattern switching AF drive control data See D13 to D14 SMD. NTSC equivalent PAL equivalent See D16 to D23 CDAT. — — — — — — — — — — — — — — — — – 14 – CXD2492R Shutter Data Data D00 to D07 D08 to D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0 10000001 → Enabled Other values → Disabled CTG Category switching See D08 to D09 CTG. SVD Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification See D10 to D19 SVD. SHD See D20 to D31 SHD. SPL See D32 to D41 SPL. — — — — – 15 – CXD2492R Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD2492R by the serial interface, the CXD2492R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode Note that the CXD2492R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D10 to D12 MODE [Drive mode] The CXD2492R drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD2492R and reflected at the falling edge of VD. D12 0 0 0 0 1 1 D11 0 0 1 1 0 1 D10 0 1 0 1 X X Description of operation Draft mode (sextuple speed: default) Frame mode (A field readout) Frame mode (B field readout) Frame mode AF1 mode AF2 mode Control data: D15 PTSG [Internal SSG output pattern] The CXD2492R internal SSG output pattern can be switched as follows. However, the drive mode bits are loaded to the CXD2492R and reflected at the falling edge of VD. D15 0 1 Description of Operation NTSC equivalent pattern PAL equivalent pattern VD period in each pattern is defined as follows. Frame mode NTSC equivalent pattern PAL equivalent pattern 918H + 1716ck 945H∗1 Draft mode 262H + 1144ck 314H + 1568ck AF1 mode 131H + 572ck 157H + 784ck AF2 mode 65H + 1430ck 78H + 1536ck ∗1 Only 944H and 945H are 1208ck period. See the Timing Charts for the actual operation. – 16 – CXD2492R Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment (°) 0 90 180 270 Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD2492R and control is applied immediately at the rising edge of SEN. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode See the Pin Status Table for the pin status in each mode. – 17 – CXD2492R Control data: [AF drive] The CXD2492R controls the drive of the vertical cut-out area of line in AF1/AF2 mode by using control data D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and this mode cannot support operation such as electrical image stabilization. AF drive bits are loaded to the CXD2492R and reflected at the falling edge of VD. As shown in the figure below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then normal transfer is performed equivalent to draft mode from the frame shift of the stage specified by the serial interface data to the timing of the falling edge of the next VD. Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for its application. VD High-speed sweep V1A Vck MODE CDAT 0 00h 4 FFh 0 00h Normal transfer Frame shift The number of high-speed sweeps are different according to the selected mode. It is specified as follows. AF1 mode: 138 stages (0 to 7H) AF2 mode: 208 stages (0 to 11H) The frame shift data is expressed as shown in the table below using D16 to D23 CDAT. MSB D23 0 D22 D21 1 ↓ 6 1 D20 0 D19 D18 1 0 ↓ 9 D17 0 LSB D16 1 → CDAT is expressed as 69h . Its definition area is specified as follows. AF1 mode: 00h ≤ CDAT ≤ FFh (11 to 23H) AF2 mode: 00h ≤ CDAT ≤ FFh (14 to 27H) – 18 – CXD2492R Control data/shutter data: [Electronic shutter] The CXD2492R realizes various electronic shutter functions by using control data D13 to D14 SMD and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 to D14 SMD. D14 0 0 1 1 D13 0 1 0 1 Description of operation Electronic shutter stopped mode High-speed/low-speed shutter mode HTSG control mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as dummy on this IC. MSB D31 X D30 0 ↓ 1 D29 0 D28 1 D27 1 D26 1 ↓ C D25 0 D24 0 D23 D22 0 0 ↓ 3 LSB D21 D20 1 1 → SHD is expressed as 1C3h . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). However, in the frame mode A field, it matches (number of SUB pulses + 1). This is a specification for flickerless when the same mode is repeated. But this change may not occur because of flickerless by the conditions during low-speed shutter. Note) The bit data definition area is assured in terms of the CXD2492R functions, and does not assure the CCD characteristics. – 19 – CXD2492R VD SHD SVD V1A SUB WEN SMD SVD SHD 01 002h 10Fh 01 000h 050h Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL VD SHD V1A SUB WEN SMD SPL SVD SHD 10 001h 002h 10Fh 01 000h 000h 0A3h SVD Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa. – 20 – CXD2492R [HTSG control mode] During this mode, all shutter data items are invalid. The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure. VD V1A SUB Vck WEN SMD 01 11 01 Exposure time – 21 – Chart-1 • ICX252 Vertical Direction Timing Chart MODE Frame mode Applicable CCD image sensor A Field B Field VD 29 34 810 918 1 28 34 810 918 1 HD SUB A High-speed sweep block C High-speed sweep block C B V1A V1B V2 V3A 1542 1544 1546 1548 1550 1539 1541 1543 1545 1547 CCD OUT PBLK OBCLP CLPDM ID WEN CXD2492R ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (918H + 1716ck units). For PAL equivalent pattern, it is 945H units, but 1208ck period as for 944H and 945H. 1549 – 22 – 1 3 5 7 1 3 5 7 9 11 13 15 V3B V4 2 4 6 8 2 4 6 8 10 12 Chart-2 • ICX252 Vertical Direction Timing Chart MODE Draft mode Applicable CCD image sensor VD 261 262 1 2 261 262 1 2 HD SUB D D V1A V1B V2 V3A – 23 – 6 3 10 15 22 27 34 4 1 8 13 20 25 32 V3B V4 527 534 539 546 525 532 537 544 549 CCD OUT 527 534 539 546 525 532 537 544 549 6 3 10 15 22 27 34 4 1 8 13 20 25 32 PBLK OBCLP CLPDM ID WEN CXD2492R ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (262H + 1144ck units). For PAL equivalent pattern, it is 314H + 1568ck units. Chart-3 AF1 mode • ICX252 Vertical Direction Timing Chart MODE Applicable CCD image sensor VD 8 10 10 25 131 1 8 25 131 1 HD SUB G Frame shift block F High-speed sweep block D F High-speed sweep block D G Frame shift block V1A V1B V2 V3A – 24 – 6 4 V3B V4 6 4 CCD OUT PBLK OBCLP CLPDM ID WEN ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ 138 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block. ∗ VD of this chart is NTSC equivalent pattern (131H + 572ck units). For PAL equivalent pattern, it is 157H + 784ck units. CXD2492R Chart-4 • ICX252 Vertical Direction Timing Chart MODE AF2 mode Applicable CCD image sensor VD 12 14 14 29 65 1 12 29 65 1 HD SUB D Frame shift block High-speed sweep block F High-speed sweep block G F DG Frame shift block V1A V1B V2 V3A – 25 – 6 4 V3B V4 6 4 CCD OUT PBLK OBCLP CLPDM ID WEN ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ 208 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block. ∗ VD of this chart is NTSC equivalent pattern (65H + 1430ck units). For PAL equivalent pattern, it is 78H + 1536ck units. CXD2492R Chart-5 • ICX252 Horizontal Direction Timing Chart MODE Frame mode Applicable CCD image sensor (2228) 0 50 200 250 100 150 HD MCKO 52 172 H1 H2 70 110 V1A/B 99 148 V2 52 128 V3A/B 90 157 – 26 – 70 138 52 174 110 110 V4 SUB 198 PBLK 10 47 OBCLP 198 CLPDM ID WEN ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-1. CXD2492R Chart-6 • ICX252 Horizontal Direction Timing Chart MODE Draft/AF1/AF2 mode Applicable CCD image sensor (2228) 0 50 100 150 200 250 HD MCKO 52 172 H1 H2 52 71 90 128 109 147 V1A/B 64 83 102 140 121 159 V2 52 71 109 147 90 128 V3A/B 64 102 83 140 121 159 – 27 – 71 140 52 174 110 110 V4 SUB 198 PBLK 10 47 OBCLP 198 CLPDM ID WEN ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4. CXD2492R Chart-7 Frame mode • ICX252 Horizontal Direction Timing Chart (High-speed sweep: C) MODE Applicable CCD image sensor (2228) 0 50 200 250 100 150 HD MCKO 52 172 H1 H2 52 81 110 139 168 197 226 255 V1A/B 71 129 100 158 187 216 245 274 V2 52 110 168 81 139 197 226 255 V3A/B 71 100 129 158 187 216 245 274 – 28 – #1 70 138 V4 #2 #3 #4 SUB PBLK OBCLP CLPDM ID WEN ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 26H of 768ck (#1038). CXD2492R Chart-8 • ICX252 Horizontal Direction Timing Chart (High-speed sweep: F) (Frame shift: G) 50 100 150 200 250 MODE AF1/AF2 mode Applicable CCD image sensor (2228) 0 HD MCKO 52 172 H1 H2 52 71 90 128 166 204 109 147 185 223 242 261 V1A/B 64 83 102 140 178 121 159 197 216 235 254 273 V2 52 71 109 147 166 185 90 128 204 223 242 261 280 V3A/B 64 83 102 121 140 159 178 197 216 235 254 273 V4 71 – 29 – #1 140 52 105 110 #2 SUB PBLK 10 47 OBCLP CLPDM 219 ID WEN ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ WEN are output at the timing shown above at the position shown in Chart-3 and 4. ∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 6H of 2056ck (#138) in AF1 mode and 10H of 884ck (#208) in AF2 mode. ∗ Frame shift of V1A/B, V2, V3A/B and V4 receives the output control by the serial interface data and it can specify up to #255 for both of AF1/AF2 mode. ∗ ID is output at the timing shown with dotted line during frame shift. CXD2492R Chart-9 • ICX252 Horizontal Direction Timing Chart MODE Frame mode Applicable CCD image sensor 52 70 90 99 110 128 148 157 181 211 241 1100 1130 1160 1190 1250 1280 1310 52 70 90 99 110 128 (2288) 0 (2288) 0 HD [A] [A Field] V1A V1B V2 V3A V3B – 30 – [B] V4 [B Field] V1A V1B V2 V3A V3B V4 Logic alignment portion CXD2492R ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. 148 157 Chart-10 Draft /AF1/AF2 mode • ICX252 Horizontal Direction Timing Chart MODE Applicable CCD image sensor 52 64 71 83 90 102 109 121 128 140 147 159 1010 1040 1070 1100 1130 1160 1190 1220 1250 1280 1310 1340 1370 1400 1430 52 64 71 83 90 102 109 121 128 140 147 (2288) 0 (2288) 0 HD [D] V1A V1B – 31 – V2 V3A V3B V4 ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. 159 CXD2492R Chart-11 • ICX252 High-speed Phase Timing Chart MODE Applicable CCD image sensor HD HD' CKI CKO ADCLK 52 172 1 MCKO – 32 – H1 H2 RG XSHP XSHD XRS CXD2492R ∗ HD' indicates the HD which is the actual CXD2492R load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. Chart-12 • ICX252 Vertical Direction Sequence Chart MODE Draft → Frame → Draft Applicable CCD image sensor VD V1A V1B V2 V3A V3B – 33 – Close B B 0 01 050h 050h 050h 01 01 0 0 C E 3 00 000h C D E V4 SUB Open F E 3 00 000h 0 01 050h F 0 01 050h Mechanical shutter Exposure time A CCD OUT A MODE 0 0 SMD 01 01 SHD 050h 050h ∗ This chart is a drive timing chart example of electronic shutter normal operation. ∗ Data exposed at D includes blooming component. For details, see CCD image sensor specification. ∗ CXD2492R does not generate the pulse to control mechanical shutter operation. ∗ The switching timing of drive mode and electronic shutter data is not the same. CXD2492R CXD2492R Application Circuit Block Diagram DRVOUT VRT VRB OBCLP CCD ICX252 CCD OUT S/H CXA2006Q CLPDM A/D CXD2311AR ADCLK D0 to 9 10 XSHD XSHP PBLK XRS H1 H2 RG V1A V1B V2 V3A V3B V4 SUB 16 17 18 19 20 22 12 13 9 41 43 39 44 46 40 47 26 27 28 37 48 V-Dr TG CXD2492R 23 25 30 34 35 4 5 2 3 6 31 32 33 CKO MCKO VD HD ID WEN Signal processor Block 15.0V 0V –7.5V RST SNCSL SSGSL CKI OSCO TEST1 TEST2 OSCI SCK SEN SSI Controller Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes for Power-on Of the three –7.5V, +15.0V and +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential. t1 20% 20% t2 t2 ≥ t1 – 34 – CXD2492R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 12 13 B (0.22) + 0.05 0.127 – 0.02 0.13 M 0.1 0.1 ± 0.1 0.5 ± 0.2 S (0.127) +0.05 0.127 – 0.02 (0.18) 0.18 ± 0.03 0° to 10° 0.5 ± 0.2 DETAIL B:SOLDER DETAIL A DETAIL B:PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g – 35 – 0.127 ± 0.04 + 0.08 0.18 – 0.03