CXD2498R

CXD2498R Timing Generator for Frame Readout CCD Image Sensor Description The CXD2498R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX282 CCD image sensor. Features • Base oscillation frequency 45MHz • Electronic shutter function • Supports various drive modes such as draft and AF mode • Horizontal driver for CCD image sensor • Vertical driver for CCD image sensor Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX282 (Type 2/3, 5070K pixels) 48 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.3 to +7.0 V VL –10.0 to VSS V VH VL – 0.3 to +26.0 V • Input voltage VI VSS – 0.3 to VDD + 0.3 V • Output voltage VO1 VSS – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V VO3 VL – 0.3 to VH + 0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDDa, VDDb, VDDc 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75 V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00X63-PS CXD2498R Block Diagram VDD2 VDD3 H1A H1B H2A 8 11 16 10 12 13 15 H2B RG 9 14 18 19 VCO XSHD XSHP VSS2 VSS3 17 VDD4 20 PBLK CKI 21 CLPDM 26 Pulse Generator 1/2 22 OBCLP 23 ADCLK 24 VSS4 4 5 ID/EXP WEN CKO 25 MCKO 30 SNCSL 3 Selector Latch 40 V1A 42 V1B 43 V1C SSI 31 SCK 32 SEN 33 Selector Register 38 V2 44 V3A 46 V3B V Driver 47 V3C 39 V4 48 SUB 41 VH 37 VM 45 VL SSGSL 6 SSG RST 2 TEST1 27 TEST2 28 7 VDD1 29 VDD5 1 VSS1 36 VSS5 35 HD 34 VD –2– CXD2498R Pin Configuration TEST2 MCKO VSS5 TEST1 VDD5 SEN SCK SSI HD VD 36 VM V2 V4 V1A VH V1B V1C V3A VL V3B V3C SUB 37 38 39 40 41 42 43 44 45 46 47 48 1 35 34 33 32 31 30 29 28 27 26 25 24 VSS4 23 ADCLK 22 OBCLP 21 CLPDM 20 PBLK 19 XSHD 18 XSHP 17 VDD4 16 VDD3 15 H2B 14 VSS3 13 H2A 2 3 4 5 6 7 8 9 10 11 12 VDD1 SNCSL ID/EXP WEN VSS1 VSS2 RST VDD2 SSGSL ∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible. –3– H1A H1B RG CKO CKI CXD2498R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol VSS1 RST SNCSL ID/EXP WEN SSGSL VDD1 RG VSS2 H1A VDD2 H1B H2A VSS3 H2B VDD3 VDD4 XSHP XSHD PBLK CLPDM OBCLP ADCLK VSS4 CKO CKI TEST1 TEST2 VDD5 MCKO SSI I/O — I I O O I — O — O — O O — O — — O O O O O O — O I I I — O I GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor Description Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) Memory write timing pulse output. Internal SSG enable. High: Internal SSG valid, Low: External sync valid With pull-down resistor 3.3V power supply. (Power supply for common logic block) CCD reset gate pulse output. GND CCD horizontal register clock output. 3.3V power supply. (Power supply for H block) CCD horizontal register clock output. CCD horizontal register clock output. GND CCD horizontal register clock output. 3.3V power supply. (Power supply for H block) 3.3V power supply. (Power supply for CDS block) CCD precharge level sample-and-hold pulse output. CCD data level sample-and-hold pulse output. Pulse output for horizontal and vertical blanking period pulse cleaning. CCD dummy signal clamp pulse output. CCD optical black signal clamp pulse output. The horizontal OB pattern can be changed using the serial interface data. Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. GND Inverter output. Inverter input. IC test pin 1; normally fixed to GND. IC test pin 2; normally fixed to GND. 3.3V power supply. (Power supply for common logic block) System clock output for signal processing IC. Serial interface data input for internal mode settings. Schmitt trigger input –4– With pull-down resistor With pull-down resistor CXD2498R Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol SCK SEN VD HD VSS5 VM V2 V4 V1A VH V1B V1C V3A VL V3B V3C SUB I/O I I I/O I/O — — O O O — O O O — O O O Description Serial interface clock input for internal mode settings. Schmitt trigger input Serial interface strobe input for internal mode settings. Schmitt trigger input Vertical sync signal input/output. Horizontal sync signal input/output. GND GND (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. –7.5V power supply. (Power supply for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD electronic shutter pulse output. –5– CXD2498R Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Pins VDD2, VDD3 VDD4 VDD1, VDD5 Symbol VDDa VDDb VDDc Vt+ Vt– 0.7VDDc 0.2VDDc 0.8VDDc 0.2VDDc Feed current where IOH = –1.2mA VDDc – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –22.0mA VDDa – 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = –3.3mA VDDc – 0.8 Pull-in current where IOL = 2.4 mA Feed current where IOH = –3.3mA VDDb – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –6.9mA VDDc – 0.8 Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA VDDc – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA VDDc – 0.8 Pull-in current where IOL = 4.8mA V1A/B/C, V2, V3A/B/C, V4 = –8.25V V1A/B/C, V2, V3A/B/C, V4 = –0.25V V1A/B/C, V3A/B/C = 0.25V V1A/B/C, V3A/B/C = 14.75V SUB = –8.25V SUB = 14.75V 5.4 –4.0 5.0 –7.2 10.0 –5.0 0.4 0.4 0.4 0.4 0.4 0.4 0.4 (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 0.8VDDc 0.2VDDc Typ. 3.3 3.3 3.3 Max. 3.6 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA Input voltage RST, SSI, SCK, SEN 1∗1 Input voltage TEST1, TEST2, VIH1 SNCSL, SSGSL VIL1 2∗2 VIH2 Input/output voltage VD, HD VIL2 VOH1 VOL1 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 H1A, H1B, H2A, H2B RG VOH2 VOL2 VOH3 VOL3 XSHP XSHD, , VOH4 PBLK, OBCLP , CLPDM, ADCLK VOL4 CKO MCKO ID/EXP, WEN VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL Output current 1 V1A, V1B, V1C, V3A, V3B, V3C, V2, V4 IOM1 IOM2 IOH IOSL IOSH Output current 2 SUB ∗1 This input pin is a schmitt trigger input. ∗2 This input pin is with pull-down registor in the IC. –6– CXD2498R Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax = 50MHz sine wave 0.3 0.7VDDc 0.3VDDc Conditions Min. Typ. VDDc/2 Max. Unit V V V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Symbol TTLM TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = –7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V Note) 1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –7– CXD2498R Switching Waveforms TTMH 90% TTHM VH 90% V1A (V1B, V1C, V3A, V3B, V3C) TTLM 10% 90% 10% 90% TTML VM 10% 10% VL TTLM 90% V2 (V4) 10% 90% TTML VM 10% VL TTLH 90% 90% TTHL VH SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –8– CXD2498R Measurement Circuit Serial interface data CKI C6 VD HD +3.3V –7.5V +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 37 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C3 C1 C2 C2 C1 C2 C2 R1 38 39 40 41 42 43 44 R1 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 CXD2498R 24 23 22 21 20 19 18 17 16 15 14 13 C5 C5 C6 C6 C6 C6 C6 C6 C6 C2 C2 R1 C4 C5 C5 C1: 3300pF R1: 30Ω C2: 560pF R2: 10Ω C3: 820pF C4: 8pF C5: 320pF C6: 10pF –9– CXD2498R AC Characteristics AC characteristics between the serial interface clocks 0.8VDDc SSI SCK SEN SEN ts2 0.2VDDc 0.8VDDc ts1 0.2VDDc ts3 0.8VDDc th1 (Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns ts1 th1 ts2 ts3 Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD V1A 0.2VDDc ts1 0.8VDDc SEN th1 0.2VDDc ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period during which V1A/B/C and V3A/B/C values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HD SEN hold time, activated by the falling edge of HD Min. 0 134 Typ. Max. Unit ns µs ts1 th1 ∗ Restriction in draft mode with an operating frequency of 22.5MHz. – 10 – CXD2498R Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD HD 0.2VDDc ts1 SEN 0.8VDDc th1 0.2VDDc ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of VD SEN hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns ts1 th1 ∗ Restriction with an operating frequency of 22.5MHz. Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2498R at the timing shown in “Serial interface clock internal loading characteristics (1)” above. However, one exception to this is when the data such as STB is loaded to the CXD2498R and controlled at the rising edge of SEN. See ”Description of Operation”. SEN 0.8VDDc Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 70 Uniy ns tpdPULSE Output signal delay, activated by the rising edge of SEN – 11 – CXD2498R RST loading characteristics RST 0.8VDDc 0.2VDDc tw1 (Within the recommended operating conditions) Symbol Definition RST pulse width Min. 22 Typ. Max. Unit ns tw1 VD and HD phase characteristics VD 0.2VDDc ts1 th1 0.2VDDc 0.2VDDc HD (Within the recommended operating conditions) Symbol Definition VD setup time, activated by the falling edge of HD VD hold time, activated by the falling edge of HD Min. 0 44 Typ. Max. Unit ns ns ts1 th1 HD loading characteristics HD 0.2VDDd ts1 th1 0.8VDDd 0.2VDDd MCKO MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition HD setup time, activated by the rising edge of MCKO HD hold time, activated by the rising edge of MCKO Min. 31 0 Typ. Max. Unit ns ns ts1 th1 – 12 – CXD2498R Output variation characteristics 0.8VDDc MCKO WEN, ID/EXP tpd1 WEN and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition Time until the above outputs change after the rise of MCKO Min. 23 Typ. Max. 33 Unit ns tpd1 – 13 – CXD2498R Description of Operation Pulses output from the CXD2498R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS1 RST SNCSL ID/EXP WEN SSGSL VDD1 RG VSS2 H1A VDD2 H1B H2A VSS3 H2B VDD3 VDD4 XSHP XSHD PBLK CLPDM OBCLP ADCLK VSS4 ACT ACT ACT ACT ACT ACT L L L L L L — ACT L — — L L L L L L ACT ACT H H H ACT ACT ACT L L — L ACT ACT L — L L ACT ACT ACT L — L ACT ACT ACT ACT ACT ACT ACT ACT L L ACT — L ACT CAM SLP — ACT ACT L L ACT L ACT L L ACT STB RST Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKO CKI TEST1 TEST2 VDD5 MCKO SSI SCK SEN VD∗1 HD∗1 VSS5 VM V2 V4 V1A VH V1B V1C V3A VL V3B V3C SUB ACT ACT ACT VH VH VH ACT ACT ACT VH VH VH — VH VH VH VL VL VL ACT ACT ACT VM VM VH — VH VH VH VM VM VL ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L L — — VM VM VH VM VL VM CAM ACT ACT SLP ACT ACT — — — L ACT ACT ACT L L ACT DIS DIS DIS H H STB L ACT RST ACT ACT ∗1 It is for output. For input, all items are “ACT”. Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 41), VM (Pin 37) and VL (Pin 45), respectively, in the controlled status. – 14 – CXD2498R Serial Interface Control The CXD2498R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B/C and V3A/B/C, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN. SSI SCK SEN 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 These are two categories of serial interface data : the CXD2498R drive control data (hereafter “control data”) and electronic shutter data (hereafter “shutter data”). The details of each data are described below. – 15 – CXD2498R Control Data Data D00 to D07 D08 to D09 D10 to D11 D12 D13 D14 D15 D16 to D17 D18 to D32 D33 D34 to D35 D36 to D37 D38 to D39 D40 to D47 EXP PTOB PTMD SMD HTSG — Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 0 0 0 0 All 0 All 0 0 All 0 1 LDAD ADCLK logic phase adjustment See D36 to D37 LDAD. 0 STB Standby control See D38 to D39 STB. All 0 All 0 10000001 → Enabled Other values → Disabled See D08 to D09 CTG. CTG Category switching MODE — Drive mode switching — Electronic shutter mode switching∗1 HTSG control switching∗1 — Drive mode pattern switching See D10 to D11 MODE. — OFF OFF — — ON ON — See D16 to D17 PTMD. — — ID/EXP output switching OBCLP waveform pattern switching — ID — EXP See D34 to D35 PTOB. — — — — ∗1 See D13 SMD. – 16 – CXD2498R Shutter Data Data D00 to D07 D08 to D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 0 10000001 → Enabled Other values → Disabled See D08 to D09 CTG. CTG Category switching Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification — SVD See D10 to D19 SVD. SHD See D20 to D31 SHD. SPL See D32 to D41 SPL. — — – 17 – CXD2498R Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD2498R by the serial interface, the CXD2498R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode Note that the CXD2498R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D34 to D35 PTOB [OBCLP waveform pattern] This specifies the OBCLP waveform pattern. The default is “Normal”. See the Timing Charts for details. D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Rearward) (Forward) (Wide) Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment (°) 0 90 180 270 Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD2498R and control is applied immediately at the rising edge of SEN. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode See the Pin Status Table for the pin status in each mode. – 18 – CXD2498R Control data: [Drive mode] The CXD2498R realizes various drive modes by using control data D10 to D11 MODE and D16 to D17 PTMD. The drive mode bits are loaded to the CXD2498R and reflected at the falling edge of VD. These details are described below. First, the basic drive mode is assigned using the control data D10 to D11 MODE. D11 0 0 1 1 D10 0 1 0 1 Description of operation Draft mode (default) Progressive scan mode Double speed mode Frame mode Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX282. This is a high frame rate drive mode that can be used for purposes such as monitoring and auto focus (AF). Progressive scan mode is the pulse eliminator drive mode called double speed mode (1) in the ICX282. Pulse elimination is performed, but the frame data is obtained over one field period and corresponds to progressive scan drive, so it is called progressive scan mode in this data sheet. Double speed mode is the pulse eliminator drive mode called double speed mode (2) in the ICX282. Readout is applied with two lines added to provide an image which appears like frame mode with an increased frame rate. This drive mode is comprised of A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so on. Frame mode is the ICX282 drive mode in which the data for all lines are read. This drive mode is also comprised of A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so on like double speed mode. [Special drive modes] Of the above basic drive modes, when a drive mode other than double speed mode is specified, special drive modes can be specified using the control data D16 to D17 PTMD. Description of operation Draft mode Draft mode AF1 mode AF2 mode Progressive scan mode Center scan 1 mode Center scan 2 mode Frame mode Center scan 1 mode Center scan 2 mode D17 0 1 1 D16 X 0 1 Progressive scan mode Frame mode See the Timing Charts for details of all drive modes. Note that center scan modes (3) and (4) in the ICX282 correspond to center scan 1 and 2 in frame mode, and center scan modes (1) and (2) in the ICX282 correspond to center scan 1 and 2 in progressive scan mode. – 19 – CXD2498R Control data/shutter data: [Electronic shutter] The CXD2498R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 SMD. D13 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 D30 X 0 ↓ 1 LSB D23 D22 D21 D20 0 0 ↓ 3 1 1 SHD is expressed as 1C3H . D29 D28 0 1 D27 D26 1 1 ↓ C D25 D24 0 0 [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [Electronic shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) Note) The bit data definition area is assured in terms of the CXD2498R functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)} Concretely, when specifying high-speed shutter, SVD is set to “000h”. (See the figure.) During low-speed shutter, or in other words when SVD is set to “001h” or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). – 20 – CXD2498R VD V1A SUB WEN EXP SMD SVD SHD SHD SVD 1 002h 10Fh 1 000h 050h Exposure time Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL 000 VD SHD V1A SUB WEN EXP SMD SPL SVD SHD 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVD 002 Exposure time Incidentally, SPL is counted as “000h”, “001h”, “002h” and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. – 21 – CXD2498R [HTSG control mode] This mode controls the V1A/B/C and V3A/B/C ternary level outputs (readout pulse block) using D14 HTSG. When control is applied, V pulse modulation does not occur during the readout period, and only normal V transfer is performed. D14 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode VD V1A SUB Vck WEN EXP HTSG SMD 0 1 1 0 0 1 Exposure time [EXP pulse] The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP The . default is the “ID” pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. The transition point is midpoint value (1515ck) of the last SUB pulse falling edge and each V1A/ B/C and V3A/B/C ternary output falling edge. When there is no SUB pulse, the later ternary output falling edge (1590ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation. – 22 – Chart-1 Vertical Direction Timing Chart A Field MODE Frame mode Applicable CCD image sensor • ICX282 B Field VD 1013 1017 1 73 78 1059 1 27 32 HD SUB C V1A High-speed sweep block A D High-speed sweep block B V1B V1C V2 V3A 1952 1954 1956 1958 1960 1941 1943 1945 1947 1949 1951 1953 1955 1957 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 1 3 5 7 1 3 5 7 9 11 13 15 1959 – 23 – V3B V3C V4 2 4 6 8 2 4 6 8 10 12 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 1059H in the A Field and 1017H in the B Field (2894ck in both cases). The B Field 1016H only has a 950ck period. Chart-2 Vertical Direction Timing Chart MODE Progressive scan mode Applicable CCD image sensor • ICX282 VD 1038 1 49 54 1038 1 49 54 HD SUB C V1A High-speed sweep block E C High-speed sweep block E V1B V1C V2 V3A 1949 1950 1953 1954 1957 1958 1946 1949 1950 1953 1954 1957 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 2 5 6 1 2 5 6 9 10 13 14 1958 – 24 – V3B V3C V4 2 5 6 1 2 5 6 9 10 13 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 1038H period (2894ck). 1037H only has a 1922ck period. Chart-3 Vertical Direction Timing Chart A Field MODE Double speed mode Applicable CCD image sensor • ICX282 B Field VD 519 527 1 69 72 563 1 25 28 HD SUB H V1A High-speed sweep block F I High-speed sweep block G V1B V1C V2 V3A 1949 1951 1953 1955 1958 1960 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 3 7 3 7 11 15 19 23 27 31 35 39 1 5 1 5 9 13 17 21 25 29 33 37 1957 1959 – 25 – V3B V3C V4 4 8 4 8 12 16 20 24 28 32 2 6 2 6 10 14 18 22 26 30 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 563H in the A Field and 527H in the B Field (3102ck in both cases). The B Field 525H has a 1700ck period and 526H has a 1699ck period. Chart-4 Vertical Direction Timing Chart MODE Draft mode Applicable CCD image sensor • ICX282 VD 249 1 2 249 1 2 HD SUB J V1A J V1B V1C V2 1937 1941 1946 1950 1937 1941 1946 1950 1953 1957 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 6 5 14 21 30 37 2 1 10 17 26 33 1953 1957 – 26 – V3A V3B V3C V4 6 5 14 21 30 37 2 1 10 17 26 33 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 249H (3022ck) period. 248H only has a 1294ck period. Chart-5 Vertical Direction Timing Chart A Field MODE Frame mode (center scan 1) Applicable CCD image sensor • ICX282 B Field VD 530 1 71 91 576 1 25 45 HD SUB C V1A High-speed sweep block A K Frame shift block D High-speed sweep block B K Frame shift block V1B V1C V2 V3A 497 499 501 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 1 2 498 – 27 – V3B V3C V4 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 576H in the A Field and 530H in the B Field (2894ck in both cases). Chart-6 Vertical Direction Timing Chart A Field MODE Frame mode (center scan 2) Applicable CCD image sensor • ICX282 B Field VD 302 1 71 100 347 1 25 54 HD SUB C V1A High-speed sweep block A K Frame shift block D High-speed sweep block B K Frame shift block V1B V1C V2 V3A 735 737 739 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 1 2 736 – 28 – V3B V3C V4 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 347H in the A Field and 302H in the B Field (2894ck in both cases). The B Field 301H only has a 1563ck period. Chart-7 Vertical Direction Timing Chart MODE Progressive scan mode (center scan 1) Applicable CCD image sensor • ICX282 VD 519 1 12 33 519 1 12 33 HD SUB C V1A High-speed sweep block E K Frame shift block C High-speed sweep block E K Frame shift block V1B V1C V2 501 502 505 501 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 2 2 502 – 29 – V3A V3B V3C V4 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 519H (2894ck) period. 518H only has a 2408ck period. Chart-8 Vertical Direction Timing Chart MODE Progressive scan mode (center scan 2) Applicable CCD image sensor • ICX282 VD 295 1 17 47 295 1 17 47 HD SUB C V1A High-speed sweep block E K Frame shift block C High-speed sweep block E K Frame shift block V1B V1C V2 V3A 737 738 741 737 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 2 2 738 – 30 – V3B V3C V4 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 295H (2894ck) period. Chart-9 Vertical Direction Timing Chart MODE Draft mode (AF1) Applicable CCD image sensor • ICX282 VD 125 1 9 19 125 1 9 19 HD SUB High-speed sweep block High-speed sweep block M V1A J L Frame shift block M J L Frame shift block V1B V1C V2 V3A 561 565 570 574 577 581 561 565 570 574 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 6 2 6 2 577 581 – 31 – V3B V3C V4 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 125H (3022ck) period. 124H only has a 647ck period. Chart-10 Vertical Direction Timing Chart MODE Draft mode (AF2) Applicable CCD image sensor • ICX282 VD 63 1 13 27 63 1 13 HD SUB M V1A High-speed sweep block J L Frame shift block M High-speed sweep block J L Frame shift block V1B V1C V2 V3A 849 853 858 862 865 869 – 32 – V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN 6 2 6 2 CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 63H (3022ck) period. 62H only has a 324ck period. Chart-11 Horizontal Direction Timing Chart MODE Frame mode (including center scan 1 and 2) Progressive scan mode (including center scan 1 and 2) Applicable CCD image sensor • ICX282 (2894) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 270 298 310 314 H1A/B H2A/B 89 166 141 219 193 115 245 V1A/B/C V2 62 V3A/B/C V4 – 33 – 176 234 296 SUB 62 PBLK 24 52 44 32 60 60 272 296 OBCLP (1) 16 OBCLP (2) OBCLP (3) 16 OBCLP (4) CLPDM 115 ID/EXP 115 WEN ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1, 2, 5, 6, 7 and 8. CXD2498R Chart-12 Horizontal Direction Timing Chart MODE Double speed mode Applicable CCD image sensor • ICX282 (3102) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 478 506 518 522 H1A/B H2A/B 89 166 141 219 193 115 245 270 323 297 349 401 453 374 427 V1A/B/C V2 62 V3A/B/C V4 384 442 504 – 34 – SUB 62 PBLK 24 52 44 32 60 60 480 504 OBCLP (1) 16 OBCLP (2) OBCLP (3) 16 OBCLP (4) CLPDM 115 ID/EXP 115 WEN ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3. CXD2498R Chart-13 Horizontal Direction Timing Chart MODE Draft mode (including AF1 and 2) Applicable CCD image sensor • ICX282 (3022) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 398 426 438 442 H1A/B H2A/B 73 104 94 126 115 84 136 146 168 157 178 199 220 188 210 230 252 241 262 283 304 272 294 314 336 325 346 367 388 356 378 V1A/B/C V2 62 V3A/B/C V4 307 365 424 – 35 – SUB 62 PBLK 24 52 44 32 60 60 400 424 OBCLP (1) 16 OBCLP (2) OBCLP (3) 16 OBCLP (4) CLPDM 115 ID/EXP 115 WEN ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-4, 9 and 10. CXD2498R Chart-14 Horizontal Direction Timing Chart (High-speed sweep: C) MODE Frame mode (including center scan 1 and 2) Progressive scan mode (including center scan 1 and 2) Applicable CCD image sensor • ICX282 (2894) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 270 298 310 314 H1A/B H2A/B 62 114 88 140 166 192 218 244 270 296 322 348 374 400 426 452 478 504 530 556 V1A/B/C V2 62 114 88 140 166 192 218 244 270 296 322 348 374 400 426 452 478 504 530 556 V3A/B/C V4 #1 176 – 36 – ∗ ∗ ∗ ∗ ∗ ∗ #2 234 #3 #4 #5 SUB 62 PBLK 24 52 OBCLP CLPDM ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1, 2, 5, 6, 7 and 8. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 70H 2362ck (#1970) in the A Field of frame mode (including center scan 1 and 2), 47H 2884ck (#1335) in progressive scan mode, 10H 2842ck (#305) in progressive scan mode (center scan 1), and 16H 2846ck (#472) in progressive scan mode (center scan 2). CXD2498R Chart-15 Horizontal Direction Timing Chart (High-speed sweep: D) MODE Frame mode (including center scan 1 and 2) Applicable CCD image sensor • ICX282 (2894) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 270 298 310 314 H1A/B H2A/B 62 98 80 116 134 152 170 188 206 224 242 260 278 296 314 332 350 368 386 404 422 440 458 476 494 512 530 548 V1A/B/C V2 62 98 80 116 134 152 170 188 206 224 242 260 278 296 314 332 350 368 386 404 422 440 458 476 494 512 530 548 V3A/B/C – 37 – ∗ ∗ ∗ ∗ ∗ ∗ V4 #1 SUB 62 #2 176 234 #3 #4 #5 #6 #7 PBLK 24 52 OBCLP CLPDM ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. PBLK, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1, 5, and 6. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 24H 1670ck (#986) in the B Field of frame mode (including center scan 1 and 2). CXD2498R Chart-16 Horizontal Direction Timing Chart (High-speed sweep: H) MODE Double speed mode Applicable CCD image sensor • ICX282 (3102) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 478 506 518 522 H1A/B H2A/B 62 114 88 140 166 192 218 244 270 296 322 348 374 400 426 452 478 504 530 556 V1A/B/C V2 62 114 88 140 166 192 218 244 270 296 322 348 374 400 426 452 478 504 530 556 V3A/B/C – 38 – ∗ ∗ ∗ ∗ ∗ V4 #1 SUB PBLK OBCLP CLPDM ID/EXP WEN #2 #3 384 #4 442 #5 The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 66H 314ck (#1970). CXD2498R Chart-17 Horizontal Direction Timing Chart (High-speed sweep: I) MODE Double speed mode Applicable CCD image sensor • ICX282 (3102) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 478 506 518 522 H1A/B H2A/B 62 98 80 116 134 152 170 188 206 224 242 260 278 296 314 332 350 368 386 404 422 440 458 476 494 512 530 548 V1A/B/C V2 62 98 80 116 134 152 170 188 206 224 242 260 278 296 314 332 350 368 386 404 422 440 458 476 494 512 530 548 V3A/B/C V4 – 39 – SUB 62 #1 #2 #3 #4 #5 384 442 #6 #7 PBLK 24 52 OBCLP CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 22H 2810ck (#986). CXD2498R Chart-18 Horizontal Direction Timing Chart (High-speed sweep: M) MODE Draft mode (AF1 and 2) Applicable CCD image sensor • ICX282 (3022) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 398 426 438 442 H1A/B H2A/B 73 104 94 126 115 146 157 178 199 188 210 230 241 262 283 272 294 314 325 346 367 356 378 398 409 430 451 440 462 482 493 514 535 524 546 V1A/B/C V2 62 V3A/B/C 84 136 168 220 252 304 336 388 420 472 504 556 – 40 – ∗ ∗ ∗ ∗ ∗ V4 #1 SUB PBLK OBCLP CLPDM ID/EXP WEN #2 #3 307 #4 365 #5 #6 The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 7H 2848ck (#285) in draft mode (AF1), 11H 2184ck (#421) in draft mode (AF2). CXD2498R Chart-19 Horizontal Direction Timing Chart (Frame shift : K) MODE Frame mode (including center scan 1 and 2) Progressive scan mode (including center scan 1 and 2) Applicable CCD image sensor • ICX282 (2894) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 270 298 310 314 H1A/B H2A/B 89 166 141 219 297 349 374 427 505 557 V1A/B/C V2 62 193 115 245 270 323 401 453 478 531 V3A/B/C – 41 – ∗ ∗ ∗ ∗ ∗ V4 #1 176 234 #2 #3 SUB PBLK OBCLP CLPDM ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. Frame shift of V1A/B/C, V2, V3A/B/C and V4 is performed up to 90H 2864ck (#250) in the A Field of frame mode (center scan 1), 44H 2864ck (#250) in the B Field, 99H 1570ck (#369) in the A Field of frame mode (center scan 2), 53H 1570ck (#369) in the B Field, 32H 2864ck (#250) in progressive scan mode (center scan 1), and 46H 1646ck (#369) in progressive scan mode (center scan 2). CXD2498R Chart-20 Horizontal Direction Timing Chart (Frame shift: L) MODE Draft mode (AF1 and 2) Applicable CCD image sensor • ICX282 (3022) 0 50 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 398 426 438 442 H1A/B H2A/B 73 104 94 126 115 146 157 178 199 188 210 230 241 262 283 272 294 314 325 346 367 356 378 398 409 430 451 440 462 482 493 514 535 524 546 V1A/B/C V2 62 V3A/B/C 84 136 168 220 252 304 336 388 420 472 504 556 – 42 – ∗ ∗ ∗ ∗ ∗ V4 #1 SUB PBLK OBCLP CLPDM ID/EXP WEN #2 #3 307 #4 365 #5 #6 The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. Frame shift of V1A/B/C, V2, V3A/B/C and V4 is performed up to 18H 2092ck (#276) in draft mode (AF1), 22H 2100ck (#420) in draft mode (AF2). CXD2498R Chart-21 Horizontal Direction Timing Chart MODE Frame mode (including center scan 1 and 2) Applicable CCD image sensor • ICX282 1380 1410 1440 1470 1530 1560 1590 1620 1650 1680 (2894) 0 1710 (2894) 0 115 141 166 193 219 245 270 297 323 115 141 166 193 219 HD [A Field] V1A V1B V1C V2 V3A V3B V3C V4 [B Field] V1A V1B V1C V2 V3A V3B V3C V4 Logic alignment portion B A 245 62 89 62 89 – 43 – CXD2498R ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. Chart-22 Horizontal Direction Timing Chart MODE Progressive scan mode (including center scan 1 and 2) Applicable CCD image sensor • ICX282 1380 1410 1440 1470 1500 1530 1560 1590 1620 1650 1680 (2894) 0 1710 (2894) 0 115 141 166 193 219 245 270 297 323 115 141 166 193 219 HD E V1A V1B V1C V2 V3A V3B V3C V4 ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. 245 62 89 62 89 – 44 – CXD2498R Chart-23 Horizontal Direction Timing Chart MODE Double speed mode Applicable CCD image sensor • ICX282 1380 1410 1440 1470 1530 1560 1590 1620 1650 1680 (3102) 0 1710 (3102) 0 62 89 115 141 166 193 219 245 270 297 323 349 374 401 427 453 478 505 531 HD [A Field] V1A V1B V1C V2 V3A V3B V3C F V4 [B Field] V1A V1B V1C V2 V3A V3B V3C V4 Logic alignment portion G 62 89 115 141 166 193 219 245 270 297 323 349 374 – 45 – CXD2498R ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. Chart-24 Horizontal Direction Timing Chart MODE Draft mode (including AF1 and 2) Applicable CCD image sensor • ICX282 1290 1320 1350 1380 1410 1440 1470 1500 1530 1560 (3022) 0 1590 (3022) 0 62 73 84 94 104 115 126 136 146 157 168 178 188 199 210 220 230 241 252 262 272 283 294 304 314 325 336 346 356 367 378 388 HD J V1A V1B V1C V2 V3A V3B V3C V4 ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. 62 73 84 94 104 115 126 136 146 157 168 178 188 199 210 220 230 241 252 262 272 283 294 304 314 – 46 – CXD2498R Chart-25 High-Speed Phase Timing Chart MODE Applicable CCD image sensor • ICX282 HD HD' CKI CKO ADCLK 1 62 270/398/478 MCKO – 47 – H1A/B H2A/B RG XSHP XSHD ∗ HD’ indicates the HD which is the actual CXD2498R load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. CXD2498R Chart-A1 Vertical Direction Sequence Chart MODE Draft → Frame (or double speed) → Draft Applicable CCD image sensor • ICX282 VD V1A V1B V1C V2 V3A – 48 – V3B V3C V4 SUB Mechanical shutter Exposure time CCD OUT MODE 0 A A 0 B B 0 C C 0 0 3 D E E 3 E 0 Close Open F F 0 ∗ ∗ ∗ ∗ CXD2498R This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD2498R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data are not the same. Chart-A2 Vertical Direction Sequence Chart MODE Draft → Progressive scan → Draft Applicable CCD image sensor • ICX282 VD V1A V1B V1C V2 V3A – 49 – V3B V3C V4 SUB Mechanical shutter Exposure time CCD OUT MODE 0 A A 0 B B 0 C C 0 0 1 D E E 0 Close Open F F 0 G G 0 H H 0 ∗ ∗ ∗ ∗ CXD2498R This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD2498R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data are not the same. CXD2498R Application Circuit Block diagram CCD ICX282 CCD OUT Digital OUT CDS/ADC Block CLPDM OBCLP 18 19 20 21 22 23 H1A H1B H2A H2B RG V1A V1B V1C V2 V3A V3B V3C V4 SUB 10 12 13 15 8 40 42 43 38 44 46 47 39 48 26 CKI ADCLK XSHD XSHP PBLK 4 5 25 30 TG CXD2498R V-Dr 2 3 6 34 SSG 35 ID/EXP WEN CKO MCKO VD HD RST SNCSL SSGSL Signal Processor Block 27 28 VCO TEST1 TEST2 31 32 33 SSI SCK SEN Controller Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes for Power-on Of the three –7.5V, +15.0V, +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential. 15.0V t1 20% 0V 20% t2 t2 ≥ t1 –7.5V – 50 – CXD2498R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 12 13 B (0.22) + 0.05 0.127 – 0.02 0.13 M 0.1 0.1 ± 0.1 0.5 ± 0.2 S 0.18 ± 0.03 0˚ to 10˚ 0.5 ± 0.2 DETAIL B:PALLADIUM DETAIL A NOTE: Dimension “ ∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g 0.127 ± 0.04 – 51 – Sony Corporation