CXD2589Q

CXD2589Q CD Digital Signal Processor Description The CXD2589Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters, zero detection circuit, 1-bit DAC, and analog low-pass filter on a single chip. Features Digital Signal Processor (DSP) Block • Playback mode supporting CAV (Constant Angular Velocity) – Frame jitter-free – Allows 0.5 to double-speed continuous playback – Allows relative rotational velocity readout – Supports external spindle control • Wide capture range playback mode – Spindle rotational velocity following method – Supports normal-speed and double-speed playback • 16K RAM • EFM data demodulation • Enhanced EFM frame sync protection • SEC strategy-based error correction • Subcode demodulation and Sub Q data error detection • Digital spindle servo • 16-bit traverse counter • Asymmetry compensation circuit • Serial bus-based CPU interface • Error correction monitor signals, etc. are output from a new CPU interface. • Servo auto sequencer • Digital audio interface output • Digital peak meter Digital Filter, DAC, Analog Low-Pass Filter Block • DBB (Digital Bass Boost) • Supports double-speed playback • Digital de-emphasis • Digital attenuation function • Zero detection function • 8Fs oversampling digital filter • S/N: 100dB or more (master clock: 384Fs typ.) Logical value: 109dB • THD + N: 0.007% or less (master clock: 384Fs typ.) • Rejection band attenuation: –60dB or less Applications CD players Structure Silicon gate CMOS IC 80 pin QFP (Plastic) Absolute Maximum Ratings –0.3 to +7.0 V • Supply voltage VDD • Input voltage VI –0.3 to +7.0 V (Vss – 0.3V to VDD + 0.3V) • Output voltage VO –0.3 to +7.0 V • Storage temperature Tstg –40 to +125 °C • Supply voltage difference VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V Note) AVDD includes XVDD, and AVSS includes XVSS. Recommended Operating Conditions • Supply voltage VDD 3.4 to 5.25 V • Operating temperature Topr –20 to +75 °C Note) The VDD (min.) for the CXD2589Q varies according to the playback speed selection. VDD (min.) [V] Playback speed 2× 1× 1×∗1 CD-DSP block VCO high VCO normal speed speed 3.4 3.4 3.4 3.5 3.5 4.5 3.4 DAC block ∗1 When the internal operation of the CD-DSP side is set to double-speed mode and the crystal oscillation frequency is halved, normal-speed playback results. Input/Output Capacitances • Input capacitance CI 12 (max.) • Output capacitance CO 12 (max.) Note) Measurement conditions VDD = VI = 0V fM = 1MHz pF pF Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96Y02A73 CXD2589Q Block Diagram EMPHI WFCK PCMD EMPH LRCKI PCMDI VPCO SYSM XUGF C2PO V16M VCTL LRCK XTSL VCKI GFS BCK 51 25 26 27 28 47 49 54 56 50 39 41 43 55 40 42 44 62 BCKI 24 TES1 23 TEST C4M 52 Clock Generator OSC Error Corrector EFM demodurator D/A Interface 79 XRST RF 35 ASYI 37 ASYO 38 BIAS 36 Asymmetry Corrector 3 Serial-In Interface Timing Logic 2 RMUT LMUT 70 XTAI 71 XTAO 16K RAM XPCK 48 FILO 30 FILI 31 PCO 29 CLTV 33 Digital PLL Sub Code Processor Digital OUT Over Sampling Digital Filter 3rd-Order Noise Shaper PWM PWM FOK 18 SEIN 10 CNIN 11 Servo Auto Sequencer CPU Interface Digital CLV 12 13 14 6 7 8 9 15 16 17 57 58 59 5 4 21 22 53 74 75 76 67 66 65 SCOR DOUT LOUT2 SENS XLON AOUT2 SQCK CLKO SQSO SPOB MDP AIN2 LOUT1 SPOA CLOK XLTO EXCK –2– AOUT1 XLAT DATO SBSO PWMI DATA AIN1 CXD2589Q Pin Configuration EMPHI PCMDI WFCK EMPH DOUT EXCK XPCK XUGF GFS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD 61 SYSM 62 AVss 63 AVDD 64 AOUT1 65 AIN1 66 LOUT1 67 AVss 68 XVDD 69 XTAI 70 XTAO 71 XVss 72 AVss 73 LOUT2 74 AIN2 75 AOUT2 76 AVDD 77 AVss 78 XRST 79 VDD 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 LRCKI 39 LRCK 38 ASYO 37 ASYI 36 BIAS 35 RF 34 AVDD 33 CLTV 32 AVss 31 FILI 30 FILO 29 PCO 28 VCTL 27 V16M 26 VCKI 25 VPCO 24 TES1 23 TEST 22 PWMI 21 MDP SQSO SQCK RMUT SPOA SPOB CLOK XLON CNIN SEIN BCK Vss LMUT CLKO XLAT DATA XLTO –3– DATO SENS FOK VDD Vss Vss PCMD SBSO SCOR XTSL C2PO C4M VDD Vss BCKI CXD2589Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol VSS LMUT RMUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA SPOB XLON FOK VDD VSS MDP PWMI TEST TES1 VPCO VCKI V16M VCTL PCO FILO FILI AVSS CLTV AVDD RF — O O I O O I I I I I O O O I I O I — — O I I I O I O I O O I — I — I — — 1, 0 — — 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 I/O — 1, 0 1, 0 GND Left-channel zero detection flag. Right-channel zero detection flag. SQSO readout clock input. Sub Q 80-bit serial output. SENS output to CPU. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Microcomputer extended interface (input A). Microcomputer extended interface (input B). Microcomputer extended interface (output). Focus OK input. Used for SENS output and the servo auto sequencer. Power supply (+5V). GND Description 1, Z, 0 Spindle motor servo control. Spindle motor external control input. TEST pin; normally GND. TEST pin; normally GND. 1, Z, 0 Charge pump output for the wide-band EFM PLL. VCO2 oscillation input for the wide-band EFM PLL. VCO2 oscillation output for the wide-band EFM PLL. VCO2 control voltage input for the wide-band EFM PLL. 1, Z, 0 Master PLL charge pump output. Analog Master PLL (slave = digital PLL) filter output. Master PLL filter input. Analog GND. Master VCO control voltage input. Analog power supply (+5V). EFM signal input. –4– CXD2589Q Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Symbol BIAS ASYI ASYO LRCK LRCKI PCMD PCMDI BCK BCKI VSS VDD XUGF XPCK GFS C2PO XTSL C4M DOUT EMPH EMPHI WFCK SCOR SBSO EXCK VSS VDD SYSM AVSS AVDD AOUT1 AIN1 LOUT1 AVSS XVDD XTAI XTAO I O I I O O I O I O I — — O O O O I O O O I O O O I — — I — — O I O — I/O Description Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. 1, 0 1, 0 EFM full-swing output (low = VSS, high = VDD). D/A interface. LR clock output f = Fs. LR clock input. 1, 0 D/A interface. Serial data output (two's complement, MSB first). D/A interface. Serial data input (two's complement, MSB first). 1, 0 D/A interface. Bit clock output. D/A interface. Bit clock input. — — 1, 0 1, 0 1, 0 1, 0 GND Power supply (+5V). XUGF output. Switched to MNT1 or RFCK output by a command. XPLCK output. Switched to MNT0 output by a command. GFS output. Switched to MNT3 or XRAOF output by a command. C2PO output. Switched to GTOP output by a command. Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz. 1, 0 1, 0 1, 0 4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode. Digital Out output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off. 1, 0 1, 0 1, 0 WFCK output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. — — GND Power supply (+5V). Mute input. Active when high. — — Analog GND. Analog power supply (+5V). Left-channel analog output. Left-channel operational amplifier input. Left-channel LINE output. — Analog GND. Power supply for master clock. Crystal oscillation circuit input. Input the external master clock via this pin. Crystal oscillation circuit output. –5– CXD2589Q Pin No. 72 73 74 75 76 77 78 79 80 Symbol XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS XRST VDD — O I O — — I — I/O GND for master clock. — Analog GND. Right-channel LINE output. Description Right-channel operational amplifier input. Right-channel analog output. — — Analog power supply (+5V). Analog GND. System reset. Reset when low. — Power supply (+5V). Notes) • PCMD is an MSB first, two's complement output. • GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) • XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before sync protection. • XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide. • GFS goes high when the frame sync and the insertion protection timing match. • RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed). • C2PO represents the data error status. • XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin. –6– CXD2589Q Electrical Characteristics DC Characteristics Item (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) ∗ Conditions Min. 0.7VDD 0.3VDD 0.8VDD 0.2VDD Vss VDD – 0.5 0 VDD – 0.5 0 VDD VDD 0.4 VDD 0.4 VDD 0.4 5 5 Typ. Max. Unit V V V V V V V V V V V µA µA ∗1, ∗2, ∗3 ∗7 ∗6 ∗5 ∗3 ∗4 ∗2 Applicable pins ∗1 Input voltage High level input voltage VIH (1) (1) Low level input voltage VIL (1) Input voltage High level input voltage VIH (2) Schmitt input (2) Low level input voltage VIL (2) Input voltage Input voltage (3) Output voltage (1) Output voltage (2) Output voltage (4) VIN (3) Analog input High level output voltage VOH (1) IOH = –1mA Low level output voltage VOL (1) IOL = 1mA High level output voltage VOH (2) IOH = –1mA Low level output voltage VOL (2) IOL = 2mA High level output voltage VOH (4) IOH = –0.28mA VDD – 0.5 Low level output voltage VOL (4) IOL = 0.36mA ILI ILO VI = 0 to 5.50V VO = 0 to 5.50V 0 –5 –5 Input leak current Tri-state pin output leak current Applicable pins ∗1 XTSL, DATA, XLAT, PWMI, SYSM, EMPHI, PCMDI ∗2 CLOK, XRST, EXCK, SQCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, SPOA, SPOB ∗3 CLTV, FILI, RF, VCTL, AIN1, AIN2 ∗4 MDP, PCO, VPCO ∗5 ASYO, DOUT, C4M, SBSO, SQSO, SCOR, EMPH, DATO, CLKO, XLTO, SENS, WFCK, V16M, LMUT, RMUT, XLON, LRCK, PCMD, BCK, XUGF, XPCK, GFS, RFCK, C2PO ∗6 FILO ∗7 SENS, PCO, VPCO ∗note) : XVDD and XVSS are included for AVPP and AVSS, respectively. Those are the same for the explanation from the next page. –7– CXD2589Q AC Characteristics 1. XTAI pin (1) When using self-excited oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Min. 15 Typ. Max. 34 Unit MHz Oscillation frequency fMAX (2) When inputting pulses to XTAI pin (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item High level pulse width Symbol Min. 13 13 26 VDD – 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns tWHX Low level pulse width tWLX Pulse cycle Input high level Input low level Rise time, fall time tCK VIHX VILX tR, tF tCK tWHX tWLX VIHX VIHX × 0.9 XTAI VDD/2 VIHX × 0.1 VILX tR tF (3) When inputting sine waves to XTAI pin via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Input amplitude Symbol V1 Min. 2.0 Typ. Max. Unit VDD + 0.3 Vp-p –8– CXD2589Q 2. CLOK, DATA, XLAT, CNIN, SQCK and EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65∗ 750∗ 1/fCK tWCK tWCK CLK Unit MHz ns ns ns ns ns MHz ns tWCK tSU tH tD tWL fT fWT DATA XLT tSU EXCK CNIN SQCK tH tD tWL tWT 1/fT tWT SQSO SBSO tSU tH ∗ In pseudo double-speed playback mode, except when SQSO is Sub Q Read, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs. 3. BCKI, LRCKI and PCMDI pins Item BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Min. 94 18 18 18 tW(BCKI) tW(BCKI) VDD/2 tSU tH (PCMDI) (PCMDI) VDD/2 Symbol Conditions Typ. Max. Unit ns ns ns ns tW tSU tH tSU BCKI PCMDI tSU (LRCKI) LRCKI –9– CXD2589Q 1-bit DAC, LPF Block Analog Characteristics Analog Characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C) Item Total harmonic distortion S/N ratio Symbol THD Conditions 1kHz, 0dB data 1kHz, 0dB data (using A-weighting filter) Crystal 384Fs 768Fs S/N 384Fs 768Fs 96 96 Min. Typ. 0.0050 0.0045 100 100 Max. 0.0070 0.0065 dB Unit % For both items, Fs = 44.1kHz. The total harmonic distortion and S/N ratio measurement circuits are shown below. 12k AOUT1 (2) 680p 12k AIN1 (2) 150p LOUT1 (2) 22µ 100k Audio Analyzer 12k SHIBASOKU (AM51A) LPF External Circuit Diagram 768Fs/384Fs Rch DATA TEST DISC RF CXD2589Q Lch A Audio Analyzer B Block Diagram for Measuring Analog Characteristics – 10 – CXD2589Q (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = – 20 to +75°C) Item Output voltage Load resistance Symbol VOUT RL 8 Min. Typ. 1.12∗ Max. Unit Vrms kΩ Applicable pins ∗1 ∗1 ∗ Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is output. Applicable pins ∗1 LOUT1, LOUT2 – 11 – CXD2589Q Description of Functions 1. CPU Interface and Commands • CPU Interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D1 D2 D3 D0 D1 D2 D3 750ns or more Data XLAT Address Registers 4 to E Valid 300ns max • Information on each address and the data is provided in Table 1-1. • The internal registers are initialized by a reset when XRST is low; the initialization data is shown in Table 1-2. Note) When XLAT is low, SQCK must be set high. – 12 – Command Table Data 1 Data 2 Data 3 Data 4 Data 5 D0 D2 — — — — — — D1 D0 — — D3 D3 D2 D1 D0 — D0 D1 — — — — D3 D2 D0 D1 — — — — D3 D2 D0 — — — D3 D2 D1 D2 D1 Data 6 Address Command Register name D3 D2 D1 D0 D3 4 Auto sequence 0 1 0 0 AS3 AS2 AS1 AS0 5 — — — Blind (A, E), Overflow (C) Brake (B) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0 1 0 1 0.18ms 0.09ms 0.05ms 0.02ms — — — 0.36ms 0.18ms 0.09ms 0.05ms — — — 6 Kick (D) 0 1 1 0 11.6ms 5.8ms 2.9ms 1.45ms 7 256 16 Auto sequence (N) track jump count 128 64 32 2 1 8 4 — — VCO DOUT DOUT WSEL SEL1 Mute ON/OFF 0 SOCT 1 0 VCO KSL3 KSL2 KSL1 KSL0 SEL2 0 0 — SYCOF 0 OPSL1 MCSL 0 0 — ZDPL ZMUT OPSL1 MCSL 1 0 0 ZDPL ZMUT 0 0 0 — — DSPB ON/OFF 0 0 0 0 0 DSPB ON/OFF 0 0 0 0 SYCOF 0 0 Mute ATT 0 0 OPSL2 EMPH SMUT 0 OPSL2 EMPH SMUT 1 0 0 0 0 0 — 0 1 1 1 32768 16384 8192 4096 2048 1024 512 — — — — — — 8 MODE specification 1 0 0 0 CDROM — — — — — — 1 0 0 1 0 — — — — — — — 9 Function specification – 13 – 0 Mute ATT 0 0 SL0 CPUSR 0 TRMI TRMO MTSL1 MTSL0 — — — — — — — — — — — — — — TB TP Gain VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 CLVS — — — Gain Gain CAV1 CAV0 0 1 0 0 1 0 0 DCOF 0 0 — — — — 1 0 1 0 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — A Audio CTRL AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL 1 0 1 0 0 B Serial bus CTRL 1 0 1 1 SL1 — — — — — — — — — C Servo coefficient setting 1 1 0 0 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 — — — — — — — — — D CLV CTRL 1 1 0 1 0 — — — — — — — — — E CLV mode 1 1 1 0 CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON 0 — — — — — — — — CXD2589Q Table 1-1 Reset Initialization Data 1 Data 2 Data 3 Data 4 Data 5 D0 D2 — — — — — — D1 D0 — — D3 D3 D2 D1 D0 — D0 D2 — — D1 — — D3 D0 D2 — — D1 — — D3 D0 D1 — 0 — — D3 D2 D2 D1 0 0 Data 6 Address Command Register name D3 D2 D1 D0 D3 4 Auto sequence 0 1 0 0 0 5 0 — — — — — — — — — — — — — — — — 1 — Blind (A, E), Overflow (C) Brake (B) 1 1 1 — — — — — — — — — — — — — — 1 — — — 0 1 0 1 0 — — — 6 Kick (D) 0 1 1 0 0 — — — 7 0 0 0 — — 0 0 0 0 0 0 1 0 0 0 0 Auto sequence (N) track jump count setting 0 0 0 0 0 — 1 0 0 1 0 0 0 0 0 0 0 — 0 1 1 1 0 — — — — — — 8 MODE specification 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 — — — — — — 9 Function specification 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 — — — — – 14 – 0 1 1 0 0 — 0 0 0 0 0 0 — — 1 1 — — — — — — 0 — — — — — 0 0 1 0 1 0 0 0 1 0 0 — — — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A Audio CTRL 1 0 1 0 0 0 0 0 0 0 0 0 0 B Serial bus CTRL 1 0 1 1 0 — — — — — — — — — C Servo coefficient setting 1 1 0 0 0 — — — — — — — — — D CLV CTRL 1 1 0 1 0 — — — — — — — — — E CLV mode 1 1 1 0 0 0 — — — — — — — — Table 1-2 CXD2589Q CXD2589Q 1-1. The meaning of the data for each address is explained below. $4X commands Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 AS0 0 1 RXF RXF RXF RXF RXF = 0 FORWARD RXF = 1 REVERSE • When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. • When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Setting timers: A, E, C, B Command Blind (A, E), Over flow (C) Brake (B) D3 0.18ms 0.36ms D2 0.09ms 0.18ms D1 0.05ms 0.09ms D0 0.02ms 0.05ms Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Setting timer: D Command KICK (D) D3 11.6ms D2 5.8ms D1 2.9ms D0 1.45ms Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset) D = 10.15ms $7X commands Auto sequence track jump/move count setting (N) Data 1 Command Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 29 28 27 26 25 24 23 22 21 20 Auto sequence track jump 15 14 13 12 11 10 2 2 2 2 2 2 count setting This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence. • The maximum track count is 65,535, but note that with 2N-track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. • The number of tracks jumped is counted according to the signals input from the CNIN pin. – 15 – CXD2589Q $8X commands Data 1 Command D3 D2 D1 D0 D3 Data 2 D2 0 D1 SOCT D0 VCO SEL2 D3 KSL3 Data 3 D2 KSL2 D1 KSL1 D0 KSL0 DOUT DOUT VCO MODE CDROM WSEL Mute ON/OFF SEL1 specification See the $BX commands. Data 4 D3 0 D2 0 D1 1 D0 0 Command bit CDROM = 1 CDROM = 0 C2PO timing See Timing Chart 1-1. See Timing Chart 1-1. Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted. Command bit DOUT ON/OFF = 1 DOUT ON/OFF = 0 Processing Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin. Command bit WSEL = 1 WSEL = 0 Sync protection window width ±26 channel clock∗1 ±6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. ∗1 In normal-speed playback, channel clock = 4.3218MHz. – 16 – CXD2589Q Command bit VCOSEL1 0 0 0 0 1 1 1 1 KSL3 0 0 1 1 0 0 1 1 KSL2 0 1 0 1 0 1 0 1 Processing Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8 frequency-divided. ∗1 Approximately twice the normal speed. Command bit VCOSEL2 0 0 0 0 1 1 1 1 KSL1 0 0 1 1 0 0 1 1 KSL0 0 1 0 1 0 1 0 1 Processing Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided. Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/8 frequency-divided. ∗2 Approximately twice the normal speed. – 17 – Timing Chart 1-1 LRCK CDROM = 0 Rch 16bit C2 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG – 18 – C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer C2PO CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits CXD2589Q CXD2589Q $9X commands (OPSL1= 0) Data 1 Command Function specification D3 0 D2 DSPB ON/OFF D1 0 ∗ Data 2 D0 and subsequent data are DF/DAC function settings. Data 2 D0 D3 to D1 D0 0 000 SYCOF D3 0 Data 3 D2 MCSL D1 0 D0 0 D3 Data 4 D2 D1 — D0 — ZDPL ZMUT OPSL1 D3 — Data 5 D2 — D1 — D0 — $9X commands (OPSL1= 1) Command Function specification Data 1 D3 0 D2 DSPB ON/OFF D1 0 ∗ Data 2 D0 and subsequent data are DF/DAC function settings. Data 2 D0 D3 to D1 D0 0 000 SYCOF D3 1 Data 3 D2 MCSL D1 0 D0 0 D3 Data 4 D2 D1 0 D0 0 ZDPL ZMUT OPSL1 D3 0 Data 5 D2 DCOF D1 0 D0 0 Command bit DSPB = 1 DSPB = 0 Processing Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block) Command bit SYCOF = 1 SYCOF = 0 LRCK asynchronous mode Normal operation Processing ∗ Set SYCOF = 0 in advance when setting the $AX command LRWO to 1. Command bit OPSL1 = 1 OPSL1 = 0 DCOF can be set. DCOF cannot be set. Processing Command bit MCSL = 1 MCSL = 0 Processing DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz) – 19 – CXD2589Q Command bit ZDPL = 1 ZDPL = 0 Processing LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted. ∗ See "Mute flag output" for the mute flag output conditions. Command bit ZMUT = 1 ZMUT = 0 Zero detection mute is on. Zero detection mute is off. Processing Command bit DCOF = 1 DCOF = 0 DC offset is off. DC offset is on. Processing ∗ DCOF can be set when OPSL1 = 1. ∗ Set DC offset to off when zero detection mute is on. $AX commands (OPSL2 = 0) Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 0 ∗ Data 2 and subsequent data are DF/DAC function settings. Data 2 D2 0 D1 0 D0 Data 3 D3 D2 0 EMPH SMUT OPSL2 Data 3 D1 AD9 D0 AD8 D3 AD7 Data 4 D2 AD6 D1 AD5 D0 AD4 D3 AD3 Data 5 D2 AD2 D1 AD1 D0 AD0 D3 — Data 6 D2 — D1 — D0 — $AX commands (OPSL2 = 1) Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 0 ∗ Data 2 and subsequent data are DF/DAC function settings. Data 2 D2 0 D1 1 D0 Data 3 D3 D2 0 EMPH SMUT OPSL2 Data 3 D1 AD9 D0 AD8 D3 AD7 Data 4 D2 AD6 D1 AD5 D0 AD4 D3 AD3 Data 5 D2 AD2 D1 AD1 D0 D3 Data 6 D2 D1 D0 AD0 FMUT LRWO BSBST BBSL – 20 – CXD2589Q Command bit Mute = 1 Mute = 0 Processing CD-DSP block mute is on. 0 data is output from the CD-DSP block. CD-DSP block mute is off. Command bit ATT = 1 ATT = 0 Processing CD-DSP block output is attenuated (–12dB). CD-DSP block attenuation is off. Command bit OPSL2 = 1 OPSL2 = 0 Meaning FMUT, LRWO, BSBST and BBSL can be set. FMUT, LRWO, BSBST and BBSL cannot be set. Command bit EMPH = 1 EMPH = 0 De-emphasis is on. De-emphasis is off. Processing ∗ If either the EMPHI pin or EMPH is high, de-emphasis is on. Command bit SMUT = 1 SMUT = 0 Soft mute is on. Soft mute is off. Processing ∗ If either the SMUT pin or SMUT is high, soft mute is on. Command bit AD9 to 0 Attenuation data. Meaning The attenuation data consists of 10 bits, and is set as follows. Attenuation data 3FFh 3FEh 3FDh : 001h 000h Audio output 0dB –0.0085dB –0.017dB –60.198dB –∞ The attenuation data (AD9 to AD0) consists of 10bits, and can be set in 1023 different ways. The audio output from 001h to 3FFh is obtained using the following equation. Audio output = 20 log Attenuation data 1024 [dB] – 21 – CXD2589Q Command bit FMUT = 1 FMUT = 0 Forced mute is on. Forced mute is off. Meaning ∗ FMUT can be set when OPSL2 = 1. Command bit LRWO = 1 LRWO = 0 Forced synchronization mode Note) Normal operation. Meaning ∗ LRWO can be set when OPSL2 = 1. Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1. Command bit BSBST = 1 BSBST = 0 Bass boost is on. Bass boost is off. Processing ∗ BSBST can be set when OPSL2 = 1. Command bit BBSL = 1 BBSL = 0 Bass boost is Max. Bass boost is Mid. Processing ∗ BBSL can be set when OPSL2 = 1. – 22 – $BX commands Data 2 D3 D0 TRM1 TRM0 MTSL1 MTSL0 D2 D1 Command Data 1 D3 D2 D1 D0 Serial bus CTRL SL1 SL0 CPUSR 0 SOCT SL1 SL0 mode 0 0 0 SubQ 0 0 1 Peak meter 0 1 0 SENS 0 1 1 D 1 0 0 SubQ 1 0 1 A The SQSO pin output can be switched to the various signals by setting the SOCT command of $8X and the SL1 and SL0 commands of $BX. Set SQCK to high at the falling edge of XLAT. Except for Sub Q and peak meter, the signals are loaded to the register when they are set at the falling edge of XLAT. Sub Q is loaded to the register with each SCOR, and Peak meter is loaded when a peak is detected. 1 1 0 B – 23 – PER5 PER6 PER7 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK VF3 VF4 VF5 VF6 VF7 ALOCK C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS PER4 PER5 PER6 PER7 0 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS SCOR GFS GTOP EMPH FOK LOCK RFCK XRAOF C1F1 C1F2 C2F1 C2F2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 1 1 1 C XLAT SQCK mode A PER0 PER1 PER2 PER3 PER4 EMPH ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 mode B VF0 VF1 VF2 LOCK EMPH mode C PER0 PER1 PER2 PER3 LOCK EMPH mode D SPOA SPOB 0 0 WFCK CXD2589Q Peak meter L0 L1 L2 CXD2589Q Signal PER0 to 7 FOK GFS LOCK EMPH ALOCK VF0 to 7 SPOA, B WFCK SCOR GTOP RFCK XRAOF L0 to L7, R0 to R7 Description RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.) VF0 = LSB, VF7 = MSB. SPOA and B pin inputs. Write frame clock output. High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output. Low when the built-in 16K RAM exceeds the ±4 frame jitter margin. Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak data. L0 and R0 are LSB. C1F1 0 1 1 C1F2 0 0 1 C1 correction status No Error Single Error Correction Irretrievable Error C2F1 0 1 1 C2F2 0 0 1 C2 correction status No Error Single Error Correction Irretrievable Error Command bit CPUSR = 1 CPUSR = 0 XLON pin is high. XLON pin is low. Processing – 24 – CXD2589Q Peak meter XLAT SQCK SQSO (Peak meter) L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is restarted 270µs to 400µs after SQCK input. The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak detection register. Peak detection can also be performed for previous value hold and average value interpolation data. Traverse monitor count value setting These bits are set when monitoring the traverse condition of the SENS output according to the CNIN frequency division. Command bit TRM1 0 0 1 1 TRM0 0 1 0 1 1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division Processing Monitor output switching The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Mode description Pin No. Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MNT1 RFCK XPCK MNT0 XPCK – 25 – GFS MNT3 XROF C2PO C2PO GTOP 47 48 49 50 CXD2589Q $CX commands Command Servo coefficient setting CLV CTRL ($DX) D3 Gain MDP1 D2 Gain MDP0 D1 Gain MDS1 D0 Gain MDS0 Gain CLVS • CLV mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS –12dB –6dB –6dB 0dB 0dB +6dB • CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP –6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS –6dB 0dB +6dB – 26 – CXD2589Q $DX commands Command CLV CTRL Data 1 D3 0 D2 TB D1 TP D0 Gain CLVS D3 VP7 Data 2 D2 VP6 D1 VP5 D0 VP4 D3 VP3 Data 3 D2 VP2 D1 VP1 D0 VP0 See the $CX commands. Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. The rotational velocity R of the spindle can be expressed with the following equation. Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) Description Playback at half (normal) speed to Playback at normal (double) speed R= 256 – n 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value Note) • Values in parentheses are for when DSPB is 1. • Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. • VP0 to 7 setting values are valid in CAV-W mode. 2 R – Relative velocity [multiple] 1.5 P DS B= 1 1 DSP 0.5 B=0 F0 VP0 to 7 setting value [HEX] E0 Fig. 1-1 – 27 – CXD2589Q $EX commands Data 1 Command CLV mode D3 CM3 D2 CM2 D1 CM1 D0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode.∗1 Description Spindle forward rotation mode.∗1 Spindle reverse rotation mode. Valid only when LPWR = 0, in any mode.∗1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA ∗1 See Timing Charts 1-2 to 1-6. Command bit EPWM SPDC 0 0 0 1 0 0 1 0 ICAP 0 0 1 1 SFSL 0 0 0 0 VC2C 0 1 0 0 HIFC 0 1 1 1 LPWR VPON 0 0 0 0 0 0 1 1 Mode CLV-N CLV-W CAV-W CAV-W Description Crystal reference CLV servo. Used for normal-speed playback in CLV-W mode.∗2 Spindle control with VP0 to 7. Spindle control with the external PWM. ∗2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. – 28 – CXD2589Q Command SPD mode Data 4 D3 D2 D1 0 D0 0 Gain Gain CAV1 CAV0 Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB –6dB –12dB –18dB • This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. Mode LPWR Command KICK Timing chart 1-2 (a) 1-2 (b) 1-2 (c) 1-3 (a) 1-3 (b) 1-3 (c) 1-4 (a) 1-4 (b) 1-4 (c) 1-5 (a) 1-5 (b) 1-5 (c) 1-6 (a) 1-6 (b) 1-6 (c) CLV-N 0 BRAKE STOP KICK 0 CLV-W 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 1 BRAKE STOP KICK BRAKE STOP Mode CLV-N CLV-W LPWR 0 0 1 0 1 Timing chart 1-7 1-8 1-9 1-10 (EPWM = 0) 1-11 (EPWM = 0) 1-12 (EPWM = 1) 1-13 (EPWM = 1) – 29 – CAV-W 0 1 CXD2589Q Timing Chart 1-2 CLV-N mode LPWR = 0 KICK H MDP Z (a) KICK MDP L (b) BRAKE Z MDP Z BRAKE STOP (c) STOP Timing Chart 1-3 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 KICK H Z (a) KICK Z MDP L (b) BRAKE MDP Z BRAKE STOP MDP (c) STOP Timing Chart 1-4 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 KICK H MDP Z (a) KICK MDP BRAKE STOP Z MDP Z (b) BRAKE (c) STOP Timing Chart 1-5 CAV-W mode LPWR = 0 KICK H MDP MDP L (b) BRAKE MDP BRAKE STOP Z (a) KICK (c) STOP Timing Chart 1-6 CAV-W mode LPWR = 1 KICK H BRAKE STOP MDP MDP Z (b) BRAKE MDP Z (c) STOP (a) KICK – 30 – CXD2589Q Timing Chart 1-7 CLV-N mode LPWR = 0 n · 236 (ns) n = 0 to 31 Acceleration MDP Z Deceleration 132kHz 7.6µs Timing Chart 1-8 CLV-W mode LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8µs Timing Chart 1-9 CLV-W mode LPWR = 1 Acceleration MDP Z 264kHz 3.8µs The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-10 CAV-W mode EPWM = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8µs Timing Chart 1-11 CAV-W mode EPWM = LPWR = 1 Acceleration MDP Z 264kHz 3.8µs The BRAKE pulse is masked when LPWR = 1. – 31 – CXD2589Q Timing Chart 1-12 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-13 CAV-W mode EPWM = LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. – 32 – CXD2589Q 1-2. Description of SENS Output The following signals are output from SENS, depending on the microcomputer serial register value (latching not required). Microcomputer serial register value (latching not required) $0X, 1X, 2X, 3X $4X $5X $6X $AX $EX SENS output SEIN XBUSY FOK SEIN GFS OV64 Meaning SEIN, a signal input to this LSI from the SSP, is output. Low while the auto sequencer is in operation, high when operation terminates. Outputs the signal input to the FOK pin. Normally, FOK (from RF) is input. High for "focus OK". SEIN, a signal input to this LSI from the SSP, is output. High when the regenerated frame sync is obtained with the correct timing. Low when the EFM signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. SENS pin is fixed to low. Calculates the number of tracks from the frequency division ratio set by $B.High when $C is latched; toggles each time CNIN is input the number of times set in register B. $7X, 8X, 9X, BX, DX, FX “L” $CX CNIN division Note that the SENS output can be read out from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0. (See the $BX commands.) 2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2589Q. Sub Q can be read out after checking the CRC of the 80bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) 2-2. 80-bit Sub Q Readout Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register. • First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. • 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80bits are loaded into the parallel/serial register. When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the CPU determines that new data (which passed the CRC check) has been loaded. • When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. • Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. • The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. • While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.) • The high and low intervals for SQCK should be between 750ns and 120µs. – 33 – CXD2589Q Timing Chart 2-1 Internal PLL clock 4.3218 ± ∆MHz WFCK SCOR EXCK 400ns max SBSO S0 · S1 Q R WFCK SCOR EXCK SBSO S0·S1 Q R S T U V W S0·S1 P1 QRST UVW P1 P2 P3 Same Same Sub Code P.Q.R.S.T.U.V.W Read Timing – 34 – Fig. 2-1. Block Diagram (AFRAM) (ASEC) (AMIN) ADDRS CTRL SUBQ SIN 80bit S/P Register ABCDEFGH 8 8 8 8 8 8 Order Inversion 8 8 8 HGFEDCBA 80bit P/S Register SO LD LD LD LD LD SUBQ LD CRCC Mono/Multi SHIFT LD LD SI – 35 – SHIFT SQCK CRCF SQSO Mix CXD2589Q Timing Chart 2-2 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK Order Inversion Determined by mode L 80 Clock CRCF2 SCOR SQSO CRCF1 SQCK Registere load forbidder – 36 – 750ns to 120µs 270µs to 400µs for SQCK = High ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Mono/multi (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD2589Q CXD2589Q Timing Chart 2-3 Measurement interval (approximately 3.8µs) Reference window (132.2kHz) Measurement pulse (VCKI/2) Measurement counter Load VF0 to 7 m The relative velocity R of the disc can be expressed with the following equation. R= m+1 32 (R: Relative velocity, m: Measurement results) VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). – 37 – CXD2589Q 3. Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control. The PLL capture range is ±150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to the VCKI pin.) While starting to rotate a disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. This is because the capture range for CLV-W mode is wider than the conventional lock range. Concretely, first send $E6650 to set CAV-W mode and kick the disc, then send $E60C0 to set CLV-W mode when ALOCK is high. Playback is normally performed in CLV-W mode. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit. 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low-speed to double-speed. (See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. These values match those of the 256-n for control with VP0 to 7. In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc (excluding DATO, CLKO and XLTO). Note) The capture range for this mode is theoretically up to the signal processing limit. – 38 – CXD2589Q CAV-W Rotational velocity CLVS Target velocity CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A0XXXXX CAV-W $E6650 (CLVA) NO ALOCK = H ? YES CLV-W $E60C0 (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart – 39 – CXD2589Q 4. Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit • The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2589Q has a built-in three-stage PLL. • The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. The output of this first-stage PLL is used as a reference for all clocks within the LSI. • The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL. • The third-stage PLL is a digital PLL that regenerates the actual channel clock. • A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. – 40 – CXD2589Q Block Diagram 4-1 CLV-W CAV-W Spindle rotation information X'tal OSC 1/2 1/32 Selector VPCO Phase comparator XTSL CLV-N 1/2 1/n CLV-W CAV-W /CLV-N Microcomputer control n = 1 to 256 (VP7 to 0) LPF VCOSEL2 1/K (KSL1, 0) VCTL VCO2 V16M 2/1 MUX VPON VCKI 1/M Phase comparator PCO 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL CXD2589Q VCOSEL1 – 41 – CXD2589Q 4-2. Frame Sync Protection • In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. • In the CXD2589Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. 4-3. Error Correction • In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. • The CXD2589Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. • The correction status can be monitored externally. See Table 4-1. • When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 1 1 1 MNT1 0 0 1 0 0 1 MNT0 0 1 1 0 1 1 Table 4-1. Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible – 42 – CXD2589Q Timing Chart 4-1 Normal-speed PB t = Dependent on error condition MNT3 C1 correction C2 correction MNT1 MNT0 Strobe Strobe 4-4. DA Interface • The CXD2589Q DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. – 43 – Timing Chart 4-2 48bit slot Normal-Speed Playback LRCK (44.1k) 6 7 8 9 10 11 12 24 1 2 3 4 5 BCK (2.12M) PCMD L14 L13 L12 L11 L10 L9 L8 L7 L6 R0 Lch MSB (15) L5 L4 L3 L2 L1 L0 RMSB – 44 – 24 Rch MSB L0 48bit slot Double-Speed Playback LRCK (88.2k) 1 2 BCK (4.23M) PCMD Lch MSB (15) R0 CXD2589Q CXD2589Q 4-5. Digital Out There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2589Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3) of the channel status. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 Bits 0 to 3...Sub Q control bits that matched twice with CRCOK Bit 29..........1 when VPON is 1 Table 4-2. 4-6. Servo Auto Sequencer This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jumps, and N-track move are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but can be sent to the CXD2589Q. Connect the CPU, RF and SSP as shown in Fig. 4-2. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). – 45 – CXD2589Q (a) Auto Focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts with focus search-up, and the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Connection diagram for using auto sequencer (example) RF FOK FOK DATA CXD2589Q C. out SSP SENS DATA CLK XLT CNIN SEIN DATO CLKO XLTO CLOK XLAT SENS Micro-computer Fig. 4-2. Auto focus Focus search up FOK = H NO YES (Checks whether FZC is continuously high for the period of time E set with register 5) FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 4-3-(a). Auto Focus Flow Chart – 46 – CXD2589Q $47latch XLT FOK SEIN (FZC) BUSY Command for SSP Blind E $03 $08 Fig. 4-3-(b). Auto Focus Timing Chart (b) Track Jump 1, 10, and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. • 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-4. Set blind A and brake B with register 5. • 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-5. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through CNIN, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. • 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-6. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. • N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 4-7. N can be set to 216 tracks. CNIN is used for counting the number of jumps. This N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. – 47 – CXD2589Q Track Track FWD kick sled servo OFF WAIT (Blind A) (REV kick for REV jump) CNIN = YES Track REV kick WAIT (Brake B) Track, sled servo ON NO (FWD kick for REV jump) END Fig. 4-4-(a). 1-Track Jump Flow Chart $48 (REV = $49) latch XLT CNIN BUSY Blind A Command for SSP $28 ($2C) $2C ($28) Brake B $25 Fig. 4-4-(b). 1-Track Jump Timing Chart – 48 – CXD2589Q 10 Track Track, sled FWD kick WAIT (Blind A) (Counts CNIN × 5) CNIN = 5 ? YES Track, REV kick NO C = Overflow ? YES Track, sled servo ON NO (Checks whether the CNIN cycle is longer than overflow C) END Fig. 4-5-(a). 10-Track Jump Flow Chart $4A (REV = $4B) latch XLT CNIN BUSY Blind A Command for SSP $2A ($2F) CNIN 5 count Overflow C $2E ($2B) $25 Fig. 4-5-(b). 10-Track Jump Timing Chart – 49 – CXD2589Q 2N Track Track, sled FWD kick WAIT (Blind A) CNIN = N YES Track REV kick NO C = Overflow YES Track servo ON NO WAIT (Kick D) Sled servo ON END Fig. 4-6-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) latch XLT CNIN BUSY Blind A Command for SSP $2A ($2F) CNIN N count $2E ($2B) Overflow $26 ($27) Kick D $25 Fig. 4-6-(b). 2N-Track Jump Timing Chart – 50 – CXD2589Q N Track move Track servo OFF Sled FWD kick WAIT (Blind A) CNIN = N YES Track, sled servo OFF NO END END Fig. 4-7-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLT CNIN BUSY Blind A Command for SSP $22 ($23) CNIN N count $20 Fig. 4-7-(b). N-Track Move Timing Chart – 51 – CXD2589Q 4-7. Digital CLV Fig. 4-8 shows the Block Diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the signal sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDP 1/2 MUX Gain MDS Over Sampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI LPWR Mode Select MDP CLVS U/D: MDS error: MDP error: PWMI: Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-8. Block Diagram – 52 – CXD2589Q 4-8. Asymmetry Compensation CXD2589Q ASYO R1 RF 35 R1 47 R2 R1 ASYI 46 R1 36 BIAS R1 2 = R2 5 Fig. 4-9. Example of Asymmetry Compensation Application Circuit – 53 – CXD2589Q 5. 1bit DAC Block 5-1. DAC Block Input Timing Timing Chart 5-1 shows the input timing for the DAC block. Audio data is not transferred from the CD signal processer block to the DAC block inside the CXD2589Q. This is to allow data to be sent to the DAC block via the audio DSP, etc. When data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI. In this case, EMPH, LRCK, BCK and PCMD can be connected directly with EMPHI, LRCKI, BCKI and PCMDI, respectively. 5-2. Description of DAC Block Functions Zero data detection When the condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued for approximately 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected by the ZDPL command of $9X. • When zero data is detected • When a high signal is input to the SYSM pin • When the SMUT command of $AX is set Attenuation operation Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point. 0dB 7F (H) A Y1 B Y3 C Y2 –∞ 00 (H) 23.2 [ms] – 54 – CXD2589Q DAC block mute operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met. • When attenuation data of "000" (high) is set • When the SMUT command of $AX is set to 1 • When a high signal is input to the SYSM input pin Soft mute off 0dB Soft mute on Soft mute off – ∞dB 23.2 [ms] 23.2 [ms] Forced mute Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low. ∗ When setting FMUT, set OPSL2 to 1. (See the $AX commands.) Zero detection mute Forced mute is applied when the $9X command ZMUT is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) – 55 – Timing Chart 5-1 Normal-Speed Playback LRCKI (44.1k) 6 7 8 9 10 11 12 1 2 3 4 5 24 BCKI (2.12M) PCMDI R0 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 Lch MSB (15) L4 L3 L2 L1 L0 RMSB – 56 – 24 Rch MSB L0 Double-Speed Playback LRCKI (88.2k) BCKI (4.23M) 1 2 PCMDI Lch MSB (15) R0 CXD2589Q Input Timing for DAC Block CXD2589Q LRCK Synchronization Synchronization is performed at the first falling edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases. • When the XTSL pin switches between high and low • When the DSPB command of $9X setting changes • When the MCSL command of $9X setting changes LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in this case as well. For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set LRWO to 0. ∗ When setting LRWO, set OPSL2 to 1. (See the $AX commands.) SYCOF When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1. Normally, the memory proof, etc., is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting SYCOF of address 9 to 1 ignores that the LRCKI input synchronization is lost, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the LRCKI input. ∗ Set SYCOF to 0 except when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI, respectively, and performing playback in CAV-W mode. ∗ Set SYCOF to 0 in advance when LRCK resynchronization is applied with LRWO=1. Digital Bass Boost Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 5-2 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 Normal DBB MID DBB MAX [dB] –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 –14.00 10 30 100 300 1k 3k 10k 30k Digital Bass Boost Frequency Response [Hz] Graph 5-2. – 57 – CXD2589Q 6. LPF Block The CXD2589Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD – AVSS)/2. The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc ≈ 40kHz. The external capacitors' values when fc = 30kHz and 50 kHz are noted below as a reference. The resistors' values do not change at this time. • When fc ≈ 30kHz: C1 = 200pF, C2 = 910pF • When fc ≈ 50kHz: C1 = 120pF, C2 = 560pF LPF Block Application Circuit AOUT1 (2) 12k C2 680p 12k AIN1 (2) Vc C1 150p 12k Analog out LOUT1 (2) Fig. 6-1. LPF External Circuit – 58 – CXD2589Q 7. Setting Method of the CXD2589Q Playback Speed (in CLV-N mode) (A) CD-DSP block The playback modes shown below can be selected by the combination of the crystal, XTSL pin and DSPB command of $9X. CD-DSP block playback speed X'tal 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 1 DSPB 0 1 0 1 1 CD-DSP block playback speed 1× 2× 1× 2× 1×∗1 Fs = 44.1kHz ∗1 Low power consumption mode. The CD-DSP processing speed is halved, allowing the power consumption to be decreased. (B) 1-bit DAC block The operating speed of the DAC block is determined by the crystal and the MCSL command of $9X regardless of the operating conditions of the CD-DSP block mentioned above. This allows the playback mode for the DAC block and CD-DSP block to be set independently. 1-bit DAC block playback speed X'tal 768Fs 768Fs 384Fs Fs = 44.1kHz MCSL 1 0 0 DAC block playback speed 1× 2× 1× – 59 – Application Circuit 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Vss GFS VDD Vss C4M XTSL EXCK C2PO SBSO XPCK SCOR DOUT XUGF BCKI BCK WFCK EMPHI EMPH 61 VDD 62 SYSM ASYO 38 ASYI 37 BIAS 36 RF 35 AVDD 34 CLTV 33 AVss 32 FILI 31 FILO 30 PCO 29 VCTL 28 V16M 27 VCKI 26 VPCO 25 TES1 24 TEST 23 PWMI 22 RF PCMDI LRCKI 40 LRCK 39 63 AVss 64 AVDD 65 AOUT1 66 AIN1 67 LOUT1 68 AVss 69 XVDD 70 XTAI 71 XTAO 72 XVss 73 AVss SENS DATO SQSO CNIN SQCK SEIN RMUT CLOK SPOA SPOB XLON LMUT XLAT CLKO Vss DATA XLTO 1 2 3 7 4 8 5 6 9 10 11 12 13 14 15 16 17 18 19 20 FOK VDD Vss FOK SENS XRST DATA XLAT CLK GFS SQSO SQCK SCOR MUTE VDD Vss – 60 – MDP 21 74 LOUT2 75 AIN2 76 AOUT2 77 AVDD 78 AVss 79 XRST PCMD 80 VDD DRIVER LS SSP CXD2589Q Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2589Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 0.1 41 40 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 61 80 1 0.65 20 21 + 0.15 0.1 – 0.1 ± 0.12 M 0° to 10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 LQFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g – 61 – 0.5 ± 0.2 + 0.15 0.3 – 0.1 (15.0)