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CXD2951GA-2

CXD2951GA-2

  • 厂商:

    SONY(索尼)

  • 封装:

  • 描述:

    CXD2951GA-2 - Single Chip GPS LSI - Sony Corporation

  • 数据手册
  • 价格&库存
CXD2951GA-2 数据手册
CXD2951GA-2 Single Chip GPS LSI Description The CXD2951GA-2 is a dedicated single chip LSI for the GPS (Global Positioning System), satellitebased location measurement system. This LSI enables the configuration of a single chip system providing a cost-effective, low-power solution. Compared with conventional methods, position detection time and sensitivity are substantially improved with the use of an advanced signal processing scheme. With the integration of both the Radio and baseband blocks into a single CMOS IC, the CXD2951GA-2 is ideal for use in automotive, cellular handset, handheld navigation, mobile computing and other location-based applications. Features • 12-channel GPS receiver capable of simultaneously receiving 12 satellites • Reception frequency: 1575.42MHz (L1 band, CA code) • Reference clock (TCXO) frequency: 18.414MHz (GPS, Sony standard), The unique frequency of major applications is available, such as GSM and W-CDMA. (optional) 13.000MHz (GSM), 14.400MHz (CDMA), 16.368MHz (GPS), 19.800MHz (PDC/CDMA), 26.000MHz (GSM) 176 pin LFLGA (Plastic) Radio • Image Rejection Mixer • VCO Tank • IF Filters Structure Silicon gate CMOS IC Absolute Maximum Ratings • Supply voltage I/O IOVDD • Supply voltage core CVDD • Supply voltage radio VDD • Input voltage VI • Output voltage VO • Operating temperature Topr • Storage temperature Tstg –0.5 to +4.6 –0.5 to +2.5 –0.5 to +2.5 –0.5 to +6 –0.5 to +6 –40 to +85 –50 to +150 V V V V V °C °C • 32 bits RISC CPU (ARM7TDMI) • 288K-bytes Program ROM • 72K-bytes Data RAM Power is supplied only to 8K-byte Data RAM while in backup mode. • System power management • 1-channel UART • Internal RTC (Real Time Clock) • 10-bit successive approximation system A/D converter, A/D data available on NMEA messages • All-in-view positioning • Communication format: Supports NMEA-0183 • 1 PPS output • Supports assisted-GPS for cellular (optional) Recommended Operating Conditions • Supply voltage I/O IOVDD 3.0 to 3.6 V ∗ Under operation with internal ROM, using no external expansion bus: IOVDD 2.6 to 3.6 V ∗ Under operation in backup mode: BKUPIOVDD 2.5 (Min.) V • Supply voltage core CVDD 1.62 to 1.98 V • Supply voltage radio VDD 1.62 to 1.98 V • Operating temperature Topr –40 to +85 °C Input/Output Pin Capacitance (Baseband) • Input capacitance CIN 9 (Max.) • Output capacitance COUT 11 (Max.) • I/O capacitance CI/O 11 (Max.) pF pF pF Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04445A49 CXD2951GA-2 Performance Baseband • Tracking sensitivity: –152dBm (average) or less • Acquisition sensitivity: –139dBm (average) or less in Normal mode –150dBm (average) or less in High sensitivity mode ∗ Reference data using the Sony's reference board when using both an antenna of 0dBi and a RF amplifier with NF ≤ 2dB, 25dB gain. • TTFF (Time to First Fix): Time until initial position measurement after power-on with the following conditions: Cold Start (without both ephemeris and almanac time): 50s (average) / 60s (95% possibility) Warm Start (without ephemeris but with almanac time): 35s (average) / 40s (95% possibility) Hot Start (with both ephemeris and almanac time): 2s (minimum) / 6s (95% possibility) ∗ Reference data with elevation angle of 5° or more and no interception environment with satellite powers ≥ –130dBm. (Not in High sensitivity mode) Note) "95% possibility" means "position time with 95% possibility". • Positioning accuracy: 2DRMS: approx. 5m ∗ Reference data with elevation angle of 5° or more and no interception environment with satellite powers ≥ –130dBm. • Measurement data update time: 1s • Power consumption: 50mW (average) while position calculating with tracking satellites in low power mode 120mW (average) while position calculating with acquiring and tracking satellites ∗ Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its amplitude is 3.3V swing. • 1PPS output 1µs or less precision, 1PPS outputs from ECLKOUT (Pin 97). Note) These values are not guaranteed, depending on the conditions. Radio • Total Gain (typ.): 100dB • Noise figure (typ.): 8dB • Synthesizer phase noise (typ.): –70dBc/Hz (10kHz) –80dBc/Hz (100kHz) • PLL spurious (typ.): –45dBc (inside fosc ±1.023MHz) –55dBc (outside fosc ±1.023MHz) Note) These values are not guaranteed. –2– CXD2951GA-2 System Block Diagram 1575.42MHz TCXO LNA CPU Freq. Synthesizer RF/IF 1575.42MHz → 1.023MHz BPF SAW TCXO Reference clock 18.414MHz (GPS, Sony standard) LNA Down Converter 1.023MHz LPF 1 bit Acquisition Block • Acquire GPS signals Tracking Block • Locking to GPS signals • 12ch correlations Costas Loop & DLL Computation & Control • Control Acquisition & Tracking block • Position calculating ARM7TDMI I/O UART A/D RTC Timer 3ch RAM 72KB ROM 288KB X'tal 32.768kHz –3– CXD2951GA-2 Pin Configuration (Top View) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V 87 EA3 85 EA5 81 CVSS3 79 EA9 76 IOVDD2 75 IOVSS2 71 EA15 67 EA19 64 ETEST0 62 CVSS2 59 57 53 TEST OUTP 50 49 47 RFIN V IF2GND IF1GND MIXGND LNASRC U 90 EA0 88 EA2 86 EA4 83 EA7 80 EA8 77 EA11 73 EA13 70 EA16 68 EA18 63 CVDD2 60 VCOM 56 IF1VCC 54 48 46 45 44 42 U TEST MIXGND MIXGND LNASRC MIXGND NRING OUTN T 92 CVDD4 89 EA1 84 EA6 82 CVDD3 78 EA10 74 EA12 72 EA14 69 EA17 66 65 61 RREF 58 52 55 51 40 43 41 T ETEST2 ETEST1 IF2VCC TESTINN TEST TESTINP RFSUB RFRREF LNAMAT OUTD R 93 ECLKI 91 CVSS4 96 IOVDD3 37 39 38 R VDDVCO VCODE VSSVCO CAP P 94 ECLKO 95 IOVSS3 98 EXROMI 33 VDDCP 35 LPFRF 36 VSSCP P N 102 97 100 31 32 34 LPFIF N EADVRB ECLKOUT EAVDPLL VDDPLL VSSPLL M 104 99 103 27 28 30 M EVIN1 EAVSPLL EVIN0 ETESTTCK TMS RADIOSUB L 106 101 105 EVIN2 29 24 26 TCK L EVIN3 EAVSAD ETESTTMS TDI K 110 108 107 25 21 22 K ETEST3 EAVDAD EADVRT ETESTTDI ETESTTINT TDO J 112 IOVDD7 109 IOVSS8 111 ETEST4 23 ETESTTDO 19 CVDD1 18 CVSS1 J H 115 114 113 20 TRST 15 17 H ECCKI BKUPCVDD BKUPCVSS IOVDD1 EXTCXO G 116 117 119 13 12 16 G ECCKO BKUPIOVSS EOSCEN EPORT12 EPORT11 ETCXO F 118 121 122 11 9 14 F BKUPIOVDD ECLKS1 ECLKS2 EPORT10 EPORT8 IOVSS1 E 120 123 125 EXCS1 7 EPORT6 6 10 E ECLKS0 IOVSS4 EPORT5 EPORT9 D 126 EXOE 124 EXCS0 127 EXWE3 5 EPORT4 3 8 D EPORT2 EPORT7 C 128 131 129 EXWE1 137 ED27 139 ED25 143 ED21 145 ED19 147 ED17 155 ED15 158 ED12 161 ED9 165 ED5 167 ED3 169 ED1 173 1 176 4 C EXWE2 IOVSS5 ERXD0 EPORT0 IOVDD6 EPORT3 B 130 132 133 ED31 135 ED29 138 ED26 141 ED23 146 ED18 149 CVSS5 150 CVDD5 154 IOVDD5 157 ED13 159 ED11 163 ED7 164 ED6 171 CVSS6 175 IOVSS7 174 2 B EXWE0 IOVDD4 ETXD0 EPORT1 A 134 ED30 136 ED28 140 ED24 142 ED22 144 ED20 148 ED16 151 152 153 156 160 ED10 162 ED8 166 ED4 168 ED2 170 ED0 172 CVDD6 A EXRS ETESTXRS IOVSS6 ED14 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 : Pin 1 index. –4– CXD2951GA-2 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol EPORT0 EPORT1 EPORT2 EPORT3 EPORT4 EPORT5 EPORT6 EPORT7 EPORT8 EPORT9 EPORT10 EPORT11 EPORT12 IOVSS1 IOVDD1 ETCXO EXTCXO CVSS1 CVDD1 TRST ETESTTINT TDO ETESTTDO TDI ETESTTDI TCK ETESTTCK TMS I O O O I I I I I I O I/O I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Description I/O port 0 (with a software controllable pull-down resistor, Connected to GND with a resistor.) I/O port 1 (with a software controllable pull-down resistor, See software application note.) I/O port 2 (with a software controllable pull-down resistor, See software application note.) I/O port 3 (with a software controllable pull-down resistor, See software application note.) I/O port 4 (with a software controllable pull-down resistor, See software application note.) I/O port 5 (with a software controllable pull-down resistor, See software application note.) I/O port 6 (with a software controllable pull-down resistor, See software application note.) I/O port 7 (with a software controllable pull-down resistor, See software application note.) I/O port 8 (with a software controllable pull-down resistor, See software application note.) I/O port 9 (with a software controllable pull-down resistor, See software application note.) I/O port 10 (with a software controllable pull-down resistor, See software application note.) I/O port 11 (with a software controllable pull-down resistor, See software application note.) I/O port 12 (with a software controllable pull-down resistor, See software application note.) GND 3.3V TCXO oscillator (Frequency selectable, See software application note.) GND 1.8V Test (Open, with a pull-down resistor) Test Test Test Test (Open, with a pull-up resistor) Test (Open, with a pull-up resistor) Test (Open, with a pull-down resistor) Test (Open, with a pull-down resistor) Test (Open, with a pull-up resistor) –5– CXD2951GA-2 Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Symbol ETESTTMS RADIOSUB VDDPLL VSSPLL VDDCP LPFIF LPFRF VSSCP VDDVCO VSSVCO VCODECAP RFSUB LNAMAT NRING RFRREF MIXGND LNASRC MIXGND RFIN MIXGND LNASRC MIXGND TESTINP TESTINN TESTOUTP TESTOUTN TESTOUTD IF1VCC IF1GND IF2VCC IF2GND VCOM RREF CVSS2 CVDD2 I/O I ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Description Test (Open, with a pull-up resistor) Radio GND PLL 1.8V PLL GND Charge pump 1.8V Loop filter for IF PLL Loop filter for RF PLL Charge pump GND VCO 1.8V VCO GND VCO decap pin RF GND LNA 1.8V LNA 1.8V External resistor pin Mixer GND LNA GND Mixer GND RF input Mixer GND LNA GND Mixer GND Radio test (Open) Radio test (Open) Radio test Radio test Radio test (Open) 1st IF 1.8V 1st IF GND 2nd IF 1.8V 2nd IF GND IF common voltage External resistor pin GND 1.8V ∗ Radio analog pins: See page 10 to 12 for details. –6– CXD2951GA-2 Pin No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol ETEST0 ETSET1 ETEST2 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 IOVSS2 IOVDD2 EA11 EA10 EA9 EA8 CVSS3 CVDD3 EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0 CVSS4 CVDD4 ECLKI ECLKO IOVSS3 IOVDD3 ECLKOUT EXROMI EAVSPLL EAVDPLL I/O I I I O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z External expansion address 19 External expansion address 18 External expansion address 17 External expansion address 16 External expansion address 15 External expansion address 14 External expansion address 13 External expansion address 12 GND 3.3V O/Z O/Z O/Z O/Z External expansion address 11 External expansion address 10 External expansion address 9 External expansion address 8 GND 1.8V O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z External expansion address 7 External expansion address 6 External expansion address 5 External expansion address 4 External expansion address 3 External expansion address 2 External expansion address 1 External expansion address 0 GND 1.8V I O CPU clock oscillator GND 3.3V O/Z I Test (Connect to GND.) Description 1PPS output (Effective 1s late after reset release) Boot selection (Low: Internal ROM, High: External Memory/EXCS0) PLL GND PLL 3.3V –7– CXD2951GA-2 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Symbol EAVSAD EADVRB EVIN0 EVIN1 EVIN2 EVIN3 EADVRT EAVDAD IOVSS8 ETEST3 ETEST4 IOVDD7 BKUPCVSS BKUPCVDD ECCKI ECCKO BKUPIOVSS BKUPIOVDD EOSCEN ECLKS0 ECLKS1 ECLKS2 IOVSS4 EXCS0 EXCS1 EXOE EXWE3 EXWE2 EXWE1 EXWE0 IOVSS5 IOVDD4 ED31 ED30 ED29 ED28 ED27 ED26 I/O A/D converter GND I I I I I I Description A/D converter Reference input Bottom A/D converter Analog input 0 A/D converter Analog input 1 A/D converter Analog input 2 A/D converter Analog input 3 A/D converter Reference input Top A/D converter 3.3V GND I/O/Z I/O/Z (Connect to GND with a resistor.) (Connect to GND with a resistor.) 3.3V Backup core power supply GND Backup core power supply 1.8V I O RTC oscillator (32.768kHz) Backup I/O power supply GND Backup I/O power supply 3.3V I I I I O/Z O/Z O/Z O/Z O/Z O/Z O/Z Oscillator enable (H-Active), See backup mode section. Test (Connect to GND.) Test (Connect to GND.) Test (Connect to GND.) GND External expansion chip selection 0 (Program boot is enable if EXROMI is high.) External expansion chip selection 1 External expansion read signal External expansion write signal External expansion write signal External expansion write signal External expansion write signal GND 3.3V I/O I/O I/O I/O I/O I/O External expansion data 31 (with a pull-down resistor) External expansion data 30 (with a pull-down resistor) External expansion data 29 (with a pull-down resistor) External expansion data 28 (with a pull-down resistor) External expansion data 27 (with a pull-down resistor) External expansion data 26 (with a pull-down resistor) –8– CXD2951GA-2 Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Symbol ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 CVSS5 CVDD5 EXRS ETESTXRS IOVSS6 IOVDD5 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 CVSS6 CVDD6 ERXD0 ETXD0 IOVSS7 IOVDD6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description External expansion data 25 (with a pull-down resistor) External expansion data 24 (with a pull-down resistor) External expansion data 23 (with a pull-down resistor) External expansion data 22 (with a pull-down resistor) External expansion data 21 (with a pull-down resistor) External expansion data 20 (with a pull-down resistor) External expansion data 19 (with a pull-down resistor) External expansion data 18 (with a pull-down resistor) External expansion data 17 (with a pull-down resistor) External expansion data 16 (with a pull-down resistor) GND 1.8V I I Reset (L-Active) Test (Open, with a pull-up resistor) GND 3.3V I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O External expansion data 15 (with a pull-down resistor) External expansion data 14 (with a pull-down resistor) External expansion data 13 (with a pull-down resistor) External expansion data 12 (with a pull-down resistor) External expansion data 11 (with a pull-down resistor) External expansion data 10 (with a pull-down resistor) External expansion data 9 (with a pull-down resistor) External expansion data 8 (with a pull-down resistor) External expansion data 7 (with a pull-down resistor) External expansion data 6 (with a pull-down resistor) External expansion data 5 (with a pull-down resistor) External expansion data 4 (with a pull-down resistor) External expansion data 3 (with a pull-down resistor) External expansion data 2 (with a pull-down resistor) External expansion data 1 (with a pull-down resistor) External expansion data 0 (with a pull-down resistor) GND 1.8V I O/Z UART (CH0) reception data (with a pull-down resistor during reset interval) UART (CH0) transmission data (with Hi-Z during reset interval) GND 3.3V –9– CXD2951GA-2 Radio Pin Description Pin No. 30 31 32 33 Symbol RADIOSUB VDDPLL VSSPLL VDDCP Standard pin voltage [V] 0 1.8 0 1.8 VDDCP IF2VCC Equivalent circuit Description Radio GND PLL 1.8V PLL GND Charge pump 1.8V 34 LPFIF 0.8 34 1k 5k IF PLL loop filter connection VSSCP VDDCP IF2GND VDDVCO IF1VCC 35 LPFRF 0.9 1k 35 1k RF PLL loop filter connection 39 VCODECAP 0.65 VSSCP 39 1k Capacitor connection for decoupling the VCO bias circuit VSSVCO 36 37 38 40 42 VSSCP VDDVCO VSSVCO RFSUB NRING 0 1.8 0 0 1.8 IF1VCC Charge pump GND VCO 1.8V VCO GND RF GND LNA 1.8V 43 RFRREF 0.1 43 250 IF1GND External resistor connection (LNA, RF mixer bias) – 10 – CXD2951GA-2 Pin No. 44 45 46 Symbol MIXGND LNASRC VDDCP Standard pin voltage [V] 0 0 1.8 IF1VCC Equivalent circuit Description Mixer GND LNA GND Charge pump 1.8V 41 41 LNAMAT 1.8 7k LNA 1.8V 47 47 RFIN — 10k LNASRC RF input 48 49 50 MIXGND LNASRC MIXGND 0 0 0 IF1VCC Mixer GND LNA GND Mixer GND 51 TESTINP — 51 200 Radio test input pin Normally leave open. 200 52 52 TESTINN — IF1GND Radio test input pin Normally leave open. IF1VCC 53 TESTOUTP — 53 Radio test output pin Capacitor and resistor connection 54 54 TESTOUTN — IF1GND Radio test output pin Capacitor and resistor connection – 11 – CXD2951GA-2 Pin No. Symbol Standard pin voltage [V] IF2VCC Equivalent circuit Description 55 TESTOUTD — 55 Radio digital test output pin Normally leave open. IF2GND 56 57 58 59 IF1VCC IF1GND IF2VCC IF2GND 1.8 0 1.8 0 IF1VCC 1st IF 1.8V 1st IF GND 2nd IF 1.8V 2nd IF GND 40k 60 VCOM 1.0 60 1k 50k IF common voltage IF1GND IF1VCC 61 RREF 1.1 6k 61 External resistor connection (VCO, PLL, IF block bias) IF1GND – 12 – CXD2951GA-2 A/D Converter Operating Conditions Item Supply voltage Operating temperature Symbol VAD Ta Pin name EAVDAD∗1 — Min. 3.0 –40.0 Typ. 3.3 Max. 3.6 +85.0 Unit V °C A/D Converter Characteristics Item Resolution Channel Differential linearity error (DLE) Integral linearity error (ILE) Sampling time Conversion time Reference input voltage (Top) Reference input voltage (Bottom) Analog input voltage Current consumption Applicable pins ∗1 EAVDAD (Pin 108) ∗2 EADVRT (Pin 107) ∗3 EADVRB (Pin 102) ∗4 EVIN[0:3] (Pins 103 to 106) VRT∗2 VRB∗3 VIN∗4 VAD = 3.0V Symbol Conditions (VAD = 3.0 to 3.6V, Ta = –40 to +85°C) Min. Typ. Max. 10 4 VAD = 3.0V, VRT = 3.0V, VRB = 0.3V TCXO = 18.414MHz –1.0 –2.0 3 11 2.0 0 VRB 1.6 VAD 0.7 VRT +1.0 +2.0 Unit Bit Ch LSB LSB µs µs V V V mA – 13 – CXD2951GA-2 DC Characteristics Item Input voltage∗1 Output voltage∗2 Output voltage∗3 Pull-up resistor∗4 Pull-down resistor∗5 High level Low level High level Low level High level Low level (IOVDD = 3.0 to 3.6V, CVDD = 1.62 to 1.98V, Ta = –40 to +85°C) Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 RU RD TCXO = 18.414MHz, Ta = 25°C BKUPIOVDD = 3.6V, Ta = 25°C BKUPIOVDD = 3.6V, Ta = 85°C BKUPCVDD = 1.98V, Ta = 25°C BKUPCVDD = 1.98V, Ta = 85°C IOH = 4mA IOL = 4mA IOH = 8mA IOL = 8mA 48 40 60 0.2 0.2 7.5 50 1.0 1.0 15 120 2.4 0.4 110 100 Conditions Min. 2.0 –0.3 2.4 0.4 Typ. Max. 5.5 0.8 Unit V V V V V V kΩ kΩ mA µA µA µA µA Current consumption during normal IOPE operation (via IOVDD, CVDD and VDD)∗6 Current consumption during backup operation (via BKUPIOVDD)∗7 ISTB1 Current consumption during backup operation (via BKUPCVDD)∗8 ISTB2 Applicable pins ∗1 Pins 1 to 13, 20, 24 to 29, 64 to 66, 98, 119, 120 to 122, 133 to 148, 151, 152, 155 to 170, 173 ∗2 Pins 1 to 13, 21 to 23, 97, 174 ∗3 Pins 67 to 74, 77 to 80, 83 to 90, 124 to 130, 133 to 148, 155 to 170 ∗4 Pins 24, 25, 28, 29, 152 ∗5 Pins 1 to 13, 20, 26, 27, 133 to 148, 155 to 170, 173 ∗6 Pins 15, 76, 96, 100, 108, 112, 118, 132, 154, 176 (3.3V) Pins 19, 31, 33, 37, 41, 42, 56, 58, 63, 82, 92, 114, 150, 172 (1.8V) ∗7 Pin 118 ∗8 Pin 114 – 14 – CXD2951GA-2 AC Characteristics • External Expansion Bus (Read/32-bit mode) (CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = –40 to +85°C) Item EXOE ↓ to address valid EXOE ↓ to EXCS ↓ Data setup Data hold Symbol Toea Toecs Tas Tah Min. Max. 3 1 15 0 Unit ns ns ns ns EXOE Toea EA[19:0] Toecs EXCS[1:0] Tas ED[31:0] Tah – 15 – CXD2951GA-2 • Extarnal Expansion Bus (Write/32-bit mode (1-wait)) (CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = –40 to +85°C) Item EXCS ↓ to address valid EXCS ↓ to EXWE ↓ EXCS ↓ to EXWE ↑ EXCS ↓ to data valid ∗ Tsys: ARM clock cycle Symbol Tcsfav Tcswef Tcswer Tcsd Min. Max. 2 Tsys – 1 Tsys × 3 – 2 15 Unit ns ns ns ns T1 T2 T3 EXCS[1:0] Tcsfav EA[19:0] Tcswer Tcswef EXWE[3:0] Tcsd ED[31:0] – 16 – CXD2951GA-2 Backup Mode The backup mode is established by setting both EOSCEN and EXRS low. In this mode, the low power consumption can be achieved by stopping all oscillators except for RTC oscillator during the reset interval. Although all registers are initialized, the SRAM contents in backup area are held. In order to cancel this mode (reset cancellation), set EOSCEN high at first and then set EXRS high after the oscillation stabilization time and PLL lock time have passed. It needs 100ms or more. See Initialization section. Normal operation Backup Reset Normal operation IOVDD CVDD BKUPIOVDD BKUPCVDD OSC, PLL output EOSCEN EXRS Oscillation stabilization time PLL lock time (0.5ms max.) ED[31:0], EPORT[12:0], ERXD0 ETXD0 EXCS[1:0], EXWE[3:0], EXOE EA[19:0], ECLKOUT Power Off Power Off Power Off Power Off Pull-down output Hi-Z output High output Low output – 17 – CXD2951GA-2 Initialization The CXD2951GA-2 is initialized by setting the reset signal EXRS (Pin 151) to the low level. Note that internal RAM is not initialized by the operation. Satisfy the conditions shown below for the timing and others. 1. When turning the power on (Power-on reset) VDD Power supply, EOSCEN (Pin 119) VDD [V] 100ms or more VDD/2 EXRS (Pin 151) GND The power supply both 3.3V and 1.8V should turn on simultaneously, and EOSCEN (Pin 119) should also rise simultaneously with the power supply turning on. EXRS (Pin 151) should rise 100ms or more after the power supply and EOSCEN rise. 2. Initialization during operation Power supply, EOSCEN (Pin 119) VDD EXRS (Pin 151) VDD [V] 100µs or more VDD/2 GND For initialization during operation, the interior circuit except internal RAM is initialized by setting the EXRS (Pin 151) signal to the low level for 100µs or more. Note that internal RAM is not also initialized by the operation. At this time, the EOSCEN (Pin 119) signal should keep the high level. – 18 – CXD2951GA-2 RTC crystal and TCXO In order to operate CXD2951GA-2 appropriately, the recommended characteristics of RTC crystal and TCXO is shown below. Recommended characteristics of RTC crystal Operating temperature Nominal frequency Frequency tolerance Frequency temperature coefficient Frequency peak temperature Frequency aging –40 to +85°C 32.768kHz ±20ppm –0.04ppm/°C2 (Max.) +25 ± 5°C ±3ppm/year Recommended characteristics of TCXO Operating temperature Frequency tolerance Frequency vs. temperature Frequency vs. supply voltage Frequency vs. load Frequency aging Recommended parts RTC crystal TCXO EPSON FC-255 NDK SNA3088B (NT5032 series) –40 to +85°C ±2.0ppm ±2.5ppm ±0.2ppm ±0.2ppm ±1ppm/year – 19 – CXD2951GA-2 Radio Block Operation Radio block diagram shows RF section of the chip. The signal flow starts from the RFIN port (Pin 47). The signal is amplified and mixed down to the first Intermediate Frequency (IF) of 2MHz with cosine and sine wave quadrature mixers. Out of band images are filtered out and the signal is again mixed down to the 2nd IF of 1MHz with another set of quadrature mixers. The complex signal becomes real with the addition of real and imaginary components. The image of the 2nd IF mixing is removed with the last Band Pass Filter (BPF). The real signal is then amplified one last time and transferred to digital baseband processing unit. RF Digital Reset CLK RF Analog BPF A/D Converter Data RFIN 1st IF (2MHz) BPF RF Local (1573MHz) VCO IF Local (3MHz) VCO BUF PLLCLK BPF PLL BIAS PLL TEST Enable LPFRF LPFIF Radio Block Diagram To have constant internal frequencies for mixing and other purposes, the supplied TCXO frequency is counted by a Real Time Clock (RTC), and the internal PLL divider is automatically set to provide correct frequency for RF mixing and baseband operation. The loop filters (RF and IF) are externally connected. Use parts that satisfy the required tolerance. – 20 – Baseband 2nd IF (1MHz) CXD2951GA-2 Radio Characteristics DC Characteristics Item Supply current 1 Supply current 2 Symbol IDD IPS Conditions Active mode∗1 Power save mode∗1 Min. 13.5 — (VDD = 1.8V, Ta = 25°C) Typ. 17 0.1 Max. 20.5 1.5 Unit mA µA ∗1 Applicable pins 31, 33, 37, 41, 42, 56, 58 AC Characteristics Item Total gain Image rejection ratio 2nd IF filter 2.5MHz 2nd IF filter 4MHz Symbol G IMRR Fc Fa Conditions Before the A/D converter Image frequency = 1571.328MHz @2.5MHz Normalized at 1.023MHz @4MHz Normalized at 1.023MHz Min. 90 — –6 — (VDD = 1.8V, Ta = 25°C) Typ. 100 –35 0 –25 Max. — –15 4 –15 Unit dB dB dB dB ∗ Including the 50Ω matching circuit Design Measurement Results Item Total NF IIP3 P-1dB input S11 Lock up time C/N 100K Local leak Symbol NF IIP3 P1dB S11 LUT C/N Leak Measure the interval between reset input and IF output. TCXO = 18.414MHz Measure at RF input. Conditions Before the 2nd IF mixer Before the A/D converter Before the A/D converter Min. — — — — — — — (VDD = 1.8V, Ta = 25°C) Typ. 8 –90 –100 –15 2.5 –70 –65 Max. — — — — — — — Unit dB dBm dBm dB ms dBc/Hz dBm ∗ Including the 50Ω matching circuit – 21 – CXD2951GA-2 Radio Supplement Materials (Example of Representative Characteristics) IDD 24 22 20 IDD [mA] Input/output characteristic 10 VDD = 1.8V Ta = 25˚C 5 0 Output level [dBm] VDD = 1.8V Ta = 25˚C –5 –10 –15 –20 –25 –30 18 16 14 12 10 1.6 –35 1.8 VDD [V] 2.0 –40 –135 –130 –125 –120 –115 –110 –105 –100 –95 –90 –85 Input level [dBm] IIP3 10 5 0 –60 Output level [dBm] C/N –50 –55 VDD = 1.8V Ta = 25˚C –5 –10 –15 –20 –25 –80 –30 –35 VDD = 1.8V Ta = 25˚C –85 –90 10 C/N [dBc/Hz] –65 –70 –75 –40 –130 –125 –120 –115 –110 –105 –100 –95 –90 –85 –80 –75 –70 Input level [dBm] 100 Offset frequency [kHz] 1000 Image rejection ratio –20 VDD = 1.8V Ta = 25˚C Response [dB] IF filter response (simulation) 5 0 –5 –10 –15 –20 –25 –30 –25 –30 IMRR [dB] –35 –40 –45 –35 –50 0 0.5 1.0 1.5 2.0 2.5 3.0 IF frequency [MHz] –40 1.570 1.571 1.572 1.573 1.574 1.575 1.576 1.577 1.578 1.579 1.580 1.581 Frequency [GHz] Filter characteristic represented by RF frequency as x-axis (Normalized at 1.023MHz) – 22 – CXD2951GA-2 RFIN input impedance +j50 +j25 +j100 +j10 0 25 50 100 ∞ –j10 2GHz 1.8GHz 1.2GHz 1.6GHz 1.4GHz 1GHz –j50 –j25 –j100 – 23 – Application Circuit L046 56nH 10P CN012 1 2 3 4 5 6 7 8 9 10 JS041 0 R062 22 R205 47k L002 22µH C004 22µ 1 VOUT 5 NC C161 2 GND 10µ 4 3 VDD CE R1124N331D R013 470k C013 10µ C046 0.1µ 1 VDD IC004 2 GND R3112Q291A OUT 4 CD 3 C045 0.1µ C121 0.1µ R001 22 R002 22 R063 22 R202 XX IC002 XX TXD0 RXD0 RXD1 NMEA/Orig UPDATE RESET/POWER DOWN DGND VDD (3.3V/5V) BATT AGND R004 10k R005 10k JS040 0 L003 10µH 1 XRESET 2 GND 3 Reset In IC003 MAX6364 BATT 6 OUT 5 Vcc 4 1 IC006 R1160N181B VDD VOUT 5 BKUPCVDD_1.8V IC005 R1124N181D 1 VOUT 5 NC 2 GND C048 2.2µ 3 VDD 4 CE C066 10µ C162 10µ L045 1µH C150 10µ BKUPIOVDD_3.3V L040 1µH 2 GND ECO 4 3 CE C059 0.1µ JS025 0 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. SYSTEM_RESET C069 0.1µ C072 0.1µ C077 0.1µ C079 0.1µ ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 C2 B3 B2 C4 A2 B4 A3 C5 A4 C6 A5 C7 B5 B6 A6 C8 A7 B7 C9 B8 A8 C10 B9 A9 A10 A11 B10 B11 A12 C11 B12 C12 A13 C13 A14 B13 A15 C14 B14 C15 A16 B16 A17 B16 152 ETESTXRS ED31 C088 0.1µ B17 C17 B18 C16 C18 D16 D18 E16 D17 E17 F16 F17 E18 G16 R203 22 X002 C089 0.1µ C085 12p C086 12p C090 0.1µ R057 100k R056 100k C3 1 B1 2 D2 3 C1 4 D3 5 E2 6 E3 7 D1 8 F2 9 R204 22 EPORT0 EPORT1 EPORT2 EPORT3 EPORT4 EPORT5 EPORT6 EPORT7 EPORT8 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 IOVDD4 IOVSS5 EXWE0 EXWE1 EXWE2 EXWE3 EXOE EXCS1 EXCS0 IOVSS4 ECLKS2 ECLKS1 ECLKS0 EOSCEN Note) The following should be guaranteed within operating temperature. • R tolerance: ±5% or less • C tolerance: ±20% or less • L tolerance: ±20% or less 176 IOVDD6 173 ERXD0 154 IOVDD5 175 IOVSS7 153 IOVSS6 174 ETXD0 172 CVDD6 150 CVDD5 171 CVSS6 155 ED15 151 EXRS 149 CVSS5 160 ED10 159 ED11 158 ED12 157 ED13 156 ED14 148 ED16 147 ED17 146 ED18 145 ED19 144 ED20 143 ED21 142 ED22 141 ED23 140 ED24 139 ED25 138 ED26 137 ED27 136 ED28 135 ED29 134 ED30 E1 10 EPORT9 F3 11 EPORT10 G2 12 EPORT11 C067 0.1µ G3 13 EPORT12 F1 14 IOVSS1 H2 15 IOVDD1 133 ED31 BKUPIOVDD F18 BKUPIOVSS G17 ECCKO ECCKI G18 H18 170 ED0 169 ED1 168 ED2 167 ED3 166 ED4 165 ED5 164 ED6 163 ED7 162 ED8 161 ED9 C060 0.01µ R020 1M G1 16 ETCXO H1 17 EXTCXO J1 18 CVSS1 C124 0.1µ A11 A8 Vcc DQ26 Vss DQ25 NC A12 DQ21 Vss DQ27 DQ11 DQ10 NC NC DQ7 DQ8 DQ6 NC DQ5 L2 24 TDI K3 25 ETESTTDI L1 26 TCK 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 IOVSS8 EAVDAD EADVRT EVIN3 EVIN2 EVIN1 EVIN0 EADVRB EAVSAD EAVDPLL EAVSPLL EXROMI ECLKOUT IOVDD3 IOVSS3 ECLKO ECLKI CVDD4 CVSS4 EA0 EA1 J17 K17 K16 L18 L16 M18 M16 N18 L17 N16 M17 P16 N17 R16 P17 P18 R18 T18 R17 U18 T17 EA15 C094 0.1µ CVDD_1.8V EA9 EA12 ED9 R201 XX C093 0.1µ C126 0.1µ EA16 EA19 C092 0.1µ R028 XX L024 1µH R025 100k C125 0.1µ ED24 EA17 H5 NC H6 A15 H7 A18 H8 DQ24 H9 Vcc ED22 ED23 EA8 EA11 J1 DQ22 J2 DQ23 J3 A6 J4 A9 J5 NC J6 A14 J7 A17 J8 Vcc J9 DQ9 K2 Vss K3 A7 K4 A10 K5 NC K6 A13 K7 A16 K8 A19 C122 0.1µ C139 0.001µ JS039 0 C140 0.068µ C141 3300p C142 680p C143 68p R197 470 C153 XX DQ4 54 TESTOUTN 55 TESTOUTD 53 TESTOUTP 52 TESTINN 51 TESTINP 45 LNASRC 49 LNASRC 46 MIXGND 48 MIXGND 50 MIXGND 64 ETEST0 65 ETSET1 59 IF2GND 66 ETEST2 57 IF1GND 76 IOVDD2 75 IOVSS2 56 IF1VCC 58 IF2VCC 63 CVDD2 82 CVDD3 60 VCOM 62 CVSS2 81 CVSS3 61 RREF 77 EA11 78 EA10 67 EA19 68 EA18 69 EA17 70 EA16 71 EA15 72 EA14 73 EA13 74 EA12 47 RFIN 79 EA9 80 EA8 83 EA7 84 EA6 85 EA5 86 EA4 87 EA3 88 EA2 DQ30 DQ17 XWE XWP CL001 CL002 CL005 C147 0.01µ A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA6 EA3 EA7 EA4 EA9 EA8 EA7 EA6 EA5 EA4 EA3 CL003 CL004 C146 0.001µ R200 56k EA2 ED30 ED17 DE1 R206 1M C166 100p R207 1M C167 100p C148 XX C076 0.1µ C082 0.1µ C083 0.1µ C129 0.1µ Note) If a Flash ROM is used, the programs which are GPS software, Flash updater etc. required for desired operation should be written into a Flash ROM in advance. C154 0.1µ L035 56nH C158 0.1µ L036 56nH ED0 EA5 XOE ACC XCE DQ1 DQ0 U3 U4 V2 U5 V3 V4 T4 T6 V5 U6 T5 U7 V6 T7 V7 U8 T8 V8 U9 V9 T9 T10 V10 U10 T11 U11 V11 T12 U12 T13 V12 V13 U13 T14 V14 U14 V15 T15 U15 T16 V16 U16 V17 U17 DW/XW Vcc Vss NC NC NC NC A4 A1 A5 A2 A3 – 24 – ED26 ED25 ED21 ED27 ED11 ED10 ED7 ED8 ED6 ED5 EA13 EA10 K2 21 ETESTTINT X001 L051 56nH K1 22 TDO J3 23 ETESTTDO IOVDD7 ETEST4 ETEST3 J18 J16 K18 IC020 CXD2951GA-2 110 H4 H3 H2 H1 G9 G8 G7 G6 G5 G4 G3 G2 G1 F9 F8 F7 F6 F5 F4 F3 F2 EA14 C068 0.1µ J2 19 CVDD1 H3 20 TRST BKUPCVDD H17 BKUPCVSS H16 ED4 M3 27 ETESTTCK M2 28 TMS L3 29 ETESTTMS M1 30 RADIOSUB N3 31 VDDPLL N2 32 VSSPLL P3 33 VDDCP N1 34 LPFIF P2 35 LPFRF R198 33k C144 0.01µ L004 2.7nH P1 36 VSSCP R3 37 VDDVCO R1 38 VSSVCO R2 39 VCODECAP L039 12nH C145 10p T3 40 RFSUB T1 41 LNAMAT JS037 XX R199 2k JS038 0 U1 42 NRING T2 43 RFRREF U2 44 MIXGND DQ20 F1 DQ12 E9 DQ28 E8 Vss E7 NC E6 NC E5 DQ2 E4 DQ18 E3 DQ19 E2 DQ3 E1 ED20 ED12 ED28 ED2 ED18 ED19 ED3 ED13 ED29 ED14 ED31 C149 0.01µ IC021 MBM29PL320 DQ13 D9 DQ29 D8 DQ14 D7 DQ31/A-1 D6 NC D5 A0 D4 DQ16 D3 Vss D2 Vcc D1 Vcc C9 DQ15 C8 EA2 ED16 C127 0.1µ EA18 ED15 C128 0.1µ CXD2951GA-2 C134 0.001µ C132 39p L044 4.7nH L034 15nH IC022 1 2 NJG1107KB2 6 5 4 L018 27nH C163 XX C157 XX L048 12nH SWF001 C159 0.001µ C155 1p L043 3.3nH L042 15nH IC024 1 2 3 C156 100p NJG1107KB2 6 5 4 L023 82nH L041 12nH TP001 L050 3.9nH 3 C131 100p CXD2951GA-2 Radio Block Application Circuit M3 27 ETESTTCK M2 28 TMS C139 0.001µ JS039 0 C140 0.068µ C141 3300p C142 680p C143 68p R197 470 C153 XX L3 29 ETESTTMS M1 30 RADIOSUB N3 31 VDDPLL N2 32 VSSPLL P3 33 VDDCP N1 34 LPFIF P2 35 LPFRF R198 33k C144 0.01µ L004 2.7nH P1 36 VSSCP R3 37 VDDVCO R1 38 VSSVCO R2 39 VCODECAP L039 12nH C145 10p T3 40 RFSUB T1 41 LNAMAT JS037 XX R199 2k JS038 0 U1 42 NRING T2 43 RFRREF U2 44 MIXGND 54 TESTOUTN 55 TESTOUTD 53 TESTOUTP 52 TESTINN 51 TESTINP 45 LNASRC 49 LNASRC 46 MIXGND 48 MIXGND 50 MIXGND 64 ETEST0 65 ETSET1 59 IF2GND 66 ETEST2 57 IF1GND 76 IOVDD2 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. C149 0.01µ 75 IOVSS2 56 IF1VCC 58 IF2VCC 63 CVDD2 60 VCOM 62 CVSS2 61 RREF 77 EA11 78 EA10 67 EA19 68 EA18 69 EA17 70 EA16 71 EA15 72 EA14 73 EA13 74 EA12 47 RFIN 79 EA9 EA9 U3 U4 V2 U5 V3 V4 T4 T6 V5 U6 T5 U7 V6 T7 V7 U8 T8 V8 U9 V9 T9 T10 V10 U10 T11 U11 V11 T12 U12 T13 V12 V13 U13 T14 V14 U14 CL001 CL002 CL005 C147 0.01µ EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 C146 0.001µ CL003 R206 1M C166 100p R207 1M C167 100p CL004 R200 56k C148 XX C076 0.1µ C082 0.1µ C154 0.1µ L035 56nH C134 0.001µ C132 39p L044 4.7nH L034 15nH IC022 1 2 NJG1107KB2 6 5 4 L050 3.9nH 3 C131 100p Enlarged view of the previous page Parts ID C139 to C147, C149, C166, C167 L004, L039, L050 R197 to R200 R206, R207 Parts name MURATA GRM36CH series Remarks Tolerance: ±5% C145: Self-resonant frequency 2.0GHz or more Tolerance: ±5% L050: Self-resonant frequency 2.0GHz or more Tolerance: ±1% Tolerance: ±5% TAIYO YUDEN HK1005 series KOA RK73H series KOA RK73B series ∗ Always use matching circuit for the RF amplifier input pin (Pin 47), and match at 1.57542GHz. ∗ The external elements should be placed as close to the chip as possible. – 25 – EA8 80 EA8 CXD2951GA-2 Package Outline Unit: mm 176PIN LFLGA 0.1 SA 12.0 PIN 1 INDEX 1.3MAX 0.10MAX 12.0 x4 0.08 0.1 SB Y 0.2 S 3– 1.0 (0.55) (0.55) 1.2 0.5 A 176 – φ0.27 ± 0.04 φ0.05 M S A B DETAIL X V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 101112131415161718 1.2 B 1.2 1.0 0.5 DETAIL Y (0.55) C0.3 (0.55) 1.0 1.2 0.25 1.75 PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE NICKEL&GOLD PLATING COPPER 0.4g SONY CODE EIAJ CODE JEDEC CODE LFLGA-176P-052 P-LFLGA176-12x12-0.5 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS 1.75 φ0.35 S – 26 – Sony Corporation 0.08 S X
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