Single Chip GPS LSI
CXD2951GL-4
Description
The CXD2951GL-4 is a dedicated single chip LSI for the GPS (Global Positioning System), satellite-based location measurement system. This LSI enables the configuration of a single chip system providing a costeffective, low-power solution. Compared with conventional methods, position detection time and sensitivity are substantially improved with the use of an advanced signal processing scheme. With the integration of both the Radio and baseband blocks into a single CMOS IC, the CXD2951GL-4 is ideal for use in automotive, cellular handset, handheld navigation, mobile computing and other location-based applications.
Features
WAAS support 12-channel GPS receiver capable of simultaneously receiving 12 satellites Reception frequency: 1575.42MHz (L1 band, CA code) Reference clock (TCXO) frequency: 18.414MHz (GPS, Sony standard), The unique frequency of major applications is available, such as GSM and W-CDMA. (optional) 13.000MHz (GSM), 14.400MHz (CDMA), 16.368MHz (GPS), 19.800MHz (PDC/CDMA), 26.000MHz (GSM) 32 bits RISC CPU (ARM7TDMI) 288K-bytes Program ROM 72K-bytes Data RAM Power is supplied only to 8K-byte Data RAM while in backup mode. System power management 1-channel UART Internal RTC (Real Time Clock) 10-bit successive approximation system A/D converter All-in-view positioning Communication format: Supports NMEA-0183 (Ver 3.01) 1PPS output
< RADIO >
Image Rejection Mixer VCO Tank IF Filters
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E05313A5Z
CXD2951GL-4
Package
183 pin VFLGA (Plastic)
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage I/O Supply voltage core Supply voltage radio Input voltage Output voltage Operating temperature Storage temperature IOVDD CVDD VDD VI VO Topr Tstg –0.5 to +4.6 –0.5 to +2.5 –0.5 to +2.5 –0.5 to +6 –0.5 to +6 –40 to +85 –50 to +150 V V V V V
°C °C
Recommended Operating Conditions
Supply voltage I/O IOVDD 3.0 to 3.6 V
* Under operation with internal ROM, using no external expansion bus: IOVDD * Under operation in backup mode: BKUPIOVDD Supply voltage core Supply voltage radio Operating temperature CVDD VDD Topr 2.5 (Min.) 1.62 to 1.98 1.62 to 1.98 –40 to +85 V V V
°C
2.6 to 3.6
V
Input/Output Pin Capacitance (Baseband)
Input pin capacitance Output pin capacitance I/O pin capacitance CIN COUT CI/O 9 (Max.) 11 (Max.) 11 (Max.) pF pF pF
-2-
CXD2951GL-4
Performance
Baseband
Tracking sensitivity: –152dBm (average) or less Acquisition sensitivity: –139dBm (average) or less in Normal mode * Reference data using the Sony's reference board when using both an antenna of 0dBi and a RF amplifier with NF ≤ 2dB, 25dB gain. TTFF (Time to First Fix): Time until initial position measurement after power-on with the following conditions: Cold Start (without both ephemeris and almanac time): 40s (average) / 50s (95% possibility) Warm Start (without ephemeris but with almanac time): 33s (average) / 40s (95% possibility) Hot Start (with both ephemeris and almanac time): 2s (minimum) / 3s (95% possibility) * Reference data with elevation angle of 5° or more and no interception environment with satellite powers ≥ –130dBm. Note) “95% possibility” means “position time with 95% possibility”. Positioning accuracy: 2DRMS: approx. 2m * Reference data with elevation angle of 5° or more and no interception environment with satellite powers ≥ 30dBm. Measurement data update time: 1s Power consumption: 50mW (average) while position calculating with tracking satellites in low power mode 120mW (average) while position calculating with acquiring and tracking satellites * Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its amplitude is 3.3V swing. 1PPS output 1µs or less precision, 1PPS outputs from ECLKOUT (Pin 97). Note) These values are not guaranteed, depending on the conditions.
Radio
Total Gain (typ.): 100dB Noise figure (typ.): 8dB Synthesizer phase noise (typ.): –70dBc/Hz (10kHz) –80dBc/Hz (100kHz) PLL spurious (typ.): –45dBc (inside fosc ± 1.023MHz) –55dBc (outside fosc ± 1.023MHz) Note) These values are not guaranteed.
-3-
CXD2951GL-4
System Block Diagram
1575.42MHz
TCXO LNA CPU
Freq. Synthesizer
RF/IF 1575.42MHz → 1.023MHz
BPF SAW TCXO Reference clock 18.414MHz (GPS, Sony standard) LNA
Down Converter 1.023MHz
LPF
1 bit
Acquisition Block • Acquire GPS signals
Tracking Block • Locking to GPS signals • 12ch correlations Costas Loop & DLL
Computation & Control • Control Acquisition & Tracking block • Position calculating
ARM7TDMI
I/O UART A/D
RTC
Timer 3ch
RAM 72KB
ROM 288KB
X'tal 32.768kHz
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CXD2951GL-4
Pin Configuration
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
40 A
RFSUB
42
NRING NC
34
LPFIF
31
VDDPLL
32
VSSPLL
26
TCK
22
TDO
18
CVSS1
14
IOVSS1
12
9
6
3
1 A 173
ERXD0
EPORT11 EPORT8
EPORT5 EPORT2 EPORT0
46 B 48 C
MIXGND
44
43
35
LPFRF
33
30
28
TMS
24
TDI
20
TRST
16
11
8
5
EPORT4
2
EPORT1
176
IOVDD6
MIXGND MIXGND RFRREF
VDDCP RADIOSUB
ETCXO EPORT10 EPORT7
B
47
RFIN
45
41
39
VCODE CAP
37
VDDVCO
36
VSSCP
27
ETEST TCK
23
ETEST TDO
21
ETEST TINT
17
13
10
7
4
NC
175
IOVSS7
LNASRC LNAMAT
EXTCXO EPORT12 EPORT9
EPORT6 EPORT3
C
50 D
49
55
TEST OUTD
38
VSSVCO
29
ETEST TMS
25
ETEST TDI
19
CVDD1
15
IOVDD1 NC
172
CVDD6
171
CVSS6
MIXGND LNASRC
D
56 E
IF1VCC
52
51
174
ETXD0
169
ED1
167
ED3
TESTINN TESTINP
E
58 F
IF2VCC
54
TEST OUTN
53
TEST OUTP
170
ED0
165
ED5
163
ED7
F
G
57
IF1GND
59
IF2GND
60
VCOM
61
RREF
168
ED2
166
ED4
161
ED9
159
ED11
G
H
62
CVSS2
64
65
66
164
ED6
162
ED8
157
ED13
155
ED15
ETEST0 ETEST1 ETEST2
H
J
63
CVDD2
68
EA18
67
EA19
69
EA17
160
ED10
158
ED12
154
IOVDD5
153
IOVSS6
J
K
70
EA16
72
EA14
71
EA15
73
EA13
156
ED14
148
152
151
ED16 ETESTXRS EXRS
K
L
75
IOVSS2
74
EA12
77
EA11 NC
146
ED18
144
ED20
150
CVDD5 NC
L
M
76
IOVDD2
79
EA9 NC
142
ED22
147
ED17
149
CVSS5
M
N
81
CVSS3
83
EA7
78
EA10
140
ED24
143
ED21
145
ED19
N
P
82
CVDD3
85
EA5
80
EA8
105
EVIN2
108
110
112
IOVDD7
122
ECLKS2
138
ED26
139
ED25
141
ED23
P
EAVDAD ETEST3
R
88
EA2
87
EA3
90
EA0
94
ECLKO
98
102
103
EVIN0
106
EVIN3
111
ETEST4 NC
121
120
126
EXOE
128
EXWE2
136
ED28
135
ED29
137
ED27
R
EXROMI EADVRB
ECLKS1 ECLKS0
T
86
EA4
84
EA6
92
CVDD4
93
97
100
104
EVIN1
109
IOVSS8
114
116
118
125
124
EXCS0
130
EXWE0
134
ED30
132
IOVDD4
133
ED31
T
ECLKI ECLKOUT EAVDPLL
BKUPCVDD ECCKO BKUPIOVDD EXCS1
U
89
EA1
91
CVSS4
95
IOVSS3
96
99
101
107
113
115
117
119
123
127
EXWE3
129
EXWE1
131
IOVSS5
U
IOVDD3 EAVSPLL EAVSAD EADVRT BKUPCVSS ECCKI BKUPIOVSS EOSCEN IOVSS4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 : Pin 1 index.
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CXD2951GL-4
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol EPORT0 EPORT1 EPORT2 EPORT3 EPORT4 EPORT5 EPORT6 EPORT7 EPORT8 EPORT9 EPORT10 EPORT11 EPORT12 IOVSS1 IOVDD1 ETCXO EXTCXO CVSS1 CVDD1 TRST ETESTTINT TDO ETESTTDO TDI ETESTTDI TCK ETESTTCK TMS
I/O I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
Description I/O port 0 (with a software controllable pull-down resistor, Connected to GND with a resistor.) I/O port 1 (with a software controllable pull-down resistor, See software application note.) I/O port 2 (with a software controllable pull-down resistor, See software application note.) I/O port 3 (with a software controllable pull-down resistor, See software application note.) I/O port 4 (with a software controllable pull-down resistor, See software application note.) I/O port 5 (with a software controllable pull-down resistor, See software application note.) I/O port 6 (with a software controllable pull-down resistor, See software application note.) I/O port 7 (with a software controllable pull-down resistor, See software application note.) I/O port 8 (with a software controllable pull-down resistor, See software application note.) I/O port 9 (with a software controllable pull-down resistor, See software application note.) I/O port 10 (with a software controllable pull-down resistor, See software application note.) I/O port 11 (with a software controllable pull-down resistor, See software application note.) I/O port 12 (with a software controllable pull-down resistor, See software application note.) GND 3.3V
I O
TCXO oscillator (Frequency selectable, See software application note.) GND 1.8V
I O O O I I I I I
Test (Open, with a pull-down resistor) Test Test Test Test (Open, with a pull-up resistor) Test (Open, with a pull-up resistor) Test (Open, with a pull-down resistor) Test (Open, with a pull-down resistor) Test (Open, with a pull-up resistor)
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CXD2951GL-4
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Symbol ETESTTMS RADIOSUB VDDPLL VSSPLL VDDCP LPFIF LPFRF VSSCP VDDVCO VSSVCO VCODECAP RFSUB LNAMAT NRING RFRREF MIXGND LNASRC MIXGND RFIN MIXGND LNASRC MIXGND TESTINP TESTINN TESTOUTP TESTOUTN TESTOUTD IF1VCC IF1GND IF2VCC IF2GND VCOM RREF CVSS2 CVDD2 ETEST0 ETEST1 ETEST2 EA19
I/O I
*1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1
Description Test (Open, with a pull-up resistor) Radio GND PLL 1.8V PLL GND Charge pump 1.8V Loop filter for IF PLL Loop filter for RF PLL Charge pump GND VCO 1.8V VCO GND VCO decap pin RF GND LNA 1.8V LNA 1.8V External resistor pin Mixer GND LNA GND Mixer GND RF input Mixer GND LNA GND Mixer GND Radio test (Open) Radio test (Open) Radio test Radio test Radio test (Open) 1st IF 1.8V 1st IF GND 2nd IF 1.8V 2nd IF GND IF common voltage External resistor pin GND 1.8V
I I I O/Z External expansion address 19 Test (Connect to GND.)
-7-
CXD2951GL-4
Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
Symbol EA18 EA17 EA16 EA15 EA14 EA13 EA12 IOVSS2 IOVDD2 EA11 EA10 EA9 EA8 CVSS3 CVDD3 EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0 CVSS4 CVDD4 ECLKI ECLKO IOVSS3 IOVDD3 ECLKOUT EXROMI EAVSPLL EAVDPLL EAVSAD EADVRB EVIN0 EVIN1 EVIN2 EVIN3
I/O O/Z O/Z O/Z O/Z O/Z O/Z O/Z
Description External expansion address 18 External expansion address 17 External expansion address 16 External expansion address 15 External expansion address 14 External expansion address 13 External expansion address 12 GND 3.3V
O/Z O/Z O/Z O/Z
External expansion address 11 External expansion address 10 External expansion address 9 External expansion address 8 GND 1.8V
O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z
External expansion address 7 External expansion address 6 External expansion address 5 External expansion address 4 External expansion address 3 External expansion address 2 External expansion address 1 External expansion address 0 GND 1.8V
I O
CPU clock oscillator GND 3.3V
O/Z I
1PPS output (Effective 1s late after reset release) Boot selection (Low: Internal ROM, High: External Memory/EXCS0) PLL GND PLL 3.3V A/D converter GND
I I I I I
A/D converter Reference input Bottom A/D converter Analog input 0 A/D converter Analog input 1 A/D converter Analog input 2 A/D converter Analog input 3
-8-
CXD2951GL-4
Pin No. 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Symbol EADVRT EAVDAD IOVSS8 ETEST3 ETEST4 IOVDD7 BKUPCVSS BKUPCVDD ECCKI ECCKO BKUPIOVSS BKUPIOVDD EOSCEN ECLKS0 ECLKS1 ECLKS2 IOVSS4 EXCS0 EXCS1 EXOE EXWE3 EXWE2 EXWE1 EXWE0 IOVSS5 IOVDD4 ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20
I/O I
Description A/D converter Reference input Top A/D converter 3.3V GND
I/O/Z I/O/Z
(Connect to GND with a resistor.) (Connect to GND with a resistor.) 3.3V Backup core power supply GND Backup core power supply 1.8V
I O
RTC oscillator (32.768kHz) Backup I/O power supply GND Backup I/O power supply 3.3V
I I I I
Oscillator enable (H-Active), See backup mode section. Test (Connect to GND.) Test (Connect to GND.) Test (Connect to GND.) GND
O/Z O/Z O/Z O/Z O/Z O/Z O/Z
External expansion chip selection 0 (Program boot is enable if EXROMI is high.) External expansion chip selection 1 External expansion read signal External expansion write signal External expansion write signal External expansion write signal External expansion write signal GND 3.3V
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
External expansion data 31 (with a pull-down resistor) External expansion data 30 (with a pull-down resistor) External expansion data 29 (with a pull-down resistor) External expansion data 28 (with a pull-down resistor) External expansion data 27 (with a pull-down resistor) External expansion data 26 (with a pull-down resistor) External expansion data 25 (with a pull-down resistor) External expansion data 24 (with a pull-down resistor) External expansion data 23 (with a pull-down resistor) External expansion data 22 (with a pull-down resistor) External expansion data 21 (with a pull-down resistor) External expansion data 20 (with a pull-down resistor)
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CXD2951GL-4
Pin No. 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
*1
Symbol ED19 ED18 ED17 ED16 CVSS5 CVDD5 EXRS ETESTXRS IOVSS6 IOVDD5 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 CVSS6 CVDD6 ERXD0 ETXD0 IOVSS7 IOVDD6
I/O I/O I/O I/O I/O
Description External expansion data 19 (with a pull-down resistor) External expansion data 18 (with a pull-down resistor) External expansion data 17 (with a pull-down resistor) External expansion data 16 (with a pull-down resistor) GND 1.8V
I I
Reset (L-Active) Test (Open, with a pull-up resistor) GND 3.3V
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
External expansion data 15 (with a pull-down resistor) External expansion data 14 (with a pull-down resistor) External expansion data 13 (with a pull-down resistor) External expansion data 12 (with a pull-down resistor) External expansion data 11 (with a pull-down resistor) External expansion data 10 (with a pull-down resistor) External expansion data 9 (with a pull-down resistor) External expansion data 8 (with a pull-down resistor) External expansion data 7 (with a pull-down resistor) External expansion data 6 (with a pull-down resistor) External expansion data 5 (with a pull-down resistor) External expansion data 4 (with a pull-down resistor) External expansion data 3 (with a pull-down resistor) External expansion data 2 (with a pull-down resistor) External expansion data 1 (with a pull-down resistor) External expansion data 0 (with a pull-down resistor) GND 1.8V
I O/Z
UART (CH0) reception data (with a pull-down resistor during reset interval) UART (CH0) transmission data (with Hi-Z during reset interval) GND 3.3V
Radio analog pins: See page 11 to 14 for details.
- 10 -
CXD2951GL-4
Radio Pin Description
Standard pin voltage [V] 0 1.8 0 1.8
VDDCP IF2VCC
Pin No. 30 31 32 33
Symbol RADIOSUB VDDPLL VSSPLL VDDCP
Equivalent circuit
Description Radio GND PLL 1.8V PLL GND Charge pump 1.8V
34
LPFIF
0.8
34 1k 5k
IF PLL loop filter connection
VSSCP
IF2GND
VDDCP
VDDVCO
IF1VCC
35
LPFRF
0.9
1k 35 1k 39
RF PLL loop filter connection
39
VCODECAP
0.65
VSSCP
1k
VSSVCO
Capacitor connection for decoupling the VCO bias circuit Charge pump GND VCO 1.8V VCO GND RF GND LNA 1.8V
36 37 38 40 42
VSSCP VDDVCO VSSVCO RFSUB NRING
0 1.8 0 0 1.8
- 11 -
CXD2951GL-4
Pin No.
Symbol
Standard pin voltage [V]
Equivalent circuit
Description
IF1VCC
43
RFRREF
0.1
External resistor connection (LNA, RF mixer bias)
43 250 IF1GND
44 45 46
MIXGND LNASRC VDDCP
0 0 1.8
Mixer GND LNA GND Charge pump 1.8V
41
IF1VCC
41
LNAMAT
1.8
7k
LNA 1.8V
47
47
RFIN
—
10k LNASRC
RF input
48 49 50
MIXGND LNASRC MIXGND
0 0 0
IF1VCC
Mixer GND LNA GND Mixer GND Radio test input pin Normally leave open.
51
TESTINP
—
51 200
200 52
52
TESTINN
—
IF1GND
Radio test input pin Normally leave open.
- 12 -
CXD2951GL-4
Pin No.
Symbol
Standard pin voltage [V]
Equivalent circuit
Description
IF1VCC
53
TESTOUTP
—
53
Radio test output pin Capacitor and resistor connection Radio test output pin Capacitor and resistor connection
54
TESTOUTN
—
54
IF1GND
IF2VCC
55
TESTOUTD
—
55
Radio digital test output pin Normally leave open.
IF2GND
56 57 58 59
IF1VCC IF1GND IF2VCC IF2GND
1.8 0 1.8 0
IF1VCC
1st IF 1.8V 1st IF GND 2nd IF 1.8V 2nd IF GND
40k
60
VCOM
1.0
60 1k 50k
IF common voltage
IF1GND
- 13 -
CXD2951GL-4
Pin No.
Symbol
Standard pin voltage [V]
IF1VCC
Equivalent circuit
Description
61
RREF
1.1
6k 61
External resistor connection (VCO, PLL, IF block bias)
IF1GND
- 14 -
CXD2951GL-4
A/D Converter Operating Conditions
Item Supply voltage Operating temperature Applicable pin
*1
Symbol VAD Ta
Pin name EAVDAD*1 —
Min. 3.0 –40.0
Typ. 3.3
Max. 3.6 +85.0
Unit V
°C
EAVDAD (Pin 108)
A/D Converter Characteristics
(VAD = 3.0 to 3.6V, Ta = –40 to +85°C) Item Resolution Channel Differential linearity error (DLE) Integral linearity error (ILE) Sampling time Conversion time Reference input voltage (Top) Reference input voltage (Bottom) Analog input voltage Current consumption Applicable pins
*1 *2 *3
Symbol
Conditions
Min.
Typ.
Max. 10 4
Unit Bit Ch LSB LSB µs µs V V V mA
VAD = 3.0V, VRT = 3.0V, VRB = 0.3V TCXO = 18.414MHz VRT*1 VRB*2 VIN*3 VAD = 3.0V
–1.0 –2.0 3
+1.0 +2.0
11 2.0 0 VRB 1.6 VAD 0.7 VRT
EADVRT (Pin 107) EADVRB (Pin 102) EVIN[0:3] (Pins 103 to 106)
- 15 -
CXD2951GL-4
DC Characteristics
(IOVDD = 3.0 to 3.6V, CVDD = 1.62 to 1.98V, Ta = –40 to +85°C) Item Input voltage*1 High level Low level High level Low level High level Low level Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 RU RD IOPE TCXO = 18.414MHz, Ta = 25°C BKUPIOVDD = 3.6V, Ta = 25°C BKUPIOVDD = 3.6V, Ta = 85°C BKUPCVDD = 1.98V, Ta = 25°C BKUPCVDD = 1.98V, Ta = 85°C IOH = 4mA IOL = 4mA IOH = 8mA IOL = 8mA 48 40 60 0.2 0.2 7.5 50 1.0 1.0 15 120 2.4 0.4 110 100 Conditions Min. 2.0 –0.3 2.4 0.4 Typ. Max. 5.5 0.8 Unit V V V V V V kΩ kΩ mA µA µA µA µA
Output voltage*2
Output voltage*3 Pull-up resistor*4
Pull-down resistor*5 Current consumption during normal operation (via IOVDD, CVDD and VDD)*6 Current consumption during backup operation (via BKUPIOVDD)*7
ISTB1
Current consumption during backup operation (via BKUPCVDD)*8
ISTB2
Applicable pins
*1 *2 *3 *4 *5 *6
*7 *8
Pins 1 to 13, 20, 24 to 29, 64 to 66, 98, 119, 120 to 122, 133 to 148, 151, 152, 155 to 170, 173 Pins 1 to 13, 21 to 23, 97, 174 Pins 67 to 74, 77 to 80, 83 to 90, 124 to 130, 133 to 148, 155 to 170 Pins 24, 25, 28, 29, 152 Pins 1 to 13, 20, 26, 27, 133 to 148, 155 to 170, 173 Pins 15, 76, 96, 100, 108, 112, 118, 132, 154, 176 (3.3V) Pins 19, 31, 33, 37, 41, 42, 56, 58, 63, 82, 92, 114, 150, 172 (1.8V) Pin 118 Pin 114
- 16 -
CXD2951GL-4
AC Characteristics
1. External Expansion Bus (Read/32-bit mode)
(CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = –40 to +85°C) Item EXOE ↓ to address valid EXOE ↓ to EXCS ↓ Data setup Data hold Symbol Toea Toecs Tas Tah Min. Max. 3 1 15 0 Unit ns ns ns ns
EXOE Toea EA[19:0] Toecs
EXCS[1:0] Tas ED[31:0] Tah
- 17 -
CXD2951GL-4
2. External Expansion Bus (Write/32-bit mode (1-wait))
(CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = –40 to +85°C) Item EXCS ↓ to address valid EXCS ↓ to EXWE ↓ EXCS ↓ to EXWE ↑ EXCS ↓ to data valid Note) Tsys: ARM clock cycle
T1 T2 T3
Symbol Tcsfav Tcswef Tcswer Tcsd
Min.
Max. 2 Tsys – 1 Tsys × 3 – 2 15
Unit ns ns ns ns
EXCS[1:0] Tcsfav
EA[19:0] Tcswer Tcswef EXWE[3:0] Tcsd
ED[31:0]
- 18 -
CXD2951GL-4
Backup Mode
The backup mode is established by setting both EOSCEN and EXRS low. In this mode, the low power consumption can be achieved by stopping all oscillators except for RTC oscillator during the reset interval. Although all registers are initialized, the SRAM contents in backup area are held. In order to cancel this mode (reset cancellation), set EOSCEN high at first and then set EXRS high after the oscillation stabilization time and PLL lock time have passed. It needs 100ms or more. See Initialization section.
Normal operation Backup Reset Normal operation
IOVDD CVDD
BKUPIOVDD BKUPCVDD
OSC, PLL output EOSCEN EXRS Oscillation stabilization time PLL lock time (0.5ms max.)
ED[31:0], EPORT[12:0], ERXD0 ETXD0 EXCS[1:0], EXWE[3:0], EXOE EA[19:0], ECLKOUT
Power Off Power Off Power Off Power Off
Pull-down output Hi-Z output High output Low output
- 19 -
CXD2951GL-4
Initialization
The CXD2951GL-4 is initialized by setting the reset signal EXRS (Pin 151) to the low level. Note that internal RAM is not initialized by the operation. Satisfy the conditions shown below for the timing and others. 1. When turning the power on (Power-on reset)
VDD Power supply, EOSCEN (Pin 119) VDD [V] 100ms or more VDD/2 EXRS (Pin 151)
GND
Since there is a possibility that overcurrent may flow, please be sure to add power supply to the LSI before activate functional pin of this LSI. Additionally, the power supply both 3.3V and 1.8V should turn on simultaneously, and EOSCEN (Pin 119) should also rise simultaneously with the power supply turning on. EXRS (Pin 151) should rise 100ms or more after the power supply and EOSCEN rise. 2. Initialization during operation
Power supply, EOSCEN (Pin 119) VDD EXRS (Pin 151) VDD [V] 100µs or more VDD/2
GND
For initialization during operation, the interior circuit except internal RAM is initialized by setting the EXRS (Pin 151) signal to the low level for 100µs or more. Note that internal RAM is not also initialized by the operation. At this time, the EOSCEN (Pin 119) signal should keep the high level.
- 20 -
CXD2951GL-4
RTC crystal and TCXO
In order to operate CXD2951GL-4 appropriately, the recommended characteristics of RTC crystal and TCXO is shown below. Recommended characteristics of RTC crystal Operating temperature Nominal frequency Frequency tolerance Frequency temperature coefficient Frequency peak temperature Frequency aging –40 to +85°C 32.768kHz ±20ppm –0.04ppm/°C2 (Max.) +25 ± 5°C ±3ppm/year
Recommended characteristics of TCXO Operating temperature Frequency tolerance Frequency vs. temperature Frequency vs. supply voltage Frequency vs. load Frequency aging Recommended parts RTC crystal TCXO EPSON FC-255 NDK SNA3088B (NT5032 series) –40 to +85°C ±2.0ppm ±2.5ppm ±0.2ppm ±0.2ppm ±1ppm/year
- 21 -
CXD2951GL-4
Radio Block Operation
Radio block diagram shows RF section of the chip. The signal flow starts from the RFIN port (Pin 47). The signal is amplified and mixed down to the first Intermediate Frequency (IF) of 2MHz with cosine and sine wave quadrature mixers. Out of band images are filtered out and the signal is again mixed down to the 2nd IF of 1MHz with another set of quadrature mixers. The complex signal becomes real with the addition of real and imaginary components. The image of the 2nd IF mixing is removed with the last Band Pass Filter (BPF). The real signal is then amplified one last time and transferred to digital baseband processing unit.
RF Digital
Reset CLK
RF Analog
BPF A/D Converter Data RFIN 1st IF (2MHz) BPF RF Local (1573MHz) VCO IF Local (3MHz) VCO BUF PLLCLK BPF Baseband 2nd IF (1MHz)
PLL BIAS
PLL TEST
Enable
LPFRF
LPFIF
Radio Block Diagram
To have constant internal frequencies for mixing and other purposes, the supplied TCXO frequency is counted by a Real Time Clock (RTC), and the internal PLL divider is automatically set to provide correct frequency for RF mixing and baseband operation. The loop filters (RF and IF) are externally connected. Use parts that satisfy the required tolerance.
- 22 -
CXD2951GL-4
Radio Characteristics
DC Characteristics
(VDD = 1.8V, Ta = 25°C) Item Supply current 1 Supply current 2
*1
Symbol IDD IPS
Conditions Active mode*1 Power save mode*1
Min. 13.5 —
Typ. 17 0.1
Max. 20.5 1.5
Unit mA µA
Applicable pins 31, 33, 37, 41, 42, 56, 58
AC Characteristics
(VDD = 1.8V, Ta = 25°C) Item Total gain Image rejection ratio 2nd IF filter 2.5MHz 2nd IF filter 4MHz Symbol G IMRR Fc Fa Conditions Before the A/D converter Image frequency = 1571.328MHz @2.5MHz Normalized at 1.023MHz @4MHz Normalized at 1.023MHz Min. 90 — –6 — Typ. 100 –35 0 –25 Max. — –15 4 –15 Unit dB dB dB dB
Note) Including the 50Ω matching circuit
Design Measurement Results
(VDD = 1.8V, Ta = 25°C) Item Total NF IIP3 P-1dB input S11 Lock up time C/N 100K Local leak Symbol NF IIP3 P1dB S11 LUT C/N Leak Measure the interval between reset input and IF output. TCXO = 18.414MHz Measure at RF input. Conditions Before the 2nd IF mixer Before the A/D converter Before the A/D converter Min. — — — — — — — Typ. 8 –90 –100 –15 2.5 –70 –65 Max. — — — — — — — Unit dB dBm dBm dB ms dBc/Hz dBm
Note) Including the 50Ω matching circuit
- 23 -
CXD2951GL-4
Radio Supplement Materials (Example of Representative Characteristics)
IDD
24 22 20 IDD [mA] 18 16 14 12 10 1.6 VDD = 1.8V Ta = 25˚C 10 5 0 Output level [dBm] –5 –10 –15 –20 –25 –30 –35 1.8 VDD [V] 2.0 –40 –135 –130 –125 –120 –115 –110 –105 –100 –95 –90 –85 Input level [dBm] VDD = 1.8V Ta = 25˚C
Input/output characteristic
IIP3
10 5 0 –60 Output level [dBm] –5 –10 –15 –20 –25 –80 –30 –35 VDD = 1.8V Ta = 25˚C –85 –90 10 C/N [dBc/Hz] –65 –70 –75 –50 –55
C/N
VDD = 1.8V Ta = 25˚C
–40 –130 –125 –120 –115 –110 –105 –100 –95 –90 –85 –80 –75 –70 Input level [dBm]
100 Offset frequency [kHz]
1000
Image rejection ratio
–20 VDD = 1.8V Ta = 25˚C Response [dB] 5 0 –5 –10 –15 –20 –25 –30 –45 –35 –50 0 0.5 1.0 1.5 2.0 2.5 3.0 IF frequency [MHz]
IF filter response (simulation)
–25
–30 IMRR [dB]
–35
–40
–40 1.570 1.571 1.572 1.573 1.574 1.575 1.576 1.577 1.578 1.579 1.580 1.581 Frequency [GHz] Filter characteristic represented by RF frequency as x-axis (Normalized at 1.023MHz)
- 24 -
CXD2951GL-4
RFIN input impedance
+j50 +j25 +j100
+j10
0
25
50
100
∞
–j10
2GHz 1.8GHz 1.6GHz –j25 1.4GHz 1GHz –j100
1.2GHz –j50
- 25 -
L046 56nH
10P L040 1µH 1 XRESET BKUPIOVDD_3.3V IC006 R1160N181B 1 IC005 R1124N181D L045 1µH C150 10µ BKUPCVDD_1.8V R013 470k C121 0.1µ 1 VDD IC004 2 GND R3112Q291A CD 3 C045 0.1µ C048 2.2µ CE 3 VDD 4 C066 10µ C162 10µ OUT 4 C059 0.1µ 1 VOUT 5 NC 2 GND 2 GND ECO 4 3 CE VDD VOUT 5 2 GND 3 Reset In Vcc 4 IC003 MAX6364 OUT 5 BATT 6
CN012
TXD0
1
R001 22
R004 10k
R005 10k
RXD0
2
R002 22
RXD1
3
R063 22
JS040 0
L003 10µH
R202 XX
NMEA/Orig
4
UPDATE
5
R062 22
IC002 XX
RESET/POWER DOWN
6
R205 47k
DGND
7
L002 22µH
VDD (3.3V/5V)
8
BATT
9
C004 22µ
1 VOUT 5 NC C161 2 GND 10µ 4 3 VDD CE
C013 10µ
C046 0.1µ
Application Circuit
AGND
10
JS041 0
R1124N331D
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility forany problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
JS025 0
SYSTEM_RESET
C069 0.1µ
C072 0.1µ
C077 0.1µ
C079 0.1µ
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30
B16 C17 E15 B17 D16 D17 F15 E16 G14 E17 G15 F16 H14 F17 H15 G16 J14 G17 J15 H16 K14 H17 J16 J17 K16 K17 L16 M17 K15 M16 L14 N17 L15 N16 M15 P17 N15 P16 P15 R17 R15 R16 T15 T17
ED31
175 IOVSS7
174 ETXD0
173 ERXD0
172 CVDD6
169 ED1
167 ED3
166 ED4
164 ED6
161 ED9
160 ED10
158 ED12
157 ED13
176 IOVDD6
168 ED2
159 ED11
156 ED14
153 IOVSS6
152 ETESTXRS
149 CVSS5
171 CVSS6
154 IOVDD5
150 CVDD5
148 ED16
145 ED19
144 ED20
170 ED0
165 ED5
163 ED7
162 ED8
151 EXRS
146 ED18
137 ED27
136 ED28
134 ED30
155 ED15
141 ED23
147 ED17
140 ED24
143 ED21
142 ED22
139 ED25
138 ED26
135 ED29
133 ED31
C088 0.1µ T16 U16 T14 U15 R14 U14 R13 T12 T13 U13 P11 R11 R12 U12 C089 0.1µ R203 22 C085 12p C086 12p C090 0.1µ X002
A16 1 EPORT0 EPORT1 EPORT2 EPORT3 EPORT4 EPORT5 EPORT6 EPORT7 EPORT8 123 IOVSS4 ECLKS2 ECLKS1 ECLKS0 EOSCEN BKUPIOVDD T11 BKUPIOVSS U11 ECCKO ECCKI BKUPCVDD T9 BKUPCVSS U9 IOVDD7 ETEST4 ETEST3 IOVSS8 EAVDAD EADVRT EVIN3 EVIN2 EVIN1 EVIN0 EADVRB EAVSAD EAVDPLL 100 99 98 97 96 95 94 93 92 91 90 89 EAVSPLL EXROMI ECLKOUT IOVDD3 IOVSS3 ECLKO ECLKI CVDD4 CVSS4 EA0 EA1 P7 T7 R7 R6 U7 T6 U6 R5 T5 U5 U4 R4 T4 T3 U3 R3 U2 EA15 EA18 74 EA12 77 EA11 78 EA10 79 EA9 80 EA8 83 EA7 84 EA6 85 EA5 86 EA4 87 EA3 88 EA2 67 EA19 68 EA18 69 EA17 70 EA16 71 EA15 72 EA14 73 EA13 75 IOVSS2 76 IOVDD2 81 CVSS3 82 CVDD3 C094 0.1µ CVDD_1.8V EA9 EA12 ED9 R201 XX C093 0.1µ C126 0.1µ EA16 EA19 C092 0.1µ C125 0.1µ ED24 R8 EA17 U8 H5 NC H6 A15 H7 A18 H8 DQ24 H9 Vcc ED22 L024 1µH R028 XX ED23 R025 100k EA8 EA11 J1 DQ22 J2 DQ23 J3 A6 J4 A9 J5 NC J6 A14 J7 A17 J8 Vcc J9 DQ9 K2 Vss K3 A7 K4 A10 K5 NC K6 A13 K7 A16 K8 A19 P8 T8 P9 R9 P10 U10 T10 122 121 120 119 118 117 116 115 114 113 112 111 124 EXCS0 125 EXCS1 126 EXOE 127 EXWE3 128 EXWE2 129 EXWE1 130 EXWE0 131 IOVSS5 B15 2 A15 3 C15 4 B14 5 A14 6 C14 7 B13 8 A13 9 R204 22 C13 10 EPORT9 B12 11 EPORT10 A12 12 EPORT11 C067 0.1µ A11 14 IOVSS1 D11 15 IOVDD1 R020 1M C11 17 EXTCXO A10 18 CVSS1 D10 19 CVDD1 B10 20 TRST C10 21 ETESTTINT A9 22 TDO C9 23 ETESTTDO B9 24 TDI D9 25 ETESTTDI A8 26 TCK C8 27 ETESTTCK B8 28 TMS C139 0.001µ B7 30 RADIOSUB A6 31 VDDPLL A7 32 VSSPLL B6 33 VDDCP A5 34 LPFIF B5 35 LPFRF C7 36 VSSCP C6 37 VDDVCO D7 38 VSSVCO C5 39 VCODECAP L004 2.7nH A2 40 RFSUB C4 41 LNAMAT JS037 XX B4 43 RFRREF B3 44 MIXGND JS038 0 45 LNASRC 46 MIXGND 47 RFIN 48 MIXGND 49 LNASRC 50 MIXGND 51 TESTINP 52 TESTINN 53 TESTOUTP 54 TESTOUTN 55 TESTOUTD 56 IF1VCC 57 IF1GND 58 IF2VCC 60 VCOM 61 RREF 62 CVSS2 63 CVDD2 64 ETEST0 65 ETSET1 59 IF2GND 66 ETEST2 A3 42 NRING 101 102 103 C153 XX D8 29 ETESTTMS 104 105 106 107 108 109 110 C068 0.1µ B11 16 ETCXO C060 0.01µ C12 13 EPORT12
132 IOVDD4
Note) The following should be guaranteed within operating temperature. • R tolerance: ±5% or less • C tolerance: ±20% or less • L tolerance: ±20% or less
ED7
ED8
ED6
ED5 EA13 EA10 A8 NC EA14 NC NC Vcc Vss A11 DQ7 DQ8 A12 DQ6 Vss NC DQ5 DQ26 DQ25 DQ21 DQ27 DQ11 DQ10
ED26
ED25
ED21
ED27
ED11
X001
DQ4
L051 56nH
IC020 CXD2951GL-4
R057 100k R056 100k
H4 H3 H2 H1 G9 G8 G7 G6 G5 G4 G3 G2 G1 F9 F8 F7 F6 F5 F4 F3 F2
ED10
ED4
A4
A1
NC
XWE
NC
XCE
Vcc
A5
A2
ACC
NC
DW/XW
Vss
DQ30
DQ17
DQ1
DQ0
A3
XWP
NC
CL001
CL002
CL005
C147 0.01µ EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 EA3 C146 0.001µ R200 56k EA2
A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 EA6 EA3 EA7 EA4 EA5
CL003
CL004
ED30
ED17
DE1
R206 1M C148 XX C166 100p C167 100p
R207 1M
C076 0.1µ
C082 0.1µ
C083 0.1µ
C129 0.1µ L035 56nH C154 0.1µ L036 56nH C158 0.1µ
C134 0.001µ C132 39p
L044 4.7nH L034 15nH IC022 1 2 L050 3.9nH 3 C131 100p NJG1107KB2 6 5 4 L018 27nH C163 XX C157 XX L048 12nH SWF001
C159 0.001µ C155 1p
L043 3.3nH L042 15nH IC024 1 2 3 C156 100p NJG1107KB2 6 5 4 L023 82nH L041 12nH TP001
CXD2951GL-4
Note) If a Flash ROM is used, the programs which are GPS software, Flash updater etc. required for desired operation should be written into a Flash ROM in advance.
ED0
XOE
- 26 C3 B2 C2 C1 D2 D1 E3 E2 F3 F2 D3 E1 G1 F1 G2 G3 G4 H1 J1 H2 H3 H4 J3 J2 J4 K1 K3 K2 K4 L2 L1 M1 L3 N3 M2 P3 N1 P1 N2 T2 P2 T1 R2 R1
C124 0.1µ
C122 0.1µ
DQ20 F1 DQ12 E9 DQ28 E8 Vss E7 NC E6 NC E5 DQ2 E4 DQ18 E3 DQ19 E2 DQ3 E1
ED20 ED12 ED28
JS039 0
C140 0.068µ
R197 470
C141 3300p
ED2 ED18 ED19 ED3
C142 680p
R198 33k
C143 68p
C149 0.01µ
C144 0.01µ
IC021 MBM29PL320
DQ13 D9 DQ29 D8 DQ14 D7 DQ31/A-1 D6 NC D5 A0 D4 DQ16 D3 Vss D2 Vcc D1 Vcc C9 DQ15 C8 EA2
ED13 ED29 ED14 ED31
L039 12nH
C145 10p
ED16
R199 2k
C127 0.1µ
ED15 C128 0.1µ
CXD2951GL-4
Radio Block Application Circuit
C8 27 ETESTTCK B8 28 TMS C139 0.001µ JS039 0 C140 0.068µ C141 3300p C142 680p C143 68p R197 470 C153 XX D8 29 ETESTTMS B7 30 RADIOSUB A6 31 VDDPLL A7 32 VSSPLL B6 33 VDDCP A5 34 LPFIF B5 35 LPFRF R198 33k C144 0.01µ L004 2.7nH C7 36 VSSCP C6 37 VDDVCO D7 38 VSSVCO C5 39 VCODECAP L039 12nH C145 10p A2 40 RFSUB C4 41 LNAMAT JS037 XX R199 2k JS038 0 A3 42 NRING B4 43 RFRREF B3 44 MIXGND 54 TESTOUTN 55 TESTOUTD 53 TESTOUTP 52 TESTINN 51 TESTINP 45 LNASRC 49 LNASRC 46 MIXGND 48 MIXGND 50 MIXGND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility forany problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
C149 0.01µ
64 ETEST0
65 ETSET1
59 IF2GND
66 ETEST2
57 IF1GND
75 IOVSS2
56 IF1VCC
58 IF2VCC
63 CVDD2
60 VCOM
62 CVSS2
61 RREF
76 IOVDD2
77 EA11
78 EA10
67 EA19
68 EA18
69 EA17
70 EA16
71 EA15
72 EA14
73 EA13
74 EA12
47 RFIN
79 EA9 EA9 6 5 4
C3 B2 C2 C1 D2 D1 E3 E2 F3 F2 D3 E1 G1 F1 G2 G3 G4 H1 J1 H2 H3 H4 J3 J2 J4 K1 K3 K2 K4 L2 L1 M1 L3 N3 M2 P3
CL001
CL002
CL005
C147 0.01µ EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 C146 0.001µ R200 56k EA8
CL003
R206 1M C166 100p
R207 1M C167 100p
CL004
C148 XX
C076 0.1µ
C082 0.1µ
C154 0.1µ
L035 56nH
C134 0.001µ C132 39p
L044 4.7nH L034 15nH IC022 1 2 NJG1107KB2
L050 3.9nH
3 C131 100p
Enlarged view of the previous page
Parts ID C139 to C147, C149, C166, C167 L004, L039, L050 R197 to R200 R206, R207
Parts name MURATA GRM36CH series
Remarks Tolerance: ±5% C145: Self-resonant frequency 2.0GHz or more Tolerance: ±5% L050: Self-resonant frequency 2.0GHz or more Tolerance: ±1% Tolerance: ±5%
TAIYO YUDEN HK1005 series KOA RK73H series KOA RK73B series
Note) 1. Always use matching circuit for the RF amplifier input pin (Pin 47), and match at 1.57542GHz. 2. The external elements should be placed as close to the chip as possible.
- 27 -
80 EA8
CXD2951GL-4
Package Outline
(Unit: mm)
183PIN VFLGA (PLASTIC)
0.1 S A 10.0 X
S
1.0MAX 0.1MAX
10.0
B
0.1
x4 0.08 DETAIL X
3-
0.8
0.5 A
U T R P N M L K J H G F E D C B A
183-φ0.27 ± 0.04 φ0.05 M S AB 0.5
B
(0.5)
0.8
C0
.3
1 2 3 4 5 6 7 8 9 101112 13 14151617
0.8 (0.5) 1.0
1.0
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VFLGA-183P-051 P-VFLGA183-10X10-0.5
ORGANIC SUBSTRATE
TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.3g
- 28 -
S
Sony Corporation
0.08
S
S
PIN 1 INDEX
0.2
工商网监
湘ICP备2023018690号
