CXD3406GA

CXD3406GA Timing Generator and Signal Processor for Frame Readout CCD Image Sensor Description The CXD3406GA is a timing generator and CCD signal processor IC for the ICX252/262 CCD image sensor. Features • Timing generator functions • Horizontal drive frequency 12 to 18MHz (Base oscillation frequency 24 to 36MHz) • Supports frame readout/draft (sextuple speed)/ AF (Auto focus drive) • High-speed/low-speed shutter function • Horizontal and vertical drivers for CCD image sensor • CCD signal processor functions • Correlated double sampling • Programmable gain amplifier (PGA) allows gain adjustment over a wide range (–6 to +42dB) • 10-bit A/D converter • Chip Scale Package (CSP): CSP allows vast reduction in the CCD camera block footprint Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX252 (1/1.8", 3240K pixels) ICX262 (1/1.8", 3240K pixels) 96 pin LFLGA (Plastic) Absolute Maximum Ratings • Supply voltage VSS – 0.3 to +7.0 VDDa, VDDb, VDDc, VDDd VDDe, VDDf, VDDg VSS – 0.3 to +4.0 VL –10.0 to VSS VH VL – 0.3 to +26.0 • Input voltage (analog) VIN VSS – 0.3 to VDD + 0.3 • Input voltage (digital) VI • Output voltage VO1 VO2 VO3 • Operating temperature Topr • Storage temperature Tstg VSS – 0.3 to VDD + 0.3 VSS – 0.3 to VDD + 0.3 VL – 0.3 to VSS + 0.3 VL – 0.3 to VH + 0.3 –20 to +75 –55 to +125 V V V V V V V V V °C °C Recommended Operating Conditions • Supply voltage VDDb 3.0 to 5.5 VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 VDDe, VDDf, VDDg 3.0 to 3.6 • Operating temperature Topr –20 to +75 V V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00Z02A26 CXD3406GA Block Diagram TEST3 TEST4 TEST5 DVDD1 DVDD2 DVSS3 DVSS1 A1 A2 C7 D8 D7 B8 B6 B9 A6 C5 A3 A4 B4 A5 C4 B5 E2 F2 F3 E3 F1 C4 C8 AVDD5 A9 AVSS6 A8 C7 B7 C8 A7 C9 C6 CCDIN C9 AVDD1 E9 AVDD2 E8 AVSS1 D9 AVSS2 E7 XSHPI F9 XSHDI F8 PBLKI F7 XSHP G9 XSHD G8 PBLK G7 XRS H7 VDD4 H8 VDD2 K7 RG K8 VSS2 K9 VDD3 H9 H1 J8 H2 J9 VSS3 J7 ID N9 WEN M9 L2 VH M5 VM L4 VL M6 Selector SSG L8 SSGSL V Driver Serial Port Register SSI1 M1 SCK1 N1 SEN1 Latch 1/2 Selector Pulse Generator CDS PGA ADC Latch DAC Serial Port Register B3 B2 B1 D0 (LSB) D1 D2 DVSS2 C3 D3 C2 D4 C1 D5 D3 D6 D2 D7 D1 D8 E1 D9 (MSB) ADCLKI CLPOBI CLPDMI VSS4 ADCLK CLPOB CLPDM VSS5 OSCI OSCO CKI CKO MCKO G1 G2 G3 L3 H1 H2 H3 J3 L1 K1 J1 J2 K2 N8 SNCSL AVDD3 AVDD4 AVSS3 AVSS4 AVSS5 SCK2 Preblanking Dummy Pixel Auto Zero SEN2 SSI2 NC NC C3 C2 C1 Black Level Auto Zero M8 M3 M7 TEST1 TEST2 RST L5 N5 M4 L6 V1A V1B V3A V2 N6 N4 N7 SUB V3B V4 N2 M2 HD VD L9 VDD1 K3 L7 VDD5 VSS1 N3 VSS6 –2– CXD3406GA Pin Configuration (Top View) A B C D E F G H J K L M N NC D2 D5 D8 D9 DVSS2 ADCLKI ADCLK CKI OSCO OSCI SCK1 SEN1 1 NC D1 D4 D7 DVDD1 DVSS3 CLPOBI CLPOB CKO MCKO SSI1 VD HD 2 SCK2 D0 D3 D6 DVSS1 DVDD2 CLPDMI CLPDM VSS5 VDD5 VSS4 TEST1 VSS6 3 SSI2 SEN2 TEST4 TEST3 TEST5 AVSS5 AVSS4 AVDD4 C9 C8 C7 C3 C1 AVSS2 PBLKI PBLK XRS VSS3 VDD2 AVSS6 AVDD3 C4 C2 AVDD2 XSHDI XSHD VDD4 H1 RG SSGSL RST SNCSL 8 AVDD5 AVSS3 CCDIN AVSS1 AVDD1 XSHPI XSHP VDD3 H2 VSS2 VDD1 WEN ID 9 VM V2 V4 4 V1A VH V1B 5 V3A VL V3B 6 VSS1 TEST2 SUB 7 –3– CXD3406GA Pin Description Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 D8 D9 E1 E2 Symbol NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 D6 C1 C2 AVSS1 D9 DVDD1 I/O — — I I I — — — — O O O I I — — — — O O O I — — — — I O O O — — — O — No connected. No connected. CCD signal processor block serial interface clock input. (Schmitt trigger) CCD signal processor block serial interface data input. (Schmitt trigger) CCD signal processor block test input 3. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. CCD signal processor block analog GND. CCD signal processor block analog power supply. ADC output. ADC output. ADC output (LSB). CCD signal processor block serial interface enable input. (Schmitt trigger) CCD signal processor block test input 5. Connect to DVDD. CCD signal processor block analog power supply. Capacitor connection. CCD signal processor block analog power supply. CCD signal processor block analog GND. ADC output. ADC output. ADC output. CCD signal processor block test input 4. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. Capacitor connection. Capacitor connection. CCD output signal input. ADC output. ADC output. ADC output. Capacitor connection. Capacitor connection. CCD signal processor block analog GND. ADC output (MSB). CCD signal processor block digital power supply. (Power supply for ADC) –4– Description CXD3406GA Pin No. E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 J9 K1 K2 K3 K7 K8 K9 L1 Symbol DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI CKO VSS5 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI I/O — — — — — — — I I I I I I O O O O O O O — — I O — — O O O O — — O — I Description CCD signal processor block digital GND. (GND for ADC) CCD signal processor block analog GND. CCD signal processor block analog power supply. CCD signal processor block analog power supply. CCD signal processor block digital GND. CCD signal processor block digital GND. CCD signal processor block digital power supply. Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger) CCD data level sample-and-hold pulse input. (Schmitt trigger) CCD precharge level sample-and-hold pulse input. (Schmitt trigger) Clock input for analog/digital conversion. (Schmitt trigger) CCD optical black signal clamp pulse input. (Schmitt trigger) CCD dummy signal clamp pulse input. (Schmitt trigger) Pulse output for horizontal and vertical blanking period pulse cleaning. CCD data level sample-and-hold pulse output. CCD precharge level sample-and-hold pulse output. Clock output for analog/digital conversion. CCD optical black signal clamp pulse output. CCD dummy signal clamp pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Timing generator block digital power supply. (Power supply for CDS block) Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2) Inverter input. Inverter output. Timing generator block digital GND. Timing generator block digital GND. CCD horizontal register clock output. CCD horizontal register clock output. Inverter output for oscillation. When not used, leave open or connect a capacitor. System clock output for signal processor IC. Timing generator block digital power supply. (Power supply for common logic block) Timing generator block digital power supply. (Power supply for RG) CCD reset gate pulse output. Timing generator block digital GND. Inverter input for oscillation. When not used, fix to low. –5– CXD3406GA Pin No. L2 L3 L4 L5 L6 L7 L8 L9 M1 M2 M3 M4 M5 M6 M7 Symbol SSI1 VSS4 VM V1A V3A VSS1 SSGSL VDD1 SCK1 VD TEST1 V2 VH VL TEST2 I/O I — — O O — I — I I/O I O — — I Description Timing generator block serial interface data input. Schmitt trigger input/No protective diode on power supply side. Timing generator block digital GND. Timing generator block digital GND. (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. Timing generator block digital GND. Internal SSG enable. High: Internal SSG valid, Low: External SYNC valid (With pull-down resistor) Timing generator block digital power supply.(Power supply for common logic block) Timing generator block serial interface clock input. Schmitt trigger input/No protective diode on power supply side. Vertical sync signal input/output. Timing generator block test input 1. Normally fix to GND. CCD vertical register clock output. Timing generator block 15.0V power supply. (Power supply for vertical driver) Timing generator block –7.5V power supply. (Power supply for vertical driver) Timing generator block test input 2. Normally fix to GND. (With pull-down resistor) (With pull-down resistor) M8 RST I Timing generator block reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side Memory write timing pulse output. Timing generator block serial interface strobe input. Schmitt trigger input/No protective diode on power supply side Horizontal sync signal input/output. Timing generator block digital GND. CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. CCD electronic shutter pulse output. Control input used to switch sync system. High: CKI sync, Low: MCKO sync Vertical direction line identification pulse output. (With pull-down resistor) M9 N1 N2 N3 N4 N5 N6 N7 N8 N9 WEN SEN1 HD VSS6 V4 V1B V3B SUB SNCSL ID O I I/O — O O O O I O –6– CXD3406GA Electrical Characteristics Timing Generator Block Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 Input voltage 1∗1 Input voltage 2∗2 Input voltage 3∗3 Input voltage 4∗4 Pins VDD2 VDD3 VDD4 VDD1, VDD5 RST SSI1, SCK1, SEN1 TEST1, TEST2 SNCSL, SSGSL Symbol VDDa VDDb VDDc VDDd Vi + Vi – Vi + Vi – VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd 0.8VDDd 0.2VDDd 0.7VDDd 0.2VDDd 0.7VDDd 0.3VDDd 0.8VDDd 0.2VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.5 3.6 3.6 0.2VDDd Unit V V V V V V V V V V V V V V V V V V V V V 0.4 VDDd – 0.8 0.4 VDDd – 0.8 0.4 VDDd – 0.8 0.4 10.0 –5.0 5.0 –7.2 5.4 –4.0 V V V V V V V mA mA mA mA mA mA Input/output voltage VD, HD Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 H1, H2 RG Feed current where IOH = –1.2mA VDDd – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –22.0mA VDDb – 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = –3.3mA VDDa – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = –8.25V V1A/B, V2, V3A/B, V4 = –0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = –8.25V SUB = 14.75V VDDc – 0.8 0.4 0.4 0.4 XSHP, XSHD, VOH4 XRS, PBLK, CLPOB, CLPDM, VOL4 ADCLK CKO MCKO ID, WEN VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL IOM1 IOM2 IOH IOSL IOSH Output current 1 V1A, V1B, V3A, V3B, V2, V4 Output current 2 ∗1 ∗2 ∗3 ∗4 SUB This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC. These input pins are schmitt trigger inputs. These input pins are with pull-down resistor in the IC. These input pins are with pull-down resistor in the IC and they do not have protective diode of the power supply side in the IC. Note) The above table indicates the condition for 3.3V drive. –7– CXD3406GA Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL Conditions (Within the recommended operating conditions) Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Max. Unit V V V V 0.4 500k 20 2M 5M 50 V Ω MHz OSCO Feed current where IOH = –3.6mA Pull-in current where IOL = 2.4mA VIN = VDDd or VSS VDDd – 0.8 OSCI, OSCO RFB OSCI, OSCO f Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = –7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –8– CXD3406GA Switching Waveforms TTMH 90% TTHM VH 90% V1A (V1B, V3A, V3B) TTLM 10% 90% 10% 90% TTML VM 10% 10% VL TTLM 90% V2 (V4) 10% 90% TTML VM 10% VL TTLH 90% 90% TTHL VH SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –9– Measurement Circuit Serial interface data CKI VD HD C6 C4 C5 C5 C6 C6 +3.3V +15.0V –7.5V N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7 H2 RG H1 CKI XRS VSS6 VSS2 VDD5 VSS3 VSS5 CKO VDD3 SSI1 VDD2 OSCI VDD4 VSS4 XSHP MCKO OSCO CLPDM CLPOB XSHD PBLK CLPDMI G3 CLPOBI G2 ADCLK XSHPI XSHDI PBLKI DVDD2 DVSS3 H1 F9 F8 F7 F3 F2 ADCLKI G1 AVDD1 AVSS1 AVSS2 CXD3406GA DVSS2 DVSS1 DVDD1 AVDD2 C2 C1 D6 D7 D8 CCDIN C4 C3 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVSS3 AVDD3 D5 D4 D3 TEST4 AVSS5 NC NC SCK2 SSI2 TEST3 AVSS4 C9 E9 D9 E7 F1 E3 E2 E8 D8 D7 D3 D2 D1 C9 C8 C7 M4 V2 M5 VH M6 VL E1 D9 L8 SSGSL VDD1 L9 M1 SCK1 M2 VD M3 TEST1 N4 V4 N5 V1B N6 V3B M7 TEST2 M8 RST M9 WEN N1 SEN1 N2 HD L4 VM V1A V3A L5 L6 N7 SUB C3 N8 SNCSL N9 ID L7 VSS1 R1 C2 C2 R1 R1 C1 C2 C1 C2 C2 C2 C1 C2 – 10 – C3 820pF C4 30pF C5 215pF C6 10pF C2 C2 C2 C2 R1 C1 C2 C2 C1 R1 C1 C2 C2 R2 R1 A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6 CXD3406GA C1 R1 3300pF 30Ω C2 R2 560pF 10Ω CXD3406GA AC Characteristics AC characteristics between the serial interface clocks 0.8VDDd SSI1 SCK1 SEN1 SEN1 ts2 0.2VDDd 0.8VDDd ts1 0.2VDDd ts3 0.8VDDd th1 (Within the recommended operating conditions) Symbol Definition SSI1 setup time, activated by the rising edge of SCK1 SSI1 hold time, activated by the rising edge of SCK1 SCK1 setup time, activated by the rising edge of SEN1 SEN1 setup time, activated by the rising edge of SCK1 Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns ts1 th1 ts2 ts3 Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD V1A 0.2VDDd ts1 0.8VDDd SEN1 th1 0.2VDDd ∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN1 setup time, activated by the falling edge of HD SEN1 hold time, activated by the falling edge of HD – 11 – Min. 0 102 Typ. Max. Unit ns µs ts1 th1 CXD3406GA Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD HD 0.2VDDd ts1 SEN1 0.8VDDd th1 0.2VDDd ∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol Definition SEN1 setup time, activated by the falling edge of VD SEN1 hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns ts1 th1 Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3406GA at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3406GA and controlled at the rising edge of SEN1. See "Description of Operation". SEN1 0.8VDDd Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns tpdPULSE Output signal delay, activated by the rising edge of SEN1 – 12 – CXD3406GA RST loading characteristics RST 0.8VDDd 0.2VDDd tw1 (Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns tw1 VD and HD loading characteristics VD, HD 0.2VDDd ts1 th1 0.2VDDd MCKO 0.8VDDd MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition VD and HD setup time, activated by the rising edge of MCKO VD and HD hold time, activated by the rising edge of MCKO Min. 20 5 Typ. Max. Unit ns ns ts1 th1 Output variation characteristics MCKO 0.8VDDd WEN, ID tpd1 WEN and ID load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 20 Typ. Max. 60 Unit ns – 13 – CXD3406GA CCD Signal Processor Block Electrical Characteristics DC Characteristics Item Pins Symbol VDDe VDDf (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Conditions Min. 3.0 3.0 Typ. Max. Unit 3.3 3.3 3.6 3.6 V V Supply voltage 1 DVDD1 Supply voltage 2 DVDD2 AVDD1, AVDD2, Supply voltage 3 AVDD3, AVDD4, AVDD5 Analog input capacitance CCDIN VDDg 3.0 3.3 3.6 V CIN 15 1.8 pF V Input voltage SCK2, SSI2, VI + SEN2, TEST3, TEST4, XSHDI, XSHPI, ADCLKI, VI – CLPOBI, CLPDMI, PBLKI ADCLKI VOH VOL Feed current where IOH = –2.0mA Pull-in current where IOL = 2.0mA VDDe – 0.9 1.1 V A/D clock duty 50 % V 0.4 V Output voltage D0 to D9 Analog Characteristics Item CCDIN input voltage amplitude PGA maximum gain PGA minimum gain ADC resolution ADC maximum conversion rate ADC integral non-linearity error ADC differential non-linearity error Signal-to-noise ratio CCDIN input voltage clamp level CCD optical black signal clamp level Fc max EL ED SNR∗1 CLP OB Symbol VIN Gmax Gmin (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Conditions PGA gain = 0dB, output full scale PGA gain setting data = "3FFh" PGA gain setting data = "000h" Min. Typ. Max. Unit 900 42 –6 10 18 PGA gain = 0dB PGA gain = 0dB CCDIN input connected to GND via a coupling capacitor PGA gain = 0dB 1100 mV dB dB bit MHz ±1.0 ±5.0 LSB ±0.5 ±1.0 LSB 62 1.5 OBLVL = "8h" PGA gain = 0dB 32 dB V LSB ∗1 SNR = 20 log (full-scale voltage/rms noise) – 14 – CXD3406GA AC Characteristics AC characteristics between the serial interface clocks 0.8VDD SSI2 SCK2 SEN2 SEN2 ts2 0.2VDD 0.8VDD ts1 0.2VDD ts3 0.8VDD th1 ∗ The setting values are reflected to the operation 5 or 6 ADCLKI clocks after the serial data is loaded at the rise of SEN2. (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol Definition SCK2 clock period SSI2 setup time, activated by the rise of SCK2 SSI2 hold time, activated by the rise of SCK2 SCK2 setup time, activated by the rise of SEN2 SEN2 setup time, activated by the rise of SCK2 Min. 100 30 30 30 30 Typ. Max. Unit ns ns ns ns ns tp1 ts1 th1 ts2 ts3 – 15 – CXD3406GA CDS/ADC Timing Chart N CCDIN N+1 N+2 N+3 XSHPI XSHDI tw1 ADCLKI DL D0 to D9 N – 10 N–9 N–8 N–7 ∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0". (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol Definition ADCLKI clock period ADCLKI clock duty DL Data latency Min. 54 50 9 Typ. Max. Unit ns % clocks tw1 Preblanking Timing Chart PBLKI 11 Clocks ADCLKI 11 Clocks D0 to D9 All "0" – 16 – CXD3406GA Description of Operation Pulses output from the CXD3406GA's timing generator block are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on page 19 and thereafter. Pin Status Table Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 Symbol NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 CAM SLP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — STB RST Pin No. D3 D7 D8 D9 E1 E2 E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 – 17 – Symbol D6 C1 C2 AVSS1 D9 DVDD1 DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI ACT ACT ACT ACT ACT ACT ACT ACT ACT L L L L L L L — — ACT ACT CAM SLP — — — — — — — — — — — — — — — — — — — L L L L L L L H ACT ACT ACT H H ACT STB RST CXD3406GA Pin No. J2 J3 J7 J8 J9 K1 K2 K3 K7 K8 K9 L1 L2 L3 L4 L5 L6 L7 Symbol CKO VSS5 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI SSI1 VSS4 VM V1A V3A VSS1 CAM ACT SLP ACT — — STB L RST ACT Pin No. L9 M1 M2 Symbol VDD1 SCK1 VD∗1 TEST1 V2 VH VL TEST2 RST WEN SEN1 HD∗1 VSS6 V4 V1B V3B SUB SNCSL ID CAM SLP — STB RST ACT ACT ACT L — ACT L DIS H ACT ACT ACT ACT L L ACT ACT — — L L ACT L ACT ACT ACT ACT M3 M4 M5 M6 M7 M8 ACT VM — — — VM VM ACT ACT ACT ACT ACT L ACT L — ACT L ACT L L L DIS H ACT L — L ACT M9 N1 ACT ACT ACT ACT — — ACT ACT ACT DIS N2 N3 N4 N5 ACT ACT ACT ACT ACT ACT VM VH VH VH ACT L VM VH VH VH ACT L VL VM VL VL ACT L ACT ACT VH VH — VH VH VM VL N6 N7 N8 L8 SSGSL ACT ACT ACT ACT N9 ∗1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6), respectively, in the controlled status. – 18 – CXD3406GA Timing Generator Block Serial Interface Control The CXD3406GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the rising edge of SEN1. SSI1 SCK1 SEN1 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 There are two categories of timing generator block serial interface data: CXD3406GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below. – 19 – CXD3406GA Control Data Data D00 to D07 D08 to D09 D10 to D12 D13 to D14 D15 D16 to D23 D24 to D33 D34 D35 D36 to D37 D38 to D39 D40 to D47 LDAD Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 0 All 0 All 0 1 0 1 ADCLK logic phase switching See D36 to D37 LDAD. 0 STB Standby control See D38 to D39 STB. All 0 All 0 10000001 → Enabled Other values → Disabled CTG Category switching See D08 to D09 CTG. MODE Drive mode switching See D10 to D12 MODE. SMD PTSG CDAT Electronic shutter mode switching Internal SSG output pattern switching AF drive control data See D13 to D14 SMD. NTSC equivalent PAL equivalent See D16 to D23 CDAT. — — — — — — — — — — — — — — — — – 20 – CXD3406GA Shutter Data Data D00 to D07 D08 to D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0 10000001 → Enabled Other values → Disabled CTG Category switching See D08 to D09 CTG. SVD Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification See D10 to D19 SVD. SHD See D20 to D31 SHD. SPL See D32 to D41 SPL. — — — — – 21 – CXD3406GA Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD3406GA by the timing generator block serial interface, the CXD3406GA loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode Note that the CXD3406GA can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D10 to D12 MODE [Drive mode] The CXD3406GA timing generator block drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD3406GA and reflected at the falling edge of VD. D12 0 0 0 0 1 1 D11 0 0 1 1 0 1 D10 0 1 0 1 X X Description of operation Draft mode (sextuple speed: default) Frame mode (A field readout) Frame mode (B Field readout) Frame mode AF1 mode AF2 mode Control data: D15 PTSG [Internal SSG output pattern] The CXD3406GA internal SSG output pattern can be switched as follows. However, the drive mode bits are loaded to the CXD3406GA and reflected at the falling edge of VD. D15 0 1 Description of operation NTSC equivalent pattern PAL equivalent pattern The VD period in each pattern is defined as follows for each drive mode. Frame mode NTSC equivalent pattern PAL equivalent pattern 918H + 1716ck 945H∗1 Draft mode 262H + 1144ck 314H + 1568ck AF1 mode 131H + 572ck 157H + 784ck AF2 mode 65H + 1430ck 78H + 1536ck ∗1 Only 944H and 945H are 1208ck period. See the Timing Charts for the actual operation. – 22 – CXD3406GA Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment (°) 0 90 180 270 Control data: D38 to D39 STB [Standby] The operating mode of the timing generator block is switched as follows. However, the standby bits are loaded to the CXD3406GA and control is applied immediately at the rising edge of SEN1. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode See the Pin Status Table for the pin status in each mode. – 23 – CXD3406GA Control data: [AF drive] The CXD3406GA controls the drive of the vertical cut-out area of the line in AF1/AF2 mode by using control data D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and cannot support operation such as electrical image stabilization. The AF drive bits are loaded to the CXD3406GA and reflected at the falling edge of VD. As shown in the figure below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then normal transfer is performed equivalent to draft mode from the frame shift to the stage specified by the serial interface data to the timing of the falling edge of the next VD. Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for its application. VD High-speed sweep V1A Vck MODE CDAT 0 00h 4 FFh 0 00h Normal transfer Frame shift The number of high-speed sweep are different according to the selected mode. They are specified as follows. AF1 mode: 138 stages (0 to 7H) AF2 mode: 208 stages (0 to 11H) The frame shift data is expressed as shown in the table below using D16 to D23 CDAT. MSB D23 0 D22 1 ↓ 6 D21 1 D20 0 D19 1 D18 0 ↓ 9 D17 0 LSB D16 1 CDAT is expressed as 69h . Its definition area is specified as follows. AF1 mode: 00h ≤ CDAT ≤ FFh (11 to 23H) AF2 mode: 00h ≤ CDAT ≤ FFh (14 to 27H) – 24 – CXD3406GA Control data/shutter data: [Electronic shutter] The CXD3406GA realizes various electronic shutter functions by using control data D13 to D14 SMD and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 to D14 SMD. D14 0 0 1 1 D13 0 1 0 1 Description of operation Electronic shutter stopped mode High-speed/low-speed shutter mode HTSG control mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 X D30 0 ↓ 1 D29 0 D28 1 D27 1 D26 1 ↓ C D25 0 D24 0 D23 0 D22 0 ↓ 3 D21 1 LSB D20 1 SHD is expressed as 1C3h . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). However, in the frame mode A field, it matches (number of SUB pulses + 1). This is a specification for flickerless when the same mode is repeated. But this change may not occur because of flickerless depending on the conditions during low-speed shutter. Note) The bit data definition area is assured in terms of the CXD3406GA functions, and does not assure the CCD characteristics. – 25 – CXD3406GA VD SHD SVD V1A SUB WEN SMD SVD SHD 01 002h 10Fh 01 000h 050h Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL VD SHD V1A SUB WEN SMD SPL SVD SHD 10 001h 002h 10Fh 01 000h 000h 0A3h SVD Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function, it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. – 26 – CXD3406GA [HTSG control mode] During this mode, all shutter data items are invalid. The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure. VD V1A SUB Vck WEN SMD 01 11 01 Exposure time – 27 – Chart-1 Vertical Direction Timing Chart Frame mode A Field B Field MODE • ICX252/262 Applicable CCD image sensor VD 29 34 810 918 1 28 34 810 918 1 HD SUB High-speed sweep block C C High-speed sweep block A B V1A V1B V2 V3A 1542 1544 1546 1548 1550 1539 1541 1543 1545 1547 CCD OUT PBLK CLPOB CLPDM ID WEN CXD3406GA ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (918H + 1716ck units). For PAL equivalent pattern, it is 945H units, but 1208ck period only for 944H and 945H. 1549 – 28 – 1 3 5 7 1 3 5 7 9 11 13 15 V3B V4 2 4 6 8 2 4 6 8 10 12 Chart-2 Vertical Direction Timing Chart Draft mode • ICX252/262 MODE Applicable CCD image sensor VD 261 262 1 2 261 262 1 2 HD SUB D D V1A V1B V2 V3A – 29 – 6 3 10 15 22 27 34 4 1 8 13 20 25 32 V3B V4 527 534 539 546 525 532 537 544 549 CCD OUT 527 534 539 546 525 532 537 544 549 6 3 10 15 22 27 34 4 1 8 13 20 25 32 PBLK CLPOB CLPDM ID WEN CXD3406GA ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (262H + 1144ck units). For PAL equivalent pattern, it is 314H + 1568ck units. Chart-3 Vertical Direction Timing Chart AF1 mode • ICX252/262 MODE Applicable CCD image sensor VD 8 10 10 25 131 1 8 25 131 1 HD SUB D G Frame shift block F D High-speed sweep block F G High-speed sweep block Frame shift block V1A V1B V2 V3A V3B – 30 – 6 4 V4 6 4 CCD OUT PBLK CLPOB CLPDM ID WEN ∗ ∗ ∗ ∗ CXD3406GA The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 138 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift block. VD of this chart is NTSC equivalent pattern (131H + 572ck units). For PAL equivalent pattern, it is 157H + 784ck units. Chart-4 Vertical Direction Timing Chart AF2 mode • ICX252/262 MODE Applicable CCD image sensor VD 12 14 14 29 65 1 12 29 65 1 HD SUB D Frame shift block High-speed sweep block F High-speed sweep block G F D G Frame shift block V1A V1B V2 V3A V3B – 31 – 6 4 V4 6 4 CCD OUT PBLK CLPOB CLPDM ID WEN ∗ ∗ ∗ ∗ CXD3406GA The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 208 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift block. VD of this chart is NTSC equivalent pattern (65H + 1430ck units). For PAL equivalent pattern, it is 78H + 1536ck units. Chart-5 Horizontal Direction Timing Chart Frame mode • ICX252/262 MODE Applicable CCD image sensor (2288) 0 50 200 250 100 150 HD MCKO 52 172 H1 H2 70 110 V1A/B 99 148 V2 52 128 V3A/B 90 157 V4 70 138 – 32 – 52 47 174 110 110 SUB 198 PBLK 10 CLPOB 198 CLPDM ID WEN ∗ ∗ ∗ ∗ ∗ HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. ID and WEN are output at this timing shown above at the position shown in Chart-1. CXD3406GA Chart-6 Horizontal Direction Timing Chart Draft/AF1/AF2 mode • ICX252/262 MODE Applicable CCD image sensor (2288) 0 50 100 150 200 250 HD MCKO 52 172 H1 H2 57 70 93 106 129 142 V1A/B 66 79 115 102 138 151 V2 52 75 88 111 124 147 V3A/B 61 84 120 133 97 156 V4 71 140 – 33 – 52 47 174 110 110 SUB 198 PBLK 10 CLPOB 198 CLPDM ID WEN ∗ ∗ ∗ ∗ ∗ HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. ID and WEN are output at this timing shown above at the position shown in Charts-2, 3 and 4. CXD3406GA MODE Frame mode • ICX252/262 Chart-7 Horizontal Direction Timing Chart (High-speed sweep: C) Applicable CCD image sensor (2288) 0 50 100 150 200 250 HD MCKO 52 172 H1 H2 52 168 81 110 139 197 226 255 V1A/B 71 187 100 129 158 216 245 274 V2 52 110 168 81 139 197 226 255 V3A/B 71 100 158 129 187 216 245 274 V4 #1 70 138 – 34 – #2 #3 #4 SUB PBLK CLPOB CLPDM ID WEN ∗ ∗ ∗ ∗ ∗ HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 26H of 768ck(#1038). CXD3406GA MODE AF1/AF2 mode • ICX252/262 Chart-8 Horizontal Direction Timing Chart (High-speed sweep: F) (Frame shift: G) Applicable CCD image sensor (2288) 0 50 100 150 200 250 HD MCKO 52 172 H1 H2 52 128 204 71 90 166 109 147 185 223 242 261 V1A/B 64 83 102 140 178 121 159 197 216 235 254 273 V2 52 71 109 147 166 185 90 128 204 223 242 261 280 V3A/B 64 83 102 121 140 159 178 197 216 235 254 273 V4 71 – 35 – #1 140 52 47 105 110 #2 SUB PBLK 10 CLPOB CLPDM 219 ID WEN ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. WEN is output at this timing shown above at the position shown in Chart-3 and 4. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 6H of 2056ck (#138) in AF1 mode and 10H of 884ck (#208) in AF2 mode. Frame shift of V1A/B, V2, V3A/B and V4 receives the output control by the serial interface data and can specify up to #255 for both of AF1/AF2 mode. ID is output at the timing shown with dotted line during frame shift. CXD3406GA Chart-9 Horizontal Direction Timing Chart Frame mode • ICX252/262 MODE Applicable CCD image sensor 52 70 90 99 110 128 148 157 181 211 241 1100 1130 1160 1190 1250 1280 1310 52 70 90 99 110 128 (2288) 0 (2288) 0 HD [A] [A Field] V1A V1B V2 V3A V3B – 36 – [B] Logic alignment portion V4 [B Field] V1A V1B V2 V3A V3B V4 CXD3406GA ∗ HD of this chart indicates the actual CXD3406GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. 148 157 Chart-10 Horizontal Direction Timing Chart Draft/AF1/AF2 mode • ICX252/262 MODE Applicable CCD image sensor 52 57 61 66 70 75 79 84 88 93 97 102 106 111 115 120 124 129 133 138 142 147 151 156 1010 1040 1070 1100 1130 1160 1190 1220 1250 1280 1310 1340 1370 1400 (2288) 0 (2288) 0 HD [D] V1A V1B V2 V3A – 37 – V3B V4 ∗ HD of this chart indicates the actual CXD3406GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. 1430 52 57 61 66 70 75 79 84 88 93 97 102 106 111 115 120 124 129 133 138 142 147 151 156 CXD3406GA Chart-11 High-Speed Phase Timing Chart • ICX252/262 MODE Applicable CCD image sensor HD HD' CKI CKO ADCLK 52 172 1 MCKO H1 – 38 – H2 RG XSHP XSHD XRS ∗ HD' indicates the HD which is the actual CXD3406GA load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. CXD3406GA Chart-12 Vertical Direction Sequence Chart Draft → Frame → Draft • ICX252/262 MODE Applicable CCD image sensor VD V1A V1B V2 V3A V3B – 39 – Close B A 0 01 050h 050h 050h 050h 01 01 01 0 0 0 B C C D E E 3 00 000h V4 SUB Open F E 3 00 000h 0 01 050h F 0 01 050h Mechanical shutter Exposure time A CCD OUT MODE 0 SMD 01 SHD 050h ∗ This chart is a driving timing chart example of electronic shutter normal operation. ∗ Data exposed at D includes blooming component. For details, see the CCD image sensor Data Sheet. ∗ The CXD3406GA does not generate the pulse to control mechanical shutter operation. ∗ The switching timing of the drive mode and the electronic shutter data is not the same. CXD3406GA CXD3406GA CCD Signal Processor Block Serial Interface Control The CXD3406GA's CCD signal processor block basically loads the CCD signal processor block serial interface data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the operation 6 ADCLKI clocks after that. CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode. SSI2 SCK2 SEN2 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain setting data, OB clamp level setting data, and input pulse polarity setting data. Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then transmit the next category. The detail of each data are described below. Standby Control Data Data D00 D01 to D03 D04 to D14 D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED STB — Standby control Set to All 0. Normal operating mode Standby mode PGA Gain Setting Data Data D00 D01 to D03 D04 to D05 D06 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED — Set to All 0. GAIN PGA gain setting data – 40 – See D06 to D15 GAIN. CXD3406GA OB Clamp Level Setting Data Data D00 D01 to D03 D04 to D11 D12 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED — Set to All 0. OBLVL OB clamp level setting data See D12 to D15 OBLVL. Input Pulse Polarity Setting Data Data D00 D01 to D03 D04 to D12 D13 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED — Set to All 0. POL Input pulse polarity setting data Set to All 0. – 41 – CXD3406GA Detailed Description of Each Data Shared data: D01 to D03 CTG [Category] Of the data provided to the CXD3406GA by the CCD signal processor block serial interface, the CXD3406GA loads D04 and subsequent data to each data register as shown in the table below according to the combination of D01 to D03 . D01 0 0 0 0 1 D02 0 0 1 1 X D03 0 1 0 1 X Description of operation Loading to standby control data register Loading to PGA gain setting data register Loading to OB clamp level setting data register Loading to input pulse polarity setting data register Access prohibited Standby control data: D15 STB [Standby] The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor block is in standby mode, only the serial interface is valid. D15 0 1 Description of operation Normal operating mode Standby mode PGA gain setting data: D06 to D15 GAIN [PGA gain] The CXD3406GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by using PGA gain setting data D06 to D15 GAIN. The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN. MSB D06 0 ↓ 1 D07 1 D08 1 D09 1 ↓ C D10 0 D11 0 D12 0 D13 0 ↓ 3 D14 1 LSB D15 1 GAIN is expressed as 1C3h . For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting values are –6dB, 0dB, +20dB, +34dB and +42dB. – 42 – CXD3406GA OB clamp level setting data: D12 to D15 OBLVL [OB clamp level] The CXD3406GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal processor block control data D12 to D15 OBLVL. The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL. MSB D12 0 D13 1 ↓ 6 D14 1 LSB D15 0 OBLVL is expressed as 6h . For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values are 0LSB, 4LSB, 32LSB and 60LSB. – 43 – Application Circuit Block Diagram XSHPI XSHDI PBLKI CLPDMI CLPOBI XSHP XSHD PBLK CLPDM CLPOB ADCLK ADCLKI C7 0.1µF C8 0.1µF B7 A2 NC NC D0 (LSB) D1 D2 D3 D4 C2 C1 D3 D2 D5 D6 D7 D1 D8 E1 J2 K2 M2 N2 N9 M9 M8 N8 L8 D9 (MSB) CKO MCKO VD HD ID WEN RST SNCSL SSGSL Signal Processor Block A7 F9 F8 F7 G3 G2 CCDIN C9 D7 B3 D8 B2 B1 C3 C8 C7 A1 C1 C2 C3 C4 G9 G8 G7 H3 H2 H1 G1 C9 0.1µF C6 SEN2 SCK2 CCD ICX252/262 CCDOUT 1µF 1µF 390pF 390pF 240pF H1 J8 J9 K8 L5 N5 M4 L5 N6 N4 N7 H2 RG V1A V1B V2 V3A V3B V4 SUB TG/CDS/PGA/ADC CXD3406GA SSI1 SEN1 CKI OSCI SCK1 SSI2 OSCO TEST1 TEST2 TEST3 TEST4 This block diagram illustrates connections with each circuit block, and is not an actual circuit diagram. See the CCD image sensor data sheet for an example of specific circuit connections with the CCD image sensor. CXD3406GA Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. TEST5 – 44 – J1 K1 L1 M3 M7 A5 C4 B5 L2 N1 M1 A4 B4 A3 Controller CXD3406GA Notes on Operation 1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either before or at the same time as the VH pin power supply is started up. 15.0V t1 20% 0V 20% t2 t2 ≥ t1 –7.5V 2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by initializing the serial data. 3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pins. Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2 VDDf and 3 VDDg should be 0.1V or less. 5. The timing generator block and CCD signal processor block ground pins should use a shared ground which is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4, VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5 and AVSS6 should be 0.1V or less. 6. Do not perform serial communication with the CCD signal processor block during the effective image period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which are used by the CCD signal processor block, use of the dedicated ports is recommended. When using these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the effects on picture quality before use. – 45 – CXD3406GA Package Outline Oita Ass'y Unit: mm 0.2 SA 8.0 96PIN LFLGA X 12.0 0.10MAX SB x4 (0.3) (0.3) 0.5 A 0.8 96 -φ0.45 ± 0.05 φ0.08 M S A B DETAIL X N M L K J H G F E D C B A 0.9 B 0.9 0.5 (0.3) 12 3 4 5 6 7 8 9 0.8 0.5 LFLGA-96P-02 (0.3) 0.5 1.2 0.8 3 – φ0.50 PACKAGE STRUCTURE PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS ORGANIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.3 g SONY CODE EIAJ CODE JEDEC CODE P-LFLGA96-12X8-0.8 HITACHI TOKYO Ass'y 0.2 SA 8.0 96PIN LFLGA X 12.0 0.10MAX SB x4 (0.3) (0.3) 0.5 A 0.8 96 -φ0.45 ± 0.05 φ0.08 M S A B DETAIL X 0.9 N M L K J H G F E D C B A 0.9 B 0.5 (0.3) 12 3 4 5 6 7 8 9 0.8 0.5 LFLGA-96P-051 (0.3) 0.5 1.2 0.8 3 – φ0.50 PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE SONY CODE EIAJ CODE JEDEC CODE TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.3g P-LFLGA96-12.0X8.0-0.8 – 46 – S 0.15 0.2 0.2 S 0.10 S PIN 1 INDEX 1.3 MAX S 0.15 0.2 0.2 S 0.10 S PIN 1 INDEX 1.3 MAX Sony Corporation