CXD3408

CXD3408GA Timing Generator and Signal Processor for Frame Readout CCD Image Sensor Description The CXD3408GA is a timing generator and CCD signal processor IC for the ICX406 CCD image sensor. Features • Timing generator functions • Horizontal drive frequency 18MHz (base oscillation frequency 36MHz) • Supports frame readout/draft (quadruple speed) /AF (auto-focus) • High-speed/low-speed shutter function • Horizontal and vertical drivers for CCD image sensor • CCD signal processor functions • Correlated double sampling • Programmable gain amplifier (PGA) allows gain adjustment over a wide range (–6 to +42dB) • 10-bit A/D converter • Chip Scale Package (CSP): CSP allows vast reduction in the CCD camera block footprint Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX406 (1/1.8", 3980K pixels) 96 pin LFLGA (Plastic) Absolute Maximum Ratings • Supply voltage VSS – 0.3 to +7.0 VDDa, VDDb, VDDc, VDDd VDDe, VDDf, VDDg VSS – 0.3 to +4.0 VL –10.0 to VSS VH VL – 0.3 to +26.0 • Input voltage (analog) VIN VSS – 0.3 to VDD + 0.3 • Input voltage (digital) VI • Output voltage VO1 VO2 VO3 • Operating temperature Topr • Storage temperature Tstg VSS – 0.3 to VDD + 0.3 VSS – 0.3 to VDD + 0.3 VL – 0.3 to VSS + 0.3 VL – 0.3 to VH + 0.3 –20 to +75 –55 to +125 V V V V V V V V V °C °C Recommended Operating Conditions • Supply voltage VDDb 3.0 to 5.25 V VDDa, VDDc, VDDd, VDDe, VDDf, VDDg 3.0 to 3.6 V VM 0.0 V VH 14.5 to 15.5 V VL –7.0 to –8.0 V • Operating temperature Topr –20 to +75 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01341A26 CXD3408GA Block Diagram TEST3 TEST4 TEST5 DVDD1 DVDD2 DVSS3 DVSS1 A1 A2 C7 D8 D7 B8 B6 B9 A6 C5 A3 A4 B4 A5 C4 B5 E2 F2 F3 E3 F1 C4 C8 AVDD5 A9 AVSS6 A8 C7 B7 C8 A7 C9 C6 CCDIN C9 AVDD1 E9 AVDD2 E8 AVSS1 D9 AVSS2 E7 XSHPI F9 XSHDI F8 PBLKI F7 XSHP G9 XSHD G8 PBLK G7 XRS H7 VDD4 H8 VDD2 K7 RG K8 VSS2 K9 VDD3 H9 H1 J8 H2 J9 VSS3 J7 ID/EXP N9 WEN M9 L2 VH M5 VM L4 VL M6 Serial Port Register V Driver Selector N1 SEN1 SSG L8 SSGSL SSI1 M1 SCK1 Latch 1/2 Selector Pulse Generator CDS PGA ADC Latch DAC Serial Port Register B3 B2 B1 D0 (LSB) D1 D2 DVSS2 C3 D3 C2 D4 C1 D5 D3 D6 D2 D7 D1 D8 E1 D9 (MSB) ADCLKI CLPOBI CLPDMI VSS4 ADCLK CLPOB CLPDM VSS5 OSCI OSCO CKI CKO MCKO G1 G2 G3 L3 H1 H2 H3 J3 L1 K1 J1 J2 K2 N8 SNCSL AVDD3 AVDD4 AVSS3 AVSS4 AVSS5 SCK2 Preblanking Dummy Pixel Auto Zero SEN2 SSI2 NC NC C3 C2 C1 Black Level Auto Zero M8 M3 M7 TEST1 TEST2 RST L5 N5 M4 L6 V1A V1B V3A V2 N6 N4 N7 SUB V3B V4 N2 M2 HD VD L9 VDD1 K3 L7 VDD5 VSS1 N3 VSS6 –2– CXD3408GA Pin Configuration (Top View) A B C D E F G H J K L M N NC D2 D5 D8 D9 DVSS2 ADCLKI ADCLK CKI OSCO OSCI SCK1 SEN1 1 NC D1 D4 D7 DVDD1 DVSS3 CLPOBI CLPOB CKO MCKO SSI1 VD HD 2 SCK2 D0 D3 D6 DVSS1 DVDD2 CLPDMI CLPDM VSS5 VDD5 VSS4 TEST1 VSS6 3 SSI2 SEN2 TEST4 TEST3 TEST5 AVSS5 AVSS4 AVDD4 C9 C8 C7 C3 C1 AVSS2 PBLKI PBLK XRS VSS3 VDD2 AVSS6 AVDD3 C4 C2 AVDD2 XSHDI XSHD VDD4 H1 RG SSGSL RST SNCSL 8 AVDD5 AVSS3 CCDIN AVSS1 AVDD1 XSHPI XSHP VDD3 H2 VSS2 VDD1 WEN ID/EXP 9 VM V2 V4 4 V1A VH V1B 5 V3A VL V3B 6 VSS1 TEST2 SUB 7 –3– CXD3408GA Pin Description Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 D8 D9 E1 E2 Symbol NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 D6 C1 C2 AVSS1 D9 DVDD1 I/O — — I I I — — — — O O O I I — — — — O O O I — — — — I O O O — — — O — No connected. (Open) No connected. (Open) CCD signal processor block serial interface clock input. (Schmitt trigger) CCD signal processor block serial interface data input. (Schmitt trigger) CCD signal processor block test input 3. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. CCD signal processor block analog GND. CCD signal processor block analog power supply. ADC output. ADC output. ADC output (LSB). CCD signal processor block serial interface enable input. (Schmitt trigger) CCD signal processor block test input 5. Connect to DVDD. CCD signal processor block analog power supply. Capacitor connection. CCD signal processor block analog power supply. CCD signal processor block analog GND. ADC output. ADC output. ADC output. CCD signal processor block test input 4. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. Capacitor connection. Capacitor connection. CCD output signal input. ADC output. ADC output. ADC output. Capacitor connection. Capacitor connection. CCD signal processor block analog GND. ADC output (MSB). CCD signal processor block digital power supply. (Power supply for ADC) –4– Description CXD3408GA Pin No. E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 J2 J3 J7 J8 J9 K1 K2 K3 K7 K8 K9 L1 Symbol DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI CKO VSS5 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI I/O — — — — — — — I I I I I I O O O O O O O — — I O — — O O O O — — O — I Description CCD signal processor block digital GND. CCD signal processor block analog GND. CCD signal processor block analog power supply. CCD signal processor block analog power supply. CCD signal processor block digital GND. CCD signal processor block digital GND. CCD signal processor block digital power supply. Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger) CCD data level sample-and-hold pulse input. (Schmitt trigger) CCD precharge level sample-and-hold pulse input. (Schmitt trigger) Clock input for analog/digital conversion. (Schmitt trigger) CCD optical black signal clamp pulse input. (Schmitt trigger) CCD dummy signal clamp pulse input. (Schmitt trigger) Pulse output for horizontal and vertical blanking period pulse cleaning. CCD data level sample-and-hold pulse output. CCD precharge level sample-and-hold pulse output. Clock output for analog/digital conversion. CCD optical black signal clamp pulse output. CCD dummy signal clamp pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Timing generator block digital power supply. (Power supply for CDS block) Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2) Inverter input. Inverter output. Timing generator block digital GND. Timing generator block digital GND. CCD horizontal register clock output. CCD horizontal register clock output. Inverter output for oscillation. When not used, leave open or connect a capacitor. System clock output for signal processor IC. Timing generator block digital power supply. (Power supply for common logic block) Timing generator block digital power supply. (Power supply for RG) CCD reset gate pulse output. Timing generator block digital GND. Inverter input for oscillation. When not used, fix to low. –5– CXD3408GA Pin No. L2 L3 L4 L5 L6 L7 L8 L9 M1 M2 M3 M4 M5 M6 M7 Symbol SSI1 VSS4 VM V1A V3A VSS1 SSGSL VDD1 SCK1 VD TEST1 V2 VH VL TEST2 I/O I — — O O — I — I I I O — — I Description Timing generator block serial interface data input. Schmitt trigger input/No protective diode on power supply side. Timing generator block digital GND. Timing generator block digital GND. (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. Timing generator block digital GND. Internal SSG enable. High: Internal SSG valid, Low: External sync valid (With pull-down resistor) Timing generator block digital power supply. (Power supply for common logic block) Timing generator block serial interface clock input. Schmitt trigger input/No protective diode on power supply side. Vertical sync signal input. Timing generator block test input 1. Normally fix to GND. CCD vertical register clock output. Timing generator block 15.0V power supply. (Power supply for vertical driver) Timing generator block –7.5V power supply. (Power supply for vertical driver) Timing generator block test input 2. Normally fix to GND. (With pull-down resistor) (With pull-down resistor) M8 RST I Timing generator block reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side Memory write timing pulse output. Timing generator block serial interface strobe input. Schmitt trigger input/No protective diode on power supply side Horizontal sync signal input. Timing generator block digital GND. CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. CCD electronic shutter pulse output. Control input used to switch sync system. High: CKI sync, Low: MCKO sync (With pull-down resistor) M9 N1 N2 N3 N4 N5 N6 N7 N8 WEN SEN1 HD VSS6 V4 V1B V3B SUB SNCSL O I I — O O O O I N9 ID/EXP O Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) –6– CXD3408GA Electrical Characteristics Timing Generator Block Electrical Characteristics DC Characteristics Item Pins Symbol VDDa VDDb VDDc VDDd VI + VI – 0.7VDDd 0.3VDDd 0.8VDDd 0.2VDDd Feed current where IOH = –1.2mA Pull-in current where IOL = 2.4mA Feed current where IOH = –22.0mA VDDb – 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = –8.25V V1A/B, V2, V3A/B, V4 = –0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = –8.25V SUB = 14.75V 5.4 –4.0 5.0 –7.2 10.0 –5.0 VDDd – 0.8 0.4 VDDd – 0.8 0.4 VDDd – 0.8 0.4 VDDc – 0.8 0.4 VDDa – 0.8 0.4 0.4 VDDd – 0.8 0.4 (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 3.0 0.8VDDd 0.2VDDd Typ. 3.3 3.3 3.3 3.3 Max. 3.6 5.25 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA Supply voltage 1 VDD2 Supply voltage 2 VDD3 Supply voltage 3 VDD4 Supply voltage 4 VDD1, VDD5 Input voltage 1∗1 Input voltage 2∗2 RST, SCK1, SSI1, SEN1 TEST1, TEST2 VIH1 SNCSL, SSGSL VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 Input/Output voltage VD, HD Output voltage 1 Output voltage 2 H1, H2 RG Output voltage 3 XSHP, XSHD, VOH4 XRS, PBLK, CLPOB, CLPDM, VOL4 ADCLK CKO MCKO ID/EXP, WEN V1A, V1B, V3A, V3B, V2, V4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL IOM1 IOM2 IOH IOSL IOSH Output voltage 4 Output voltage 5 Output voltage 6 Output current 1 Output current 2 SUB ∗1 This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC. ∗2 These input pins are with pull-down resistor in the IC. Note) This table indicates conditions at 3.3V drive. –7– CXD3408GA Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI Symbol LVth VIH VIL VOH VOL Conditions (Within the recommended operating conditions) Min. Typ. VDDd/2 0.7VDDd 0.3VDDd Max. Unit V V V V 0.4 500k 20 2M 5M 50 V Ω MHz OSCO Feed current where IOH = –3.6mA Pull-in current where IOL = 2.4mA VIN = VDDd or VSS VDDd – 0.8 OSCI, OSCO RFB OSCI, OSCO f Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDd 0.3VDDd Conditions Min. Typ. VDDd/2 Max. Unit V V V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Conditions (VH = 15.0V, VM = GND, VL = –7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –8– CXD3408GA Switching Waveforms TTMH 90% TTHM VH 90% V1A (V1B, V3A, V3B) TTLM 10% 90% 10% 90% TTML VM 10% 10% VL TTLM 90% V2 (V4) 10% 90% TTML VM 10% VL TTLH 90% 90% TTHL VH SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –9– Measurement Circuit Serial interface data CKI VD HD C6 C4 C5 C5 C6 C6 +3.3V +15.0V –7.5V N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7 H2 RG H1 CKI XRS VSS6 VSS2 VDD5 VSS3 VSS5 CKO VDD3 SSI1 VDD2 OSCI VDD4 VSS4 XSHP MCKO OSCO CLPDM CLPOB XSHD PBLK CLPDMI G3 CLPOBI G2 ADCLK XSHPI XSHDI PBLKI DVDD2 DVSS3 H1 F9 F8 F7 F3 F2 ADCLKI G1 AVDD1 AVSS1 AVSS2 CXD3408GA DVSS2 DVSS1 DVDD1 AVDD2 C2 C1 D6 D7 D8 CCDIN C4 C3 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVSS3 AVDD3 D5 D4 D3 TEST4 AVSS5 NC NC SCK2 SSI2 TEST3 AVSS4 C9 E9 D9 E7 F1 E3 E2 E8 D8 D7 D3 D2 D1 C9 C8 C7 M4 V2 M5 VH M6 VL E1 D9 L8 SSGSL VDD1 L9 M1 SCK1 M2 VD M3 TEST1 N4 V4 N5 V1B N6 V3B M7 TEST2 M8 RST M9 WEN N1 SEN1 N2 HD L4 VM V1A V3A L5 L6 N7 SUB C3 N8 SNCSL N9 ID/EXP L7 VSS1 R1 C2 C2 R1 R1 C1 C2 C1 C2 C2 C2 C1 C2 – 10 – C3 820pF C4 8pF C5 180pF C6 10pF C2 C2 C2 C2 R1 C1 C2 C2 C1 R1 C1 C2 C2 R2 R1 A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6 CXD3408GA C1 R1 3300pF 30Ω C2 R2 560pF 10Ω CXD3408GA AC Characteristics AC characteristics between the serial interface clocks 0.8VDDd SSI1 SCK1 SEN1 SEN1 ts2 0.2VDDd 0.8VDDd ts1 0.2VDDd ts3 0.8VDDd th1 (Within the recommended operating conditions) Symbol Definition SSI1 setup time, activated by the rising edge of SCK1 SSI1 hold time, activated by the rising edge of SCK1 SCK1 setup time, activated by the rising edge of SEN1 SEN1 setup time, activated by the rising edge of SCK1 Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns ts1 th1 ts2 ts3 Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD 0.2VDDd V1A ts1 SEN1 0.8VDDd 0.2VDDd th1 ∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN1 setup time, activated by the falling edge of HD SEN1 hold time, activated by the falling edge of HD – 11 – Min. 0 110 Typ. Max. Unit ns µs ts1 th1 CXD3408GA Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD HD 0.2VDDd ts1 SEN1 0.8VDDd th1 0.2VDDd ∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol Definition SEN1 setup time, activated by the falling edge of VD SEN1 hold time, activated by the falling edge of VD Min. 0 200 Typ. Max. Unit ns ns ts1 th1 Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3408GA at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3408GA and controlled at the rising edge of SEN1. See "Description of Operation". SEN1 0.8VDDd Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns tpdPULSE Output signal delay, activated by the rising edge of SEN1 – 12 – CXD3408GA RST loading characteristics RST 0.8VDDd 0.2VDDd tw1 (Within the recommended operating conditions) Symbol Definition RST pulse width Min. 25 Typ. Max. Unit ns tw1 VD and HD phase characteristics VD 0.2VDDd ts1 th1 0.2VDDd 0.2VDDd HD (Within the recommended operating conditions) Symbol Definition VD setup time, activated by the falling edge of HD VD hold time, activated by the falling edge of HD Min. 100 20 Typ. Max. Unit ns ns ts1 th1 HD loading characteristics HD 0.2VDDd ts1 th1 0.8VDDd 0.2VDDd MCKO MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition HD setup time, activated by the rising edge of MCKO HD hold time, activated by the rising edge of MCKO Min. 20 5 Typ. Max. Unit ns ns ts1 th1 – 13 – CXD3408GA Output variation characteristics MCKO 0.8VDDd WEN, ID/EXP tpd1 WEN and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Time until the above outputs change after the rise of MCKO Min. 20 Typ. Max. 60 Unit ns – 14 – CXD3408GA CCD Signal Processor Block Electrical Characteristics DC Characteristics Item Pins Symbol VDDe VDDf (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Conditions Min. 3.0 3.0 Typ. Max. Unit 3.3 3.3 3.6 3.6 V V Supply voltage 1 DVDD1 Supply voltage 2 DVDD2 AVDD1, AVDD2, Supply voltage 3 AVDD3, AVDD4, AVDD5 Analog input capacitance CCDIN VDDg 3.0 3.3 3.6 V CIN 15 1.8 pF V Input voltage SCK2, SSI2, VI + SEN2, TEST3, TEST4, XSHDI, XSHPI, ADCLKI, VI – CLPOBI, CLPDMI, PBLKI ADCLKI VOH VOL Feed current where IOH = –2.0mA Pull-in current where IOL = 2.0mA VDDe – 0.9 1.1 V A/D clock duty 50 % V 0.4 V Output voltage D0 to D9 Analog Characteristics Item CCDIN input voltage amplitude PGA maximum gain PGA minimum gain ADC resolution ADC maximum conversion rate ADC integral non-linearity error ADC differential non-linearity error Signal-to-noise ratio CCDIN input voltage clamp level CCD optical black signal clamp level Fc max EL ED SNR∗1 CLP OB Symbol VIN Gmax Gmin (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Conditions PGA gain = 0dB, output full scale PGA gain setting data = "3FFh" PGA gain setting data = "000h" Min. Typ. Max. Unit 900 42 –6 10 18 PGA gain = 0dB PGA gain = 0dB CCDIN input connected to GND via a coupling capacitor PGA gain = 0dB 1100 mV dB dB bit MHz ±1.0 ±5.0 LSB ±0.5 ±1.0 LSB 62 1.5 OBLVL = "8h" PGA gain = 0dB 32 dB V LSB ∗1 SNR = 20 log (full-scale voltage/rms noise) – 15 – CXD3408GA AC Characteristics AC characteristics between the serial interface clocks 0.8VDD SSI2 SCK2 SEN2 SEN2 ts2 0.2VDD 0.8VDD ts1 0.2VDD ts3 0.8VDD th1 ∗ The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise of SEN2. (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol Definition SCK2 clock period SSI2 setup time, activated by the rise of SCK2 SSI2 hold time, activated by the rise of SCK2 SCK2 setup time, activated by the rise of SEN2 SEN2 setup time, activated by the rise of SCK2 Min. 100 30 30 30 30 Typ. Max. Unit ns ns ns ns ns tp1 ts1 th1 ts2 ts3 – 16 – CXD3408GA CDS/ADC Timing Chart N CCDIN N+1 N+2 N+3 XSHPI XSHDI tw1 ADCLKI DL D0 to D9 N – 10 N–9 N–8 N–7 ∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0". (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol Definition ADCLKI clock period ADCLKI clock duty DL Data latency Min. 54 50 9 Typ. Max. Unit ns % clocks tw1 Preblanking Timing Chart PBLKI 11 Clocks ADCLKI 11 Clocks D0 to D9 All "0" – 17 – CXD3408GA Description of Operation Pulses output from the CXD3408GA's timing generator block are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on page 20 and thereafter. Pin Status Table Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 Symbol NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 CAM SLP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — STB RST Pin No. D3 D7 D8 D9 E1 E2 E3 E7 E8 E9 F1 F2 F3 F7 F8 F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9 J1 Symbol D6 C1 C2 AVSS1 D9 DVDD1 DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI – 18 – ACT ACT ACT ACT ACT ACT ACT ACT ACT L L L L L L L — — ACT ACT CAM SLP — — — — — — — — — — — — — — — — — — — L L L L L L L H ACT ACT ACT H H ACT STB RST CXD3408GA Pin No. J2 J3 J7 J8 J9 K1 K2 K3 K7 K8 K9 L1 L2 L3 L4 L5 L6 L7 Symbol CKO VSS5 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI SSI1 VSS4 VM V1A V3A VSS1 CAM ACT SLP ACT — — STB L RST ACT Pin No. L9 M1 M2 Symbol VDD1 SCK1 VD∗1 TEST1 V2 VH VL TEST2 RST WEN SEN1 HD∗1 VSS6 V4 V1B V3B SUB SNCSL ID/EXP CAM SLP — STB RST ACT ACT ACT L — ACT L DIS H ACT ACT ACT ACT L L ACT ACT — — L L ACT L ACT ACT ACT ACT M3 M4 M5 M6 M7 M8 ACT VM — — — VM VM ACT ACT ACT ACT ACT L ACT L — ACT L ACT L L L DIS H ACT L — L ACT M9 N1 ACT ACT ACT ACT — — ACT ACT ACT DIS N2 N3 N4 N5 ACT ACT ACT ACT ACT ACT VM VH VH VH ACT L VM VH VH VH ACT L VL VM VL VL ACT L ACT ACT VH VH — VH VH VM VL N6 N7 N8 L8 SSGSL ACT ACT ACT ACT N9 ∗1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6), respectively, in the controlled status. – 19 – CXD3408GA Timing Generator Block Serial Interface Control The CXD3408GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the rising edge of SEN1. SSI1 SCK1 SEN1 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 There are two categories of timing generator block serial interface data: CXD3408GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below. – 20 – CXD3408GA Control Data Data D00 to D07 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 0 0 All 0 0 All 0 0 0 All 0 1 0 All 0 All 0 10000001 → Enabled Other values → Disabled See D08 to D09 CTG. D08, CTG D09 D10 to D12 D13 D14 D15, D16 D17 D18 to D31 D32 D33 FGOB EXP NTPL — MODE SMD HTSG — Category switching Drive mode switching Electronic shutter mode switching∗1 HTSG control switching∗1 — SSG function switching — Wide OBCLP generation switching ID/EXP output switching OBCLP waveform patterm switching ADCLK logic phase adjustment Standby control See D10 to D12 MODE. OFF OFF — NTSC — OFF ID ON ON — PAL — ON EXP D34, PTOB D35 D36, LDAD D37 D38, STB D39 D40 to D47 — See D34 to D35 PTOB. See D36 to D37 LDAD. See D38 to D39 STB. — — — ∗1 See D13 SMD. – 21 – CXD3408GA Shutter Data Data D00 to D07 Symbol CHIP Chip enable Function Data = 0 Data = 1 RST All 0 All 0 All 0 All 0 All 0 All 0 10000001 → Enabled Other values → Disabled See D08 to D09 CTG. D08, CTG D09 D10 to D19 D20 to D31 D32 to D41 D42 to D47 SVD Category switching Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification See D10 to D19 SVD. SHD See D20 to D31 SHD. SPL See D32 to D41 SPL. — — — — – 22 – CXD3408GA Detailed Description of Each Data Shared data: D08 , D09 CTG [Category] Of the data provided to the CXD3408GA by the serial interface, the CXD3408GA loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 D08 0 1 X Description of operation Loading to control data register Loading to shutter data register Test mode Note that the CXD3408GA can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D10 to D12 MODE [Drive mode] The CXD3408GA timing generator block drive mode can be switched as follows. However, the drive mode bits are located to the CXD3408GA and reflected at the falling edge of VD. D12 0 0 0 0 D11 0 0 1 1 D10 0 1 0 1 Description of operation Draft mode (default) AF1 mode AF2 mode Frame mode D12 1 1 1 1 D11 0 0 1 1 D10 0 1 0 1 Description of operation Draft mode Frame mode (A field read out) Frame mode (B field read out) Test mode Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame rate drive mode that can be used for purposes such as monitoring and auto focus (AF). AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these modes, the screen is swept in the vertical direction and the center portion lines are cut out. Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so on. Frame mode (A or B Field) is the drive mode in which each field can be specified separately. Control data: D17 NTPL [SSG function switching] The CXD3408GA internal SSG output pattern can be switched as follows. However, the SSG function switching bits are loaded to the CXD3408GA and reflected at the falling edge of VD. D17 0 1 Description of Operation NTSC equivalent pattern output PAL equivalent pattern output VD period in each pattern is defined as follows. Frame mode NTSC equivalent pattern PAL equivalent pattern 1012H + 1672ck 944H + 464ck Draft mode 224H + 1372ck × 2 269H + 2039ck AF1 mode 112H + 1372ck 134H + 2354ck AF2 mode 56H + 686ck 67H + 1178ck See the Timing Charts for the actual operation. – 23 – CXD3408GA Control data: D32 FGOB [Wide CLPOB generation] This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual operation. The default is "OFF". D32 0 1 Description of operation Wide CLPOB generation OFF Wide CLPOB generation ON Control data: D34 , D35 PTOB [CLPOB waveform pattern] This indicates the CLPOB waveform pattern. The default is "Normal". D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Shifted rearward) (Shifted forward) (Wide) Control data: D36 , D37 LOAD [ADCLK logical phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment (°) 0 90 180 270 Control data: D38 , D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD3408GA and control is applied immediately at the rising edge of SEN1. D39 X 0 1 D38 0 1 1 Symbol CAM SLP STB Operating mode Normal operating mode Sleep mode Standby mode See the Pin Status Table for the pin status in each mode. – 24 – CXD3408GA Control data/shutter data: [Electronic shutter] The CXD3408GA realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 SMD. D13 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 X D30 0 ↓ 1 D29 0 D28 1 D27 1 D26 1 ↓ C D25 0 D24 0 D23 0 D22 0 ↓ 3 D21 1 LSB D20 1 SHD is expressed as 1C3h . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [Electronic shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVD SHD SPL Data D10 to D19 D20 to D31 D32 to D41 Description Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) Note) The bit data definition area is assured in terms of the CXD3408GA functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)} Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). – 25 – CXD3408GA VD SHD SVD V1A SUB WEN EXP SMD SVD SHD 1 002h 10Fh 1 000h 050h Exposure time Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL 000 VD SHD V1A SUB WEN EXP SMD SPL SVD SHD 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVD 002 Exposure time Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa. – 26 – CXD3408GA [HTSG control mode] This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG. D14 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode VD V1A SUB Vck WEN EXP HTSG SMD 0 1 1 0 0 1 Exposure time [EXP pulse] The ID/EXP pin (N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation. Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the latter value is 1416ck. – 27 – Chart-1 • ICX406 Vertical Direction Timing Chart MODE Frame mode A Field B Field Applicable CCD image sensor VD 75 82 943 1013 1 74 82 943 1013 1 HD SUB A C High-speed sweep block C High-speed sweep block B V1A V1B V2 V3A 1712 1714 1716 1718 1720 1709 1711 1713 1715 1547 CCD OUT PBLK CLPOB CLPDM ID/EXP WEN CXD3408GA ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (1012H + 1672ck units). For PAL equivalent pattern, it is 944H + 464ck units. 1719 – 28 – 1 3 5 7 9 11 1 3 5 7 9 11 V3B V4 2 4 6 8 10 12 2 4 6 8 Chart-2 • ICX406 Vertical Direction Timing Chart MODE Draft mode Applicable CCD image sensor VD 218 3 3 226 1 218 226 1 HD SUB D D V1A V1B V2 V3A 1706 1710 1713 1717 1706 1710 PBLK CLPOB CLPDM ID/EXP WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (224H + 1372ck + 1372ck units). For PAL equivalent pattern, it is 269H + 2039ck units. 1713 1717 – 29 – 10 5 14 21 30 37 46 1 6 1 10 17 26 33 42 V3B V4 10 5 14 21 30 37 46 1 6 1 10 17 26 33 42 CCD OUT CXD3408GA Chart-3 • ICX406 Vertical Direction Timing Chart MODE AF1 mode Applicable CCD image sensor VD 113 9 2 106 113 2 9 106 HD SUB E F Frame shift block G High-speed sweep block G High-speed sweep block E F Frame shift block V1A V1B V2 V3A – 30 – 10 6 V3B V4 10 6 CCD OUT PBLK CLPOB CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ CXD3408GA The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (112H + 1372ck units). For PAL equivalent pattern, it is 134H + 2354ck units. Chart-4 • ICX406 Vertical Direction Timing Chart MODE AF2 mode Applicable CCD image sensor VD 57 12 2 47 57 2 12 47 HD SUB E Frame shift block Frame shift block G High-speed sweep block F G High-speed sweep block E F V1A V1B V2 V3A – 31 – 10 6 V3B V4 10 6 CCD OUT PBLK CLPOB CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ CXD3408GA The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block. VD of this chart is NTSC equivalent pattern (56H + 686ck units). For PAL equivalent pattern, it is 67H + 1178ck units. Chart-5 • ICX406 Horizontal Direction Timing Chart MODE Frame mode Applicable CCD image sensor (2669) 0 100 150 200 250 300 350 400 450 500 50 550 HD MCKO 317 345 361 365 4 60 H1 H2 92 156 220 124 168 343 232 284 252 188 V1A/B V2 60 V3A/B V4 SUB 60 PBLK – 32 – 347 319 124 124 343 24 50 CLPOB (1) 16 42 CLPOB (2) 32 58 CLPOB (3) 16 58 CLPOB (4) 58 CLPOB (wide) CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD3408GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1. CXD3408GA Chart-6 • ICX406 Horizontal Direction Timing Chart MODE Draft mode, AF1 mode, AF2 mode Applicable CCD image sensor (2669) 0 100 150 200 250 300 350 400 450 500 50 550 HD MCKO 317 345 361 365 4 60 H1 H2 92 108 100 116 168 343 232 140 180 204 244 268 308 124 164 188 228 252 292 148 172 212 236 276 300 132 156 196 220 260 284 68 V1A/B 84 V2 60 V3A/B 76 V4 SUB 60 – 33 – 347 319 124 124 343 PBLK 24 50 CLPOB (1) 16 42 CLPOB (2) 32 58 CLPOB (3) 16 58 CLPOB (4) 58 CLPOB (wide) CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD3408GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4. CXD3408GA Chart-7 • ICX406 Horizontal Direction Timing Chart (High-speed sweep: C) MODE Frame mode Applicable CCD image sensor (2669) 0 100 150 200 250 300 350 400 450 500 50 550 HD MCKO 317 345 361 365 4 60 H1 H2 116 144 116 144 200 256 312 368 172 228 284 340 396 424 200 256 312 368 424 452 480 172 228 284 340 396 452 480 508 536 508 536 564 564 60 V1A/B 88 V2 60 V3A/B 88 V4 #1 168 232 #2 #3 #4 #5 – 34 – SUB PBLK CLPOB CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD3408GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 72H of 2660ck (#1739). CXD3408GA Chart-8 • ICX406 Horizontal Direction Timing Chart (Frame shift: F) (High-speed sweep: G) MODE AF1 mode, AF2 mode Applicable CCD image sensor (2669) 0 100 150 200 250 300 350 400 450 500 50 550 HD MCKO 317 345 361 365 4 60 H1 H2 92 108 100 116 140 180 204 244 268 308 332 372 396 124 164 188 228 252 292 316 356 380 148 172 212 236 276 300 340 364 404 428 420 444 436 460 132 156 196 220 260 284 324 348 388 412 452 476 468 492 484 508 500 524 516 540 532 556 548 68 V1A/B 84 V2 60 V3A/B 76 V4 #1 168 232 – 35 – #2 #3 #4 #5 124 #6 #7 #8 SUB 60 PBLK 24 50 CLPOB CLPDM ID/EXP WEN ∗ ∗ ∗ ∗ ∗ ∗ The HD of this chart indicates the actual CXD3408GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4. Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 7H 1563ck (#232) in AF1 mode and 10H 1688ck (#360) in AF2 mode. In addition, high-speed sweep is performed up to 111H 2015ck (#240) in AF1 mode and 55H 1688ck (#360) in AF2 mode. CXD3408GA Chart-9 • ICX406 Horizontal Direction Timing Chart MODE Frame mode Applicable CCD image sensor 1104 1136 1168 1200 1202 1260 1292 124 156 188 220 252 (2669) 0 (2669) 0 HD A [A Field] V1A V1B V2 V3A V3B V4 [B Field] B V1A V1B V2 V3A V3B V4 CXD3408GA ∗ The HD of this chart indicates the actual CXD3408GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. 284 – 36 – Chart-10 • ICX406 Horizontal Direction Timing Chart MODE Draft mode Applicable CCD image sensor 1104 1136 1168 1200 1202 1260 1292 1324 1356 1358 1416 (2669) 0 60 76 92 108 124 140 156 172 (2669) 0 HD D V1A V1B V2 V3A – 37 – V3B V4 ∗ The HD of this chart indicates the actual CXD3408GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. 68 84 100 116 132 148 164 180 CXD3408GA Chart-11 • ICX406 Horizontal Direction Timing Chart MODE AF1 mode, AF2 mode Applicable CCD image sensor 1104 1136 1168 1200 1202 1260 1292 1324 1356 1358 1416 1448 1464 1456 1480 1472 1496 1488 1512 1504 1528 1520 1544 1536 1560 1552 1568 (2669) 0 (2669) 0 HD E V1A V1B V2 V3A – 38 – V3B V4 ∗ The HD of this chart indicates the actual CXD3408GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. 60 76 92 108 124 140 156 172 188 204 220 236 252 268 284 300 68 84 100 116 132 148 164 180 196 212 228 244 260 276 292 308 CXD3408GA Chart-12 • ICX406 High-Speed Phase Timing Chart MODE Applicable CCD image sensor HD HD' CKI CKO ADCLK 60 317 1 MCKO H1 – 39 – H2 RG XSHP XSHD XRS ∗ HD' indicates the HD which is the actual CXD3408GA load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. CXD3408GA Chart-13 • ICX406 Vertical Direction Sequence Chart MODE Draft → Frame → Draft Applicable CCD image sensor VD V1A V1B V2 V3A V3B V4 – 40 – Close B B E 0 1 050h 3 0 000h 0 1 050h 050h 1 0 C C D E SUB Open F E 3 0 000h 0 1 050h F 0 1 050h Mechanical shutter Exposure time A CCD OUT A MODE 0 0 SMD 1 1 SHD 050h 050h ∗ ∗ ∗ ∗ This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD3408GA does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data is not the same. CXD3408GA CXD3408GA CCD Signal Processor Block Serial Interface Control The CXD3408GA's CCD signal processor block basically loads the CCD signal processor block serial interface data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the operation 6 ADCLKI clocks after that. CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode. SSI2 SCK2 SEN2 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain setting data, OB clamp level setting data, and input pulse polarity setting data. Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for each category and wait until the setting value 6 ADCLKI clocks after that has been reflected to operation, then transmit the next category. The detail of each data are described below. Standby Control Data Data D00 D01 to D03 D04 to D14 D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED STB — Standby control Set to All 0. Normal operating mode Standby mode PGA Gain Setting Data Data D00 D01 to D03 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 D04, FIXED D05 D06 to D15 GAIN — Set to All 0. PGA gain setting data See D06 to D15 GAIN. – 41 – CXD3408GA OB Clamp Level Setting Data Data D00 D01 to D03 D04 to D11 D12 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED — Set to All 0. OBLVL OB clamp level setting data See D12 to D15 OBLVL. Input Pulse Polarity Setting Data Data D00 D01 to D03 D04 to D12 D13 to D15 Symbol TEST CTG Test code Category switching Function Data = 0 Set to 0. D01 to D03 CTG Data = 1 FIXED — Set to All 0. POL Input pulse polarity setting data Set to All 0. – 42 – CXD3408GA Detailed Description of Each Data Shared data: D01 to D03 CTG [Category] Of the data provided to the CXD3408GA by the CCD signal processor block serial interface, the CXD3408GA loads D04 and subsequent data to each data register as shown in the table below according to the combination of D01 to D03 . D01 0 0 0 0 1 D02 0 0 1 1 X D03 0 1 0 1 X Description of operation Loading to standby control data register Loading to PGA gain setting data register Loading to OB clamp level setting data register Loading to input pulse polarity setting data register Access prohibited Standby control data: D15 STB [Standby] The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor block is in standby mode, only the serial interface is valid. D15 0 1 Description of operation Normal operating mode Standby mode PGA gain setting data: D06 to D15 GAIN [PGA gain] The CXD3408GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by using PGA gain setting data D06 to D15 GAIN. The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN. MSB D06 0 ↓ 1 D07 1 D08 1 D09 1 ↓ C D10 0 D11 0 D12 0 D13 0 ↓ 3 D14 1 LSB D15 1 GAIN is expressed as 1C3h . For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting values are –6dB, 0dB, +20dB, +34dB and +42dB. – 43 – CXD3408GA OB clamp level setting data: D12 to D15 OBLVL [OB clamp level] The CXD3408GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal processor block control data D12 to D15 OBLVL. The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL. MSB D12 0 D13 1 ↓ 6 D14 1 LSB D15 0 OBLVL is expressed as 6h . For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values are 0LSB, 4LSB, 32LSB and 60LSB. – 44 – Application Circuit Block Diagram XSHPI XSHDI PBLKI CLPDMI CLPOBI XSHP XSHD PBLK CLPDM CLPOB ADCLK ADCLKI C7 0.1µF C8 0.1µF B7 A2 NC NC D0 (LSB) D1 D2 D3 D4 C2 C1 D3 D2 D5 D6 D7 D1 D8 E1 J2 K2 M2 N2 N9 M9 M8 N8 L8 D9 (MSB) CKO MCKO VD HD ID/EXP WEN RST SNCSL SSGSL Signal Processor Block A7 F9 F8 F7 G3 G2 CCDIN C9 D7 B3 D8 B2 B1 C3 C8 C7 A1 C1 C2 C3 C4 G9 G8 G7 H3 H2 H1 G1 CCD ICX406 CCDOUT 1µF 1µF 390pF 390pF 240pF H1 J8 J9 K8 L5 N5 M4 L5 N6 N4 N7 H2 RG V1A V1B V2 V3A V3B V4 SUB TG/CDS/PGA/ADC CXD3408GA J1 K1 L1 M3 M7 A5 C4 B5 L2 N1 M1 A4 B4 A3 SSI1 SEN1 SCK1 SSI2 SEN2 OSCI SCK2 CKI C9 0.1µF C6 OSCO TEST1 TEST2 TEST3 TEST4 This block diagram illustrates connections with each circuit block, and is not an actual circuit diagram. See the CCD image sensor data sheet for an example of specific circuit connections with the CCD image sensor. CXD3408GA Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. TEST5 – 45 – Controller CXD3408GA Notes on Operation 1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either before or at the same time as the VH pin power supply is started up. 15.0V t1 20% 0V 20% t2 t2 ≥ t1 –7.5V 2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by initializing the serial data. 3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pins. Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2 VDDf and 3 VDDg should be 0.1V or less. 5. The timing generator block and CCD signal processor block ground pins should use a shared ground which is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4, VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5 and AVSS6 should be 0.1V or less. 6. Do not perform serial communication with the CCD signal processor block during the effective image period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which are used by the CCD signal processor block, use of the dedicated ports is recommended. When using these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the effects on picture quality before use. – 46 – CXD3408GA Package Outline Oita Ass'y Unit: mm 0.2 SA 8.0 96PIN LFLGA X 12.0 0.10MAX SB x4 (0.3) (0.3) 0.5 A 0.8 96 -φ0.45 ± 0.05 φ0.08 M S A B DETAIL X N M L K J H G F E D C B A 12 3 4 5 6 7 8 9 0.8 0.5 LFLGA-96P-02 0.9 B 0.9 (0.3) 0.5 1.2 0.8 3 – φ0.50 0.5 (0.3) PACKAGE STRUCTURE PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS ORGANIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.3 g SONY CODE EIAJ CODE JEDEC CODE P-LFLGA96-12X8-0.8 HITACHI TOKYO Ass'y 0.2 SA 8.0 96PIN LFLGA X 12.0 0.10MAX SB x4 (0.3) (0.3) 0.5 A 0.8 96 -φ0.45 ± 0.05 φ0.08 M S A B DETAIL X 0.9 N M L K J H G F E D C B A 0.9 B 0.5 (0.3) 12 3 4 5 6 7 8 9 0.8 0.5 LFLGA-96P-051 (0.3) 0.5 1.2 0.8 3 – φ0.50 PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE SONY CODE EIAJ CODE JEDEC CODE TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.3g P-LFLGA96-12.0X8.0-0.8 – 47 – S 0.15 0.2 0.2 S 0.10 S PIN 1 INDEX 1.3 MAX S 0.15 0.2 0.2 S 0.10 S PIN 1 INDEX 1.3 MAX Sony Corporation