CXD3503R

CXD3503R Color Shading Correction IC for Liquid Crystal Projectors Description The CXD3503R is a color shading correction IC for Sony data projectors. Used together with the Sony LCD driver CXA2111R or CXA2112R, this IC corrects color shading caused by the LCD panel structure or the optical system. This IC has a built-in SRAM and D/A converter, and 16 horizontal and 13 vertical correction points can be set via a serial interface. Functions • Generates the color shading correction signals for the high-temperature polysilicon TFT LCD panels used in Sony projectors • Supports various SVGA, XGA and SXGA signals using 1/2 dot clock input • Vertical output signal interpolation using an internal arithmetic circuit • Automatic determination of eliminated lines during pulse eliminator display when used together with the Sony timing generator ICs CXD2464R or CXD3500R • Supports up/down and/or right/left inversion • Supports LCD panel display area switching conversion functions • Standby and correction OFF functions Applications Liquid crystal projectors, etc. Structure Silicon gate CMOS IC 64 pin LQFP (Plastic) Absolute Maximum Ratings (VSS = 0V) • Supply voltage VDD VSS – 0.3 to +7.0 • Input voltage VI VSS – 0.3 to VDD + 0.3 • Output voltage VO VSS – 0.3 to VDD + 0.3 • Storage temperature Tstg –55 to +125 • Operating temperature Topr –40 to +85 V V V °C °C Recommended Operating Conditions (Ta = –20 to +75°C, VSS = 0V) Supply voltage VDD 4.5 to 5.5 V Note) Company names and product names, etc. contained in these materials are trademarks or registered trademarks of the respective companies. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99432-PS CXD3503R Block Diagram DACKO DACKI 31 32 44 33 6bit HSYNC 60 VST 3 H, V detector Buff. Memory controller Buff. Memory (SRAM) DAC 36 DACO2 37 BFIN2 Buff. HST 4 Eliminator Operation block 6bit DAC 41 DACO1 42 BFIN1 Main controller V up/down counter 6bit H up/down counter Main Memory (SRAM) DAC 46 DACO0 47 BFIN0 Buff. 48 AOUT0 Buff. 43 AOUT1 38 AOUT2 Master clock CKI 63 System clear XCLR 61 Data SCTR 57 SCLK 58 SDAT 59 6 RGT 5 DWN 7 CTRL 11 to 16, 18 to 23, 25 to 30 DOUT 40 VRL Serial I/F Block –2– OLIM VRH CXD3503R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol NC NC VST HST DWN RGT CTRL TEST0 TEST1 TEST2 DOUT00 DOUT01 DOUT02 DOUT03 DOUT04 DOUT05 DVSS0 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DVDD0 DOUT20 DOUT21 DOUT22 DOUT23 DOUT24 DOUT25 DACKO DACKI OLIM DVDD1 I/O — — I I I I I I I I O O O O O O — O O O O O O — O O O O O O O I I — Not connected Not connected VST pulse input HST pulse input Up/down inversion control input (H: down scan, L: up scan) Right/left inversion control input (H: normal scan, L: reverse scan) Up/down and/or right/left inversion control signal (Serial settings selected when L.) Test (Leave open.) Test (Leave open.) Test (Leave open.) Digital data output 00 Digital data output 01 Digital data output 02 Digital data output 03 Digital data output 04 Digital data output 05 Digital GND Digital data output 10 Digital data output 11 Digital data output 12 Digital data output 13 Digital data output 14 Digital data output 15 Digital VDD (5V) Digital data output 20 Digital data output 21 Digital data output 22 Digital data output 23 Digital data output 24 Digital data output 25 DAC clock output (Connect to DACKI.) DAC clock input (Connect to DACKO.) Digital data output limiter (H: Hi-Z, L: digital data output) Digital VDD (5V) –3– Description Processing for internal input — — — — — — — L L L — — — — — — — — — — — — — — — — — — — — — — — — CXD3503R Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol DVSS1 DACO2 BFIN2 AOUT2 AVSS VRL DACO1 BFIN1 AOUT1 VRH AVDD DACO0 BFIN0 AOUT0 DVSS2 NC NC NC NC NC NC DVDD2 SCTR SCLK SDAT HSYNC XCLR DVSS3 CKI SLCK I/O — O I O — I O I O I — O I O — — — — — — — — I I I I I — I I Digital GND DAC output 2 Buffer input 2 Correction signal output 2 Analog GND Description Processing for internal input — — — — — — — — — — — — — — — — — — — — — — — — — — H — — — DAC output low reference voltage input DAC output 1 Buffer input 1 Correction signal output 1 DAC output high reference voltage input Analog power supply DAC output 0 Buffer input 0 Correction signal output 0 Digital GND Not connected Not connected Not connected Not connected Not connected Not connected Digital VDD (5V) Serial chip select input (serial transfer block) Serial clock input (serial transfer block) Serial data input (serial transfer block) HSYNC input Clear (L: system clear) Digital GND Master clock input Clock switching (H: Internal 1/2 frequency divider used.) –4– CXD3503R Electrical Characteristics DC Characteristics Item Supply voltage Input, output voltage Input voltage 1 Symbol VDD VI, VO VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL Input leak current Output leak current Pull-up resistor IIL IOZ RUP CMOS input CMOS input With pull-up resistor CMOS input With pull-down resistor TTL input 2.5 TTL Schmitt input IOH = –4mA IOL = 4mA VI = VDD, VSS During high impedance output –10 –10 60 45 During 41MHz operation 120 90 60 VDD – 2.1 0.4 10 10 240 180 V µA µA kΩ kΩ mA 0.6 V 0.7VDD 0.3VDD 0.7VDD 0.3VDD 2.2 0.8 V V V Conditions (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –40 to +85°C) Min. 4.5 VSS 0.7VDD 0.3VDD V Typ. 5.0 Max. 5.5 VDD Unit Applicable pins V V ∗1 ∗4 ∗2 ∗5 ∗3 ∗6, ∗7 ∗1, ∗3, ∗5 ∗7 ∗4 ∗2 Input voltage 2 Input voltage 3 Input voltage 4 Input voltage 5 Output voltage 1 Pull-down resistor RDN Current consumption IDD (INPUT) ∗1 CTRL, DACKI, DWN, HST, OLIM, RGT, SLCK, VST ∗2 TEST0, 1, 2 ∗3 HSYNC, SCLK, SCTR, SDAT ∗4 XCLR ∗5 CKI (OUTPUT) ∗6 DACKO ∗7 DOUT00 to 05, DOUT10 to 15, DOUT20 to 25 Note) AOUT0, 1 and 2, DACO0, 1 and 2, BFIN0, 1 and 2, VRH and VRL are not included in the DC characteristics. –5– CXD3503R AC Characteristics External Clock Input AC Characteristics Symbol Item HSYNC setup time, activated by the rising edge of CKI HSYNC hold time, activated by the rising edge of CKI CKI L/H level pulse width (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –40 to +85°C) Min. 12 0.5 — Typ. — — 50 Max. — — — Unit ns % ts0 th0 tWL/tWH Serial Transfer AC Characteristics Symbol Item (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –40 to +85°C) Min. 8Tns 4Tns 8Tns 4Tns 4Tns 4Tns Typ. — — — — — — Max. — — — — — — T: Input clock cycle ts0 ts1 th0 th1 tW1L tW1H SCTR setup time, activated by the rising edge of SCLK SDAT setup time, activated by the rising edge of SCLK SCTR hold time, activated by the rising edge of SCLK SDAT hold time, activated by the rising edge of SCLK SCLK L level pulse width SCLK H level pulse width Timing Definition External Clock Input AC Characteristics th0 ts0 50% twL CKI1, 2 50% twH 50% 50% 50% th0 HSYNC (negative polarity) 50% ts0 Serial Transfer AC Characteristics ts0 SCTR 50% tw1L SCLK 50% ts1 SDAT 50% th1 tw1H th0 –6– CXD3503R Electrical Characteristics (Analog Block) 6-bit D/A Converter part Item Resolution Conversion rate Linearity error Differential linearity error Output resistance Symbol RES FS EL ED RO (Ta = 25°C, VDD = 5.0V, VSS = 0V, VRH – VRL = 1.0V) Min. — — — — 140 Typ. — — — — 213 Max. 6 30 ±0.5 ±0.5 286 Unit Bits MPS LSB LSB Ω Operational Amplifier part (Operating Temperature variation) Item Operating temperature Input offset voltage Current consumption Maximum output saturation voltage Input voltage range Slew rate Ta VIO ICC Vopp VIN SR Symbol Min. –40 5 2.4 0 to 4.95 1.5 to 5.0 39 Typ. 25 5 1.8 0 to 4.95 1.7 to 5.0 31 (VDD = 5.0V, VSS = 0V) Max. 85 5 1.6 0 to 4.95 1.8 to 5.0 28 Unit °C mV mA V V V/µs Operational Amplifier part (Supply Voltage variation) Item Operating voltage Input offset voltage Current consumption Maximum output saturation voltage Input voltage range Slew rate Symbol VIO VIO ICC Vopp VIN SR Min. 4.5 5 1.4 0 to 4.45 1.7 to 4.5 24 Typ. 5.0 5 1.8 0 to 4.95 1.7 to 5.0 31 (Ta = 25°C, VSS = 0V) Max. 5.5 5 2.4 0 to 5.43 1.9 to 5.5 40 Unit V mV mA V V V/µs –7– CXD3503R AC Characteristics External Clock Input AC Characteristics 6-Bit D/A Converter Item Clock H level width Clock L level width Data setup time Data hold time Output delay time Timing Definition Ts DOUT Th (Ta = 25°C, VDD = 5.0V, VSS = 0V, VRH – VRL = 1.0V, CL = 30pF) Symbol Twh Twl Ts Th Tdl Min. 17 17 10 10 — Typ. — — — — 35 Max. — — — — — ns Unit DATA N Twh Twl DACKI Tdl DACO Output N – 1 Output N Internal Structure 6-Bit D/A Converter VRH VRL DACKI DOUTn5 DOUTn4 DOUTn3 DOUTn2 DOUTn1 DOUTn0 VRH VRL CLK D5 D4 D3 D2 D1 D0 AOUT DACOn Operational Amplifier AOUTn BFINn STBB STBB : Internal pin n : 0, 1, 2 –8– CXD3503R I/O Pin Description Pin No. 3 4 5 6 Symbol VST HST DWN RGT Description This pin is a reference of vertical output timing. Inputs the VST pulse from the timing generator IC. Inputs the HST pulse from the timing generator IC. When not rising pulse eliminator, connect to DVDD and use it. Up/down and/or right/left inversion control external input (H: normal scan, L: reverse scan) This setting is invalid when the internal register is used. Up/down and/or right/left inversion control signal selection setting. (For the DWN and RGT control signals, Pins 5 and 6 are selected when CTRL is H, and the settings from the internal register made via the serial interface are selected when CTRL is L.) Digital data outputs. The data input to the DAC is output as is when OLIM (Pin 33) is L. Normally, output is not performed. Set OLIM to H and leave these open. Internal DAC clock input/output. DAC clock generated inside the IC is output from DACKO. Normally, input this DACKO output to DACKI. Digital data output limiter. When OLIM is L, the data input to the DAC is output from the DOUT00 to DOUT25 output pins. When OLIM is H, these output pins go to high impedance state. Analog outputs from the internal DAC. The output impedance varies from several ten to several thousand Ω depending on the output voltage level, so connect these pins to BFIN2, 1 and 0 (buffer inputs), respectively. Internal operational amplifier buffer inputs. Connect to DACO2, 1 and 0, respectively. Analog correction signal outputs DAC L side reference voltage input (Input via buffer.) DAC H side reference voltage input (Input via buffer.) Serial control inputs. Timing control and correction point data are all set by these pins. For details, see page 12 "Serial Transfer Operation". This pin is a reference of horizontal output timing. Normally, input horizontal sync signal. System clear. Internal register is initialized by setting to L. Input pins are pulled up to H internally. Master clock input. Input level is TTL. Clock switching (H: Clock obtained by 1/2 frequency-dividing CKI using the internal frequency divider is selected. L: CKI input is selected. The selected clock is an internal master clock.) 7 CTRL 11 to 16, 18 to 23, 25 to 30 31 32 33 DOUT00 to DOUT25 DACKO DACKI OLIM 36, 41, 46 DACO2, 1, 0 37, 42, 47 38, 43, 48 40 44 57 58 59 60 61 63 64 BFIN2, 1, 0 AOUT2, 1, 0 VRL VRH SCTR SCLK SDAT HSYNC XCLR CKI SLCK 17, 35, 49, 62 DVSS 24, 34, 56 39 45 DVDD AVSS AVDD –9– Power supply inputs. Do not raise either analog power supply or digital power supply. CXD3503R Clock input (CKI: Pin 63) The master clock input (CKI: Pin 63) of this IC supports TTL level input. In addition, two modes can be set: a mode in which the CKI is used as is for the internal master clock (SLCK (Pin 64): L) and a mode in which CKI is halved using the internal frequency divider (SLCK: H). In the latter mode, all internal operation is at 1/2 clock, so "clock" in the description below refers to this 1/2 clock when SLCK is H. Internal operation is at a frequency up to 41 MHz, so when inputting a clock faster than this to CKI1, be sure to set SLCK to H. selector D Q XQ CKI b a Internal master clock (41MHz or less) s SLCK HSYNC, VST, HST Input a standard horizontal sync signal to the input HSYNC (Pin 60). At this time, the input polarity is not fixed and is set by the serial data setting HSYNCPOL. In addition, make sure the VST and HST pulses satisfy the following phase relationship. However, when not using pulse eliminator display, HST (Pin 4) can be fixed to H level. Normally input the VST pulse to the LCD panel for the VST input. HSYNC toVst VST toHst HST toDisp Blanking portion Video signal toVst: VST shall rise 20 clocks or more after the front edge of HSYNC, and after the HST pulse. toHst: The front edge of HST shall follow the rear edge of HSYNC toDisp: There shall be 1.5H or more from the rise of VST to the start of the video signal. The Sony timing generator ICs (CXD2464R, CXD3500R) pulses of the same name satisfy the above conditions. System clear pin input Set the system clear pin (XCLR: Pin 61) to L and apply a forced reset in order to initialize the internal circuits during power-on. – 10 – CXD3503R Description of Output Correction Signal Operation Horizontal direction The correction data set in the SRAM by serial transfer is arithmetically processed inside the IC to determine the output position corresponding to the value set by serial register HP7 to 0 using the front edge of HSYNC as the reference. Interpolation is not performed for the horizontal direction, and interpolated data is output at the cycle set by serial register HINT7 to 0 for the vertical direction. In addition, the maximum amplitude of the correction signal output voltage is determined by VRH (Pin 44) and VRL (Pin 40). The internal DAC outputs at the resistive potential division (VRH to VRL: 213Ω typ.), so be sure to input to VRH and VRL via buffers having current capacity. HSYNC DACKO/I Set by HP7 to 0 Set by HINT7 to 0 DOUT VRH DACO VRL The internally generated digital data DOUT is input to the internal D/A converter, latched by the D/A converter clock input from DACKI, and output from DACO2, 1 and 0 as an analog signal. Note) If edges remain, these level differences may appear as vertical stripes. Therefore, when using this as a correction signal, be sure to eliminate the edges using an LPF, etc. before input to the CXA2111R or CXA2112R. Vertical direction The vertical correction points set in the SRAM are arithmetically processed inside the IC to output interpolated data for the lines other than correction points. n fm, n m 1 fm, n + a (fm + 1, n – fm, n) 2 fm, n + a (fm + 1, n – fm, n) n+1 fm + 1, n 1 fm, n + 1 + a (fm + 1, n + 1 – fm, n + 1) 2 fm, n + 1 + a (fm + 1, n + 1 – fm, n + 1) VINT line(s) a' lines m+1 fm, n + a–1 a (fm + 1, n – fm, n) fm + 1, n fm, n + 1 + a–1 a (fm + 1, n + 1 – fm, n + 1) fm + 1, n + 1 Vertical correction point interval Set by VINT4 to 0 and ANM5 to 0 Assuming ANM5 to 0 = a, a' = VINT × a fm, n: Correction data for point (m, n) – 11 – CXD3503R Serial Transfer Operation Control method The operation timing of this IC is controlled by serial data. The control data is divided into 8-bit units. The first 8 bits are the main address, the next 8 bits are the sub address, and the subsequent data is 8-bit data blocks. The main address specifies which of the blocks in the table below are to be set. Data is set in the blocks indicated by "1", so if the main address is set to "0F", the subsequent data is set in all data blocks. In addition, the value set in the sub address sets the initial write address in the block specified by the main address. Thereafter, the write address is incremented by +1 while SCTR is L for each 8 bits of data from the address set by the sub address. This makes it possible to set only the necessary data from an optional address. The data set by serial register INIT5 to 0 is output in place of the correction data during serial transfer. SCTR SCLK SDAT M7 M6 M5 M4 M3 M2 M1 M0 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D7’ D6’ D5’ D4’ D3’ D2’ D1’ D0’ D7’ D6’ D5’ D4’ D3’ D2’ D1’ D0’ main addr. sub addr. data data data Main address table Main address 01h 02h 04h 08h Setting block Correction point data 0 (SRAM0) Correction point data 1 (SRAM1) Correction point data 2 (SRAM2) Timing control data The SRAM numbers 0, 1 and 2 correspond to the DAC output DACO numbers 0, 1 and 2. The correction point data set in the SRAM is reflected to the outputs of the corresponding numbers. Correction point data 0, 1 and 2 Correction point data is set in the 6-bit × 208 words (16 horizontal points, 13 vertical points) SRAM. The set correction data undergoes vertical interpolation and other arithmetic processing, and is then reflected to the DACO0, 1 and 2 outputs, respectively. The correction point data is 6 bits, and is set in D5, 4, 3, 2, 1 and 0. Setting to D7 and 6 is invalid. See the figure on page 13 for the relationship between the correction point data position and the SRAM address. Example) When the main address is set to 04 and the sub address is set to 08, data is written from address 08 of correction point data 2 (SRAM2), then the address is automatically incremented and written to the SRAM. – 12 – CXD3503R Timing control data Main address 08h Sub address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h D7 HB3 VB3 HP7 HINT7 — — — — HSOFF STBY1 D6 HB2 VB2 HP6 HINT6 — — — 1/A6 HPOL STBY0 D5 HB1 VB1 HP5 HINT5 — — ANM5 1/A5 VSPOL INIT5 D4 HB0 VB0 HP4 HINT4 — VINT4 ANM4 1/A4 DWN INIT4 D3 HE3 VE3 HP3 HINT3 VP3 VINT3 ANM3 1/A3 RGT INIT3 D2 HE2 VE2 HP2 HINT2 VP2 VINT2 ANM2 1/A2 D1 HE1 VE1 HP1 HINT1 VP1 VINT1 ANM1 1/A1 D0 HE0 VE0 HP0 HINT0 VP0 VINT0 ANM0 1/A0 DACKP2 DACKP1 DACKP0 INIT2 INIT1 INIT0 —: Setting invalid Data settings HB3 to 0, HE3 to 0, VB3 to 0, VE3 to 0 These set the range of the correction point data to be used. Expressed in model format, the correction points appear as shown in the figure below. To use only the shaded area, set HB: 2, HE: D, VB: 1 and VE: B. Normally set HB: 0, HE: F, VB: 0 and VE: D (16 × 13). Horizontal direction Address 00 Specified by HB Specified by HE 0F Specified by VB Vertical direction Specified by VE C0 CF Dots in the lattice above represent correction points, and the white circles are the data settings. – 13 – CXD3503R HP7 to 0 This sets the correction signal output start position in the horizontal direction. The timing until the start of correction signal output is set using the front edge of HSYNC as the reference. However, do not set HP7 to 0 to a value of 54 or less, as the arithmetically processed correction signal may not be output correctly in this case. In addition, the waveform may be disturbed by the HP and HINT values and the VST phase. In these cases, eliminate the disturbance by adjusting the HP and DACKO phase. Set by HP7 to 0 HSYNC DACO HINT7 to 0 This sets the correction point interval in the horizontal direction. Normally, when using 16 points in the horizontal direction, calculate the number of clocks at which the horizontal period can be divided into 16 sections taking into account the input clock and the system clock speed, and then set this value – 1. However, do not input a value of 11 or less to HINT7 to 0, as the internal arithmetic processing may not be able to keep up and the correct value may not be output in this case. Example 1) Inputting a dot clock 40MHz signal to a SVGA panel (800 × 600) If 1/2 the dot clock is input as the master clock and the mode without internal 1/2 frequency division (SLCK: L) is used: HINT = (800 ÷ 16 ÷ 2) – 1 = 24 Example 2) Inputting a dot clock 65MHz signal to a XGA panel (1024 × 768) If 1/2 the dot clock is input as the master clock and the mode with internal 1/2 frequency division (SLCK: H) is used: HINT = (1024 ÷ 16 ÷ 4) – 1 = 15 Set by HINT Internal clock DACO fm, n fm, n + 1 HINT = 15 – 14 – CXD3503R VP3 to 0 This sets the correction signal output start position in the vertical direction. The number of line counted from the front edge of the VST pulse at which vertical arithmetic processing of the correction signal starts is set. The correction data for the initial line is output continuously only for the number of lines set by VP. VINT4 to 0 This sets the arithmetic processing interval for vertical correction. Vertical correction arithmetic processing is performed every number of lines set by VINT. Normally set arithmetic processing for each line (VINT = 1). ANM5 to 0 This sets the correction point interval in the vertical direction. There are 13 vertical correction points with respect to the actual panel display area switching, so this sets the number of lines at which correction points are spaced for the internal arithmetic processing. Example) To use the full correction point data in the vertical direction, set the correction point interval ANM as follows. SVGA panels: ANM = 600 ÷ 12 = 50 (110010) XGA panels: ANM = 76 ÷ 12 = 64 (000000) 1/A6 to 0 This sets the inverse of ANM. Set the 6th to 12th digits below the decimal point in binary format with 7 bits. Linear interpolation with an accuracy of 1 bit is performed using this setting value. Example) ANM = 50: 1/50 (decimal) = 0.000001010010 (binary) Set the 6th to 12th digits. Example) ANM = 64: 1/64 (decimal) = 0.000001000000 (binary) Set the 6th to 12th digits. VST HSYNC DACO 0 VP 0 0 0 1 1 2 2 ANM – 1 ANM – 1 0’ 0’ VINT VINT ANM VINT VINT – 15 – CXD3503R HSOFF This is the correction ON/OFF setting. When H, correction is on; when L, correction is off and the INIT5 to 0 data is output constantly. Normally set HSOFF to H. HPOL This sets the HSYNC input signal polarity. Set HPOL to H for positive polarity, and to L for negative polarity. Be sure to set the polarity correctly in accordance with the input signal. VSPOL This sets the VST input signal polarity. Set VSPOL to H for positive polarity, and to L for negative polarity. Be sure to set the polarity correctly in accordance with the input signal. The Sony timing generator ICs CXD2464R and CXD3500R output an inverse polarity VST pulse for up/down inverse drive of a SVGA panel. Therefore, take special care for the VST polarity when using this IC with a SVGA panel. DWN, RGT DWN and RGT set up/down and right/left inversion, respectively. Normal scan is supported when DWN is H and RGT is H, and up/down and/or right/left inversion of the panel is supported by reading the correction data set in the RAM in the reverse order when these are set to L, respectively. These settings can be controlled from the external pins of the same name DWN (Pin 5) and RGT (Pin 6) by setting CTRL (Pin 7) to H. In this case these serial settings are invalid. DACKP2 to 0 This sets the DAC clock phase. Normally set to "2" to satisfy the internal DAC clock and data setup/hold specifications. STBY1 and 0 This is the standby setting. Standby mode results when STBY1, 0 are set to H, L. At this time, the internal clock is supplied only to the serial interface block, and operation of all other blocks is stopped. Buffer outputs AOUT2, 1 and 0 and digital outputs DOUT25 to 20, 15 to 10 and 05 to 00 are all high impedance at this time. INIT5 to 0 This sets the DACO output level when correction is off. When serial data HSOFF is set to L, the data for this setting is output regardless of the correction data set in the RAM. – 16 – Timing Chart 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 MCK HSYNC Effective video signal HINT HP D20 D21 D22 D23 D24 (BLK) DACKO (I) DOUT25 to 20 D10 D00 D01 D11 D12 D02 DOUT15 to 10 D13 D03 D14 D04 DOUT05 to 00 – 17 – D20 D21 D10 D11 D00 D01 VRH D22 DACO2 VRL D23 D24 VRH D12 D13 D14 DACO2 VRL VRH D02 D03 D04 DACO2 VRL CXD3503R CXD3503R Application Circuit To CXA2111R Bright pins (Pins 30, 31 and 32) LPF LPF LPF Analog 5V Digital 5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AOUT0 BFIN0 DACO0 AVDD AOUT1 BFIN1 DACO1 AVSS VRH VRL AOUT2 BFIN2 DACO2 DVSS1 DVDD1 OLIM DACKI 32 DACKO 31 DOUT25 30 DOUT24 29 DOUT23 28 DOUT22 27 DOUT21 26 DOUT20 25 CXD3503R DVDD0 24 DOUT15 23 DOUT14 22 DOUT13 21 DOUT12 20 DOUT11 19 DOUT10 18 DVSS0 17 DOUT00 DOUT01 DOUT02 DOUT03 DOUT04 DOUT05 TEST0 TEST1 TEST2 CTRL 7 DWN 5 RGT 6 49 DVSS2 50 NC 51 NC 52 NC 53 NC 54 NC 55 NC 56 DVDD2 57 SCTR Serial I/F 10k 1µ/16V 58 SCLK 59 SDAT 60 HSYNC 61 XCLR 62 DVSS3 63 CKI1 From PLL CXA3106(A)Q 64 SLCK 1 2 3 HST 4 VST NC NC 8 9 10 11 12 13 14 15 16 From TG CXD3500R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 18 – CXD3503R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 10.0 ± 0.2 48 49 33 32 0.15 ± 0.05 0.1 A 64 17 1 1.25 0.5 + 0.08 0.18 – 0.03 16 1.7 MAX 0.1 M 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 (0.5) PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L061 LQFP064-P-1010-AY – 19 –