CXD3504R

CXD3504R Selective Delay Line for LCD Description The CXD3504R is a selective delay line IC for performing signal processing during dot and line inverted drive of liquid crystal panels for Sony projectors. This chip has three built-in 10-bit × 1200-word 1H delay lines, and data path with or without a 1H delay can be selected by the control pins. Features • Supports dot and line inverted drive of liquid crystal panels for Sony projectors • Three built-in 10-bit × 1200-word 1H delay lines • Data path with or without a 1H delay can be selected by the control pins. Applications LCD projectors, etc. Structure Silicon gate CMOS IC 176 pin LQFP (Plastic) Absolute Maximum Ratings (Vss = 0V) • Supply voltage VDD –0.3 to +4.6 V • Input voltage VI –0.3 to VDD + 0.3 V • Output voltage VO –0.3 to VDD + 0.3 V • Operating temperature Topr –30 to +75 °C • Storage temperature Tstg –55 to +125 °C • Allowable power dissipation PDmax 850mW (Ta ≤ 75°C) Recommended Operating Conditions • Supply voltage VDD 3.0 to 3.6 • Operating temperature Topr –30 to +75 • Input voltage VIN 0 to VDD V °C V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99815-PS CXD3504R Block Diagram R1OUT9 R1OUT8 R1OUT7 R1OUT6 R1OUT5 R1OUT4 R1OUT3 R1OUT2 R1OUT1 R1OUT0 R2OUT9 R2OUT8 R2OUT7 R2OUT6 R2OUT5 TEST3 R2IN0 R2IN1 R2IN2 R2IN3 R2IN4 R2IN5 R2IN6 R2IN7 R2IN8 R2IN9 R1IN0 R1IN1 R1IN2 R1IN3 R1IN4 R1IN5 R1IN6 R1IN7 R1IN8 R1IN9 VDD VDD VDD VDD VSS VSS VSS 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS 88 VDD 87 R2OUT4 86 R2OUT3 85 R2OUT2 84 R2OUT1 83 R2OUT0 82 VSS 81 VDD 80 TEST2 79 G1OUT9 78 G1OUT8 77 G1OUT7 76 G1OUT6 75 G1OUT5 74 VSS 73 VDD 72 G1OUT4 71 G1OUT3 70 G1OUT2 69 G1OUT1 68 G1OUT0 67 VSS 66 VDD 65 G2OUT9 64 G2OUT8 63 G2OUT7 62 G2OUT6 61 G2OUT5 60 VSS 59 VDD 58 G2OUT4 57 G2OUT3 56 G2OUT2 55 G2OUT1 54 G2OUT0 53 VSS 52 VDD 51 TEST1 50 B1OUT9 49 B1OUT8 48 B1OUT7 47 B1OUT6 46 B1OUT5 45 VSS VDD VSS 133 G1IN9 134 G1IN8 135 G1IN7 136 G1IN6 137 G1IN5 138 G1IN4 139 G1IN3 140 G1IN2 141 G1IN1 142 G1IN0 143 G2IN9 144 G2IN8 145 G2IN7 146 G2IN6 147 G2IN5 148 G2IN4 149 G2IN3 150 G2IN2 151 G2IN1 152 G2IN0 153 VDD 154 VSS 155 B1IN9 156 B1IN8 157 B1IN7 158 B1IN6 159 B1IN5 160 B1IN4 161 B1IN3 162 B1IN2 163 B1IN1 164 B1IN0 165 B2IN9 166 B2IN8 167 B2IN7 168 B2IN6 169 B2IN5 170 B2IN4 171 B2IN3 172 B2IN2 173 B2IN1 174 B2IN0 175 VDD 176 CLK SEL TIMING GENERATOR B CH FIFO INPUT LATCH & SELECT G CH FIFO OUTPUT SELECT & LATCH R CH FIFO 1 VSS 2 PECLCK 3 NC 4 CMOSCK 5 VSS 6 CLKSEL 7 SELRA 8 SELGA 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 XCLR HD HDSEL HDEDGE NC REDGE GEDGE BEDGE POLSLA NC NC B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 B2OUT5 B2OUT6 B2OUT7 B2OUT8 B2OUT9 B1OUT0 B1OUT1 B1OUT2 B1OUT3 B1OUT4 SELBA TEST0 SELB VSS VSS VDD VDD VDD VSS –2– CXD3504R Pin Configuration R1OUT9 R1OUT8 R1OUT7 R1OUT6 R1OUT5 R1OUT4 R1OUT3 R1OUT2 R1OUT1 R1OUT0 R2OUT9 R2OUT8 R2OUT7 R2OUT6 R2OUT5 TEST3 R2IN0 R2IN1 R2IN2 R2IN3 R2IN4 R2IN5 R2IN6 R2IN7 R2IN8 R2IN9 R1IN0 R1IN1 R1IN2 R1IN3 R1IN4 R1IN5 R1IN6 R1IN7 R1IN8 R1IN9 VDD VDD VDD VDD VSS VSS VSS 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS 133 G1IN9 134 G1IN8 135 G1IN7 136 G1IN6 137 G1IN5 138 G1IN4 139 G1IN3 140 G1IN2 141 G1IN1 142 G1IN0 143 G2IN9 144 G2IN8 145 G2IN7 146 G2IN6 147 G2IN5 148 G2IN4 149 G2IN3 150 G2IN2 151 G2IN1 152 G2IN0 153 VDD 154 VSS 155 B1IN9 156 B1IN8 157 B1IN7 158 B1IN6 159 B1IN5 160 B1IN4 161 B1IN3 162 B1IN2 163 B1IN1 164 B1IN0 165 B2IN9 166 B2IN8 167 B2IN7 168 B2IN6 169 B2IN5 170 B2IN4 171 B2IN3 172 B2IN2 173 B2IN1 174 B2IN0 175 VDD 176 VSS 88 VDD 87 R2OUT4 86 R2OUT3 85 R2OUT2 84 R2OUT1 83 R2OUT0 82 VSS 81 VDD 80 TEST2 79 G1OUT9 78 G1OUT8 77 G1OUT7 76 G1OUT6 75 G1OUT5 74 VSS 73 VDD 72 G1OUT4 71 G1OUT3 70 G1OUT2 69 G1OUT1 68 G1OUT0 67 VSS 66 VDD 65 G2OUT9 64 G2OUT8 63 G2OUT7 62 G2OUT6 61 G2OUT5 60 VSS 59 VDD 58 G2OUT4 57 G2OUT3 56 G2OUT2 55 G2OUT1 54 G2OUT0 53 VSS 52 VDD 51 TEST1 50 B1OUT9 49 B1OUT8 48 B1OUT7 47 B1OUT6 46 B1OUT5 45 VSS VDD 1 VSS 2 PECLCK 3 NC 4 CMOSCK 5 VSS 6 CLKSEL 7 SELRA 8 SELGA 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 XCLR HD HDSEL NC NC NC B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 B2OUT5 B2OUT6 B2OUT7 B2OUT8 B2OUT9 B1OUT0 B1OUT1 B1OUT2 B1OUT3 B1OUT4 SELBA HDEDGE REDGE GEDGE BEDGE POLSLA TEST0 SELB VDD VSS VDD VSS VDD VSS –3– CXD3504R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol VSS PECLCK NC CMOSCK VSS CLKSEL SELRA SELGA SELBA SELB XCLR HD HDSEL HDEDGE NC REDGE GEDGE BEDGE POLSLA NC NC VDD VSS B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 VDD VSS B2OUT5 B2OUT6 B2OUT7 P P O O O O O P P O O O Power supply GND B2 output B2 output B2 output B2 output B2 output Power Supply GND B2 output B2 output B2 output I I I I I P I I I I I I I I I CMOS clock input∗2 GND 0: PECL, 1: CMOS SELA (Data path selection A) for R SELA (Data path selection A) for G SELA (Data path selection A) for B Data path selection B 0: Direct Reset Horizontal sync signal input HD selection (0: ↓, 1: ↑) CK trigger selection of HD (0: ↓, 1: ↑) Reserve CK trigger selection of R (0: ↓, 1: ↑) CK trigger selection of G (0: ↓, 1: ↑) CK trigger selection of B (0: ↓, 1: ↑) SELA polarity selection L L L L L L L L L L L H I/O P I GND Very little amp. clock input∗1 Description Input pin for open status ∗1 Connect to GND or VDD when using CMOS clock. ∗2 Connect to GND or VDD when using small amplitude clock. –4– CXD3504R Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol B2OUT8 B2OUT9 VDD VSS B1OUT0 B1OUT1 B1OUT2 B1OUT3 B1OUT4 TEST0 VDD VSS B1OUT5 B1OUT6 B1OUT7 B1OUT8 B1OUT9 TEST1 VDD VSS G2OUT0 G2OUT1 G2OUT2 G2OUT3 G2OUT4 VDD VSS G2OUT5 G2OUT6 G2OUT7 G2OUT8 G2OUT9 VDD VSS G1OUT0 I/O O O P P O O O O O I P P O O O O O I P P O O O O O P P O O O O O P P O B2 output B2 output Power supply GND B1 output B1 output B1 output B1 output B1 output 1: Test mode Power supply GND B1 output B1 output B1 output B1 output B1 output 1: Test mode Power supply GND G2 output G2 output G2 output G2 output G2 output Power supply GND G2 output G2 output G2 output G2 output G2 output Power supply GND G1 output Description Input pin for open status L L –5– CXD3504R Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Symbol G1OUT1 G1OUT2 G1OUT3 G1OUT4 VDD VSS G1OUT5 G1OUT6 G1OUT7 G1OUT8 G1OUT9 TEST2 VDD VSS R2OUT0 R2OUT1 R2OUT2 R2OUT3 R2OUT4 VDD VSS R2OUT5 R2OUT6 R2OUT7 R2OUT8 R2OUT9 TEST3 VDD VSS R1OUT0 R1OUT1 R1OUT2 R1OUT3 R1OUT4 VDD VSS I/O O O O O P P O O O O O I P P O O O O O P P O O O O O I P P O O O O O P P G1 output G1 output G1 output G1 output Power supply GND G1 output G1 output G1 output G1 output G1 output 1: Test mode Power supply GND R2 output R2 output R2 output R2 output R2 output Power supply GND R2 output R2 output R2 output R2 output R2 output 1: Test mode Power supply GND R1 output R1 output R1 output R1 output R1 output Power supply GND Description Input pin for open status L L –6– CXD3504R Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Symbol R1OUT5 R1OUT6 R1OUT7 R1OUT8 R1OUT9 VDD VSS R1IN9 R1IN8 R1IN7 R1IN6 R1IN5 R1IN4 R1IN3 R1IN2 R1IN1 R1IN0 R2IN9 R2IN8 R2IN7 R2IN6 R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 R2IN0 VDD VSS G1IN9 G1IN8 G1IN7 G1IN6 G1IN5 G1IN4 G1IN3 I/O O O O O O P P I I I I I I I I I I I I I I I I I I I I P P I I I I I I I R1 output R1 output R1 output R1 output R1 output Power supply GND R1 input R1 input R1 input R1 input R1 input R1 input R1 input R1 input R1 input R1 input R2 input R2 input R2 input R2 input R2 input R2 input R2 input R2 input R2 input R2 input Power supply GND G1 input G1 input G1 input G1 input G1 input G1 input G1 input Description Input pin for open status –7– CXD3504R Pin No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Symbol G1IN2 G1IN1 G1IN0 G2IN9 G2IN8 G2IN7 G2IN6 G2IN5 G2IN4 G2IN3 G2IN2 G2IN1 G2IN0 VDD VSS B1IN9 B1IN8 B1IN7 B1IN6 B1IN5 B1IN4 B1IN3 B1IN2 B1IN1 B1IN0 B2IN9 B2IN8 B2IN7 B2IN6 B2IN5 B2IN4 B2IN3 B2IN2 B2IN1 B2IN0 VDD I/O I I I I I I I I I I I I I P P I I I I I I I I I I I I I I I I I I I I P G1 input G1 input G1 input G2 input G2 input G2 input G2 input G2 input G2 input G2 input G2 input G2 input G2 input Power supply GND B1 input B1 input B1 input B1 input B1 input B1 input B1 input B1 input B1 input B1 input B2 input B2 input B2 input B2 input B2 input B2 input B2 input B2 input B2 input B2 input Power supply Description Input pin for open status –8– CXD3504R Electrical Characteristics Item High level input voltage Low level input voltage Symbol VIH VIL (Input/Output level/VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C) Conditions CMOS input IOH = –12mA IOL = 12mA VI = VSS, VDD Min. 0.7VDD — VDD – 0.8 — –10 80 90 Typ. — — — — — 160 180 Max. — 0.2VDD — 0.4 10 320 360 Unit V V V V µA kΩ kΩ ∗1, ∗2, ∗3 ∗2 ∗3 ∗4 Applicable pins ∗1, ∗2, ∗3 High level output voltage VOH Low level output voltage Input leak current Pull-up resistor Pull-down resistor ∗1 ∗2 ∗3 ∗4 VOL IIL RUP RDN Input pins except PECLCK XCLR CLKSEL, SELRA, SELGA, SELBA, SELB, HDSEL, HDEDGE, REDGE, GEDGE, BEDGE, POLSLA All output pins AC Characteristics PECLCK (CMOSCK) t1 t2 HD t3 t4 Input Data (R, G, B ) d in 99b d in 100b d in 1c d in 2c d in 3c d in 4c d in 5c d in 6c d in 7c d in 8c d in 9c d in 10c d in 11c d in 12c d in 13c t5 

,,  d in 96b d in 97b d in 98b d in 99b d in 100b No Care d in 4c d in 5c d in 6c d in 96a d in 97a d in 98a d in 99a d in 100a No Care d in 4b d in 5b d in 6b Through Output d in 95b d in 7c d in 8c d in 9c Delay Output d in 95a d in 7b d in 8b d in 9b Item Input frequency Symbol f Min. — Max. 80 — — — — 13 — — — — 12 Unit MHz ns ns ns ns ns ns ns ns ns ns HD set-up time to PECLCK bar t1 t2 t3 t4 t5 t1 t2 t3 t4 t5 1.5 4.5 1 6.5 4 2 3 1.5 4.5 3 HD hold time from PECLCK bar R, G, B input data set-up time to PECLCK bar R, G, B input data hold time from PECLCK bar R, G, B output data delay from PECLCK HD set-up time to CMOSCK bar HD hold time from CMOSCK bar R, G, B input data set-up time to CMOSCK bar R, G, B input data hold time from CMOSCK bar R, G, B output data delay from CMOSCK Note: The above timing values are for PECCLK (CMOSCK) = 80MHz and an output pin capacitance of 20pF. –9– CXD3504R Description of Operation 1) The following describes only R, but the operation for G and B is the same. SELRA:SELB = 0:0 R2IN → through → R1OUT R1IN → delay → R2OUT SELRA:SELB = 0:1 R2IN → delay → R1OUT R1IN → through → R2OUT SELRA:SELB = 1:0 R1IN → through → R1OUT R2IN → delay → R2OUT SELRA:SELB = 1:1 R1IN → delay → R1OUT R2IN → through → R2OUT However, POLSLA = 0 2) Be sure to set XCLR to "0" for a clock or more while HD is "1". (when HDSEL = 0) Also, input the HD signal with a "0" period length of 6 clocks or more. Very Little Signal Amplifier (VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C) Item High level input voltage Low level input voltage Input frequency Input amplitude∗1 Symbol VIH VIL f Vpp Min. 0.4 0 — 0.4 Typ. — — — — Max. 3.6 3.2 80 — Unit V V MHz V Applicable pins: PECLCK (Pin 2) ∗1 Input the signal through a capacitor. Also, this amplitude is the value between the through capacitor and the input pin. PECLCK 2 – 10 – CXD3504R Application Circuit From CXD2467Q 3.3V 0.1µ 0.1µ 0.1µ 0.1µ 10µ/16V 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 R1OUT5 R1OUT0 R1OUT6 R1OUT1 R1OUT7 R1OUT2 R1OUT8 R1OUT3 R1OUT9 R1OUT4 R2OUT9 R2OUT8 R2OUT7 R2OUT6 R2OUT5 R2IN0 R2IN1 R2IN2 R2IN3 R2IN4 R2IN5 R2IN6 R2IN7 R2IN8 R2IN9 R1IN0 R1IN1 R1IN2 R1IN3 R1IN4 R1IN5 R1IN6 R1IN7 R1IN8 R1IN9 TEST3 VDD VDD VDD VDD VSS VSS VSS VSS 0.1µ 133 VSS 134 G1IN9 135 G1IN8 136 G1IN7 137 G1IN6 138 G1IN5 139 G1IN4 140 G1IN3 141 G1IN2 142 G1IN1 143 G1IN0 144 G2IN9 145 G2IN8 146 G2IN7 147 G2IN6 148 G2IN5 149 G2IN4 150 G2IN3 151 G2IN2 152 G2IN1 153 G2IN0 154 VDD 0.1µ 155 VSS 156 B1IN9 157 B1IN8 158 B1IN7 159 B1IN6 160 B1IN5 161 B1IN4 162 B1IN3 163 B1IN2 164 B1IN1 165 B1IN0 166 B2IN9 167 B2IN8 168 B2IN7 169 B2IN6 170 B2IN5 171 B2IN4 172 B2IN3 173 B2IN2 174 B2IN1 VDD 88 R2OUT4 87 R2OUT3 86 R2OUT2 85 R2OUT1 84 R2OUT0 83 VSS 82 VDD 81 TEST2 80 G1OUT9 79 G1OUT8 78 G1OUT7 77 G1OUT6 76 G1OUT5 75 VSS 74 VDD 73 G1OUT4 72 G1OUT3 71 G1OUT2 70 G1OUT1 69 G1OUT0 68 VSS 67 VDD 66 G2OUT9 65 G2OUT8 64 G2OUT7 63 G2OUT6 62 G2OUT5 61 VSS 60 VDD 59 G2OUT4 58 G2OUT3 57 G2OUT2 56 G2OUT1 55 G2OUT0 54 VSS 53 VDD 52 TEST1 51 B1OUT9 50 B1OUT8 49 B1OUT7 48 B1OUT6 47 CMOSCK PECLCK HDEDGE B2OUT3 B2OUT4 POLSLA B2OUT2 B2OUT9 B1OUT2 B2OUT1 B2OUT6 B2OUT8 B2OUT0 B2OUT5 B2OUT7 B1OUT0 CLKSEL B1OUT1 SELGA HDSEL SELRA SELBA B1OUT3 GEDGE REDGE BEDGE B1OUT4 B1OUT5 46 TEST0 VDD VSS 45 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 175 B2IN0 VSS 176 VDD 0.1µ XCLR SELB VDD VDD VSS VSS VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 0.1µ 0.1µ 0.1µ VSS NC HD NC NC NC 0.1µ 0.1µ To CXA3197R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – CXD3504R Package Outline Unit: mm 176PIN LQFP(PLASTIC) 26.0 ± 0.2 24.0 ± 0.2 132 133 89 88 1.6 MAX (1.4) 0.1 A 176 1 0.5 44 0.1 M 45 + 0.05 0.2 – 0.04 + 0.07 0.125 – 0.02 0.1 ± 0.1 0 ° to 10 ° DETAIL A SONY CODE EIAJ CODE JEDEC CODE LQFP-176P-L061 P-LQFP176-24X24-0.5 0.5 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 1.8 g – 12 – Sony Corporation