CXD3519

CXD3519TQ Reference Voltage and Driver IC for LCD Description The CXD3519TQ is suitable IC for applying reference voltage for gamma correction which is necessary for TFT liquid crystal display. This IC has a built-in 9 channels of rail-to-rail buffer circuit which enables 2-input switch and a common driver circuit. Features • Built-in 9 channels of rail-to-rail buffer circuit • Built-in common driver circuit • Current consumption: 3.6mA (typ.) • Package: 48-pin TQFP Structure CMOS IC Applications Small liquid crystal monitor 48 pin TQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS – 0.3 to +6.0 V • Input pin voltage VI VSS – 0.3 to VDD + 0.3 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation (Ta ≤ 85°C) 220 mW PD Operating Conditions • Supply voltage VDD 4.5 to 5.5 (5.0 typ.) • Operating temperature Topr –35 to +85 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00Y07-PS CXD3519TQ Block Diagram VH4 VH5 VH6 VH7 VH8 26 VL4 VL5 VL6 VL7 VL8 NC 36 NC 37 GND 38 V6 39 V5 40 V4 41 NC 42 VDD 43 V1 44 V0 45 GND 46 35 34 33 32 31 30 29 28 27 25 24 NC 23 GND 22 V7 21 V8 20 NC 19 VDD 18 V2 17 V3 16 GND 15 VDD buff 14 COMOUT 13 NC NC 47 NC 48 1 VH3 2 VL3 3 VH2 4 VL2 5 VH1 6 VL1 7 VH0 8 VL0 9 SW 10 SW 11 GND 12 NC –2– NC CXD3519TQ Pin Description Pin No. 1 2 3 4 5 6 7 8 26 27 28 29 30 31 32 33 34 35 45 44 18 39 22 21 17 41 40 Symbol VH3 VL3 VH2 VL2 VH1 VL1 VH0 VL0 VH8 VL8 VH7 VL7 VH6 VL6 VH5 VL5 VH4 VL4 V0 V1 V2 V6 V7 V8 V3 V4 V5 VDD VDD VL 2 27 4 29 6 31 8 33 35 VH 1 26 3 28 5 30 7 32 34 VDD Pin voltage 0.5 to 4.0V (max.: 2.0Vp-p) Equivalent circuit Description DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. DC input when SW is high. DC input when SW is low. V0 output. V1 output. V2 output. V6 output. V7 output. V8 output. V3 output. V4 output. V5 output. Input switch. For V0 to V8 output, VL is output for low; VH for high. For COMOUT output, VDD level is output for low; GND level for high. Also, Pins 9 and 10 are connected internally. Input the same signal, or input one signal and leave the other signal open. 0.2 to 4.8V 0.5 to 4.0V (max.: 2.0Vp-p) GND 0.2 to 4.8V 17 39 18 40 21 41 22 44 45 0.5 to 4.0V GND 9 SW 9 10 10 SW GND –3– CXD3519TQ Pin No. Symbol Pin voltage Equivalent circuit VDD Description 14 COMOUT COMOUT 14 COM output. GND 15 19 43 11 16 23 38 46 12 13 20 24 25 36 37 42 47 48 VDD VDD VDD GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC 5.0V 5.0V 5.0V 5V power supply. 5V power supply. 5V power supply. GND. GND. GND. GND. GND. No connected. No connected. No connected. No connected. No connected. No connected. No connected. No connected. No connected. No connected. Note) • GND Make sure that Pins 11, 16, 23, 38 and 46 are connected to GND potential, and do not release them. • Decoupling capacitor Locate decoupling capacitor connected between power supply and GND as near IC pin as possible. • Design VH and VL input pins not to have capacity. –4– CXD3519TQ Electrical Characteristics (Ta = 25°C, VDD = 5V) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Item Current consumption VH, VL input current high VH, VL input current low SW input current high SW input current low VREF voltage gain SW input voltage high SW input voltage low VREF output voltage high VREF output voltage low COMOUT output voltage low VREF offset voltage VREF (V0, 1, 2, 6, 7, 8) load regulation 1 VREF (V3, 4, 5) load regulation 2 Setting time 1 Setting time 2 Output impedance Symbol ICC IIH IIL IISH IISL AV VIH VIL VOH VOL VCOL VOFF ∆VO1 Input voltage = 0.2 to 4.8V ISOURCE = 10mA ISINK = 10mA Input voltage = 0.5 to 4.0V ISOURCE = 10mA ISINK = 10mA Measurement circuits 1, 2 Measurement circuit 3 V0 – V8 ISOURCE = 10mA ISINK = 10mA ISOURCE = 10mA ISINK = 10mA Conditions Input voltage = 2.5V, No load Min. — –0.1 –0.1 –10 –10 0.985 2.0 — VDD – 1.0 — VDD – 0.1 — — — Typ. 3.6 — — — — — — — — — — — — ±5 Max. 6.0 0.1 0.1 10 10 — — 0.8 — GND + 1.0 — GND + 0.1 20 ±10 Unit mA µA µA µA µA V/V V V V V V V mV mV Input voltage = 4.8V Input voltage = 0.2V Input voltage = 5V Input voltage = 0V Input voltage = 0.2 to 4.8V COMOUT output voltage high VCOH 15 ∆VO2 ts1 ts2 ts3 ts4 Rimp — ±7 ±14 mV 16 17 18 — — — — — 15 10 6 — µs µs Ω –5– CXD3519TQ Measurement Circuits Measurement circuit 1 VH 4.8V 0.2V VL 15Ω Measurement point V0, V1, V2, V6, V7, V8 30nF Measurement circuit 2 VH 4.0V (max.) 2.0Vp-p (max.) V3, V4, V5 0.5V (min.) VL 30nF 15Ω Measurement point Measurement circuit 3 5.0V 0V V0, COMOUT 15Ω Measurement point 30nF SW 50% 50% 90% Output (V0 to V8) 10% ts1 ts2 10% Output (VCOM) 90% ts3 ts4 –6– CXD3519TQ Application Circuit 5V 47µ 0.01µ 36 37 38 To LCD To LCD To LCD 39 40 41 42 43 To LCD To LCD 44 45 46 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 buff 47µ 14 13 To LCD (VCOM) 0.01µ To LCD To LCD To LCD To LCD 47 48 1 2 3 4 5 6 7 8 9 10 11 12 Polarity inverted pulse Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –7– CXD3519TQ Package Outline Unit: mm 48PIN TQFP (PLASTIC) 9.0 ± 0.2 7.0 ± 0.1 36 25 1.2 MAX (1.0) 0.1 37 24 A 48 13 1 0.5 12 + 0.1 0.2 – 0.05 0.1 M + 0.07 0.125 – 0.02 0.1 ± 0.1 0˚ to 10˚ DETAIL A 0.5 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.15g SONY CODE EIAJ CODE JEDEC CODE TQFP-48P-L061 P-TQFP48-7X7-0.5 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS LEAD SPECIFICATIONS ITEM LEAD MATERIAL LEAD TREATMENT LEAD TREATMENT THICKNESS SPEC. COPPER ALLOY Sn-Pb 10% 5-18µm –8– Sony Corporation