CXD3607R

CXD3607R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD3607R is a timing generator IC which generates the timing pulses required by Progressive Scan CCD image sensors as well as signal processing circuits. Features • Base oscillation frequency 57.3MHz • High-speed/low-speed shutter function • Supports FINE and DRAFT mode drive (15 frames/s, 60 frames/s possible) • Random trigger shutter function (Supports TRIG and TRIGOUT mode drive) • Horizontal driver for CCD image sensor • Vertical driver for CCD image sensor Applications Progressive scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX285 (Type 2/3, 1450K pixels) 48 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDDa, b Vss – 0.3 to +7.0 VL –10.0 to Vss VH VL – 0.3 to +26.0 • Input voltage VI Vss – 0.3 to VDD + 0.3 Vss – 0.3 to VDD + 0.3 • Output voltage VO1 VO2 VL – 0.3 to Vss + 0.3 VO3 VL – 0.3 to VH + 0.3 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage VDDa 4.75 to 5.25 VDDb 3.0 to 3.6 VM 0.0 VH 14.55 to 15.45 VL –7.5 to –6.5 • Operating temperature Topr –20 to +75 V V V V V V V °C °C V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01318-PS CXD3607R Block Diagram XCPDM XCPOB ADCLK XSHD XSHP PBLK VSS1 RG 16 17 18 19 20 21 10 11 12 13 14 15 VDD2 OSCI 27 OSCO 26 VDD1 H1 H2 28 VDD3 7 VDD4 24 VSS2 25 CKI Pulse Generator 1/2 38 V1 39 V4 SSI 29 SCK 30 SEN 31 Register 40 V2A 42 V2B 47 V3 48 SUB VD 32 HD 33 TRIG 34 45 VL 2 RST 36 VSS3 1 VSS4 CKO 23 MCKO 22 V Driver 37 VM 41 VH 3 SYNSL 8 TEST1 9 TEST2 35 WEN –2– CXD3607R Pin Configuration (Top View) TRIG WEN VSS3 SEN SCK OSCO 26 OSCI VDD3 36 VM V1 V4 V2A VH V2B NC NC VL NC V3 SUB 37 38 39 40 41 42 43 44 45 46 47 48 1 35 34 33 32 31 30 29 SSI HD VD 28 27 25 24 VSS2 23 CKO 22 MCKO 21 ADCLK 20 PBLK 19 XCPOB 18 XCPDM 17 XSHP 16 XSHD 15 VDD2 14 VDD1 13 H2 2 3 4 5 6 7 8 9 10 11 12 VDD4 TEST2 VSS4 SYNSL TEST1 VSS1 RST NC NC NC RG ∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible. –3– H1 CKI CXD3607R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol VSS4 RST SYNSL NC NC NC VDD4 TEST1 TEST2 RG VSS1 H1 H2 VDD1 VDD2 XSHD XSHP XCPDM XCPOB PBLK ADCLK MCKO CKO VSS2 CKI OSCO OSCI VDD3 SSI SCK SEN VD HD TRIG WEN I/O — I I — — — — I I O — O O — — O O O O O O O O — I O I — I I I I I I O Description GND (GND for common logic block) Internal system reset input. (High: Normal operation, Low: Reset operation) Normally apply reset during power-on. Control input used to switch sync system. (High: CKI sync, Low: MCKO sync) With pull-down resistor (Leave open.) (Leave open.) (Leave open.) 3.3V power supply. (Power supply for common logic block) IC test pin 1 (Normally fix to GND.) IC test pin 2 (Normally fix to GND.) CCD reset gate pulse output. GND (GND for H1 and H2 pins) Horizontal CCD drive clock output. Horizontal CCD drive clock output. 5.0V power supply. (Power supply for H1 and H2 pins) 3.3V power supply. (Power supply for common logic block) CCD data level sample-and-hold pulse output. CCD precharge level sample-and-hold pulse output. CCD dummy signal clamp pulse output. CCD optical black signal clamp pulse output. Pulse output for horizontal and vertical blanking period pulse cleaning. Clock output for analog/digital conversion IC. System clock output for signal processing IC. (28.6MHz) Inverter output. (57.3MHz) GND (GND for common logic block) Inverter input. (57.3MHz) Inverter output for oscillation. (57.3MHz) Inverter input for oscillation. (57.3MHz) 3.3V power supply. (Power supply for common logic block) Serial interface data input for internal mode settings. Serial interface clock input for internal mode settings. Serial interface strobe input for internal mode settings. Vertical sync signal input. Horizontal sync signal input. Trigger pulse input. Memory write timing pulse output. –4– With pull-down resistor CXD3607R Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol VSS3 VM V1 V4 V2A VH V2B NC NC VL NC V3 SUB I/O — — O O O — O — — — — O O Description GND (GND for common logic block) GND (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output. (Leave open.) (Leave open.) –7.0V power supply. (Power supply for vertical driver) (Leave open.) CCD vertical register clock output. CCD electronic shutter pulse output. –5– CXD3607R Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 Supply voltage 5 Input voltage 1∗1 VDD1 VDD2 to 4 VH VM VL Pins Symbol VDDa VDDb VH VM VL Conditions (Within the recommended operating conditions) Min. 4.75 3.0 14.55 — –7.5 0.8VDDb 0.2VDDb 0.8VDDb 0.2VDDb Feed current where IOH = –3.3mA VDDb – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –6.6mA VDDb – 0.8 Pull-in current where IOL = 4.8mA Feed current where IOH = –10.4mA VDDb – 0.8 Pull-in current where IOL = 7.2mA Feed current where IOH = –22.0mA VDDa – 0.8 Pull-in current where IOL = 14.4mA V1, V2A, V2B, V3, V4 = –8.25V V1, V2A, V2B, V3, V4 = –0.25V V2A, V2B = 0.25V V2A, V2B = 14.75V SUB = –8.25V SUB = 14.75V 5.4 –4.0 5.0 –7.2 10.0 –5.0 0.4 0.4 0.4 0.4 Typ. 5.0 3.3 15.0 0 –7.0 Max. 5.25 3.6 15.45 — –6.5 Unit V V V V V V V V V V V V V V V V V mA mA mA mA mA mA RST, TEST1, Vt+ SSI, SCK, SEN, Vt– VD, HD, TRIG Vt+ Vt– Input ∗1, ∗2 SYNSL, TEST2 voltage 2 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 XCPDM, XCPOB, VOH1 PBLK, ADCLK, VOL1 WEN XSHD, XSHP , CKO RG, MCKO H1, H2 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 IOL VOM1 VOM2 VOH IOSL IOSH Output current 1 V1, V2A, V2B, V3, V4 Output current 2 SUB ∗1 These input pins are Schmitt trigger inputs, and have a protective diode on the power supply side in the IC. Therefore, they do not support 5V input. ∗2 These input pins are with pull-down resistor in the IC. Note) This table shows the conditions for 3.3V drive. –6– CXD3607R Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillator frequency Pins OSCI OSCI OSCO OSCI OSCO OSCI OSCO Symbol LVth VIH VIL VOH VOL RFB f Conditions — — — (Within the recommended operating conditions) Min. — 0.7VDDb — VDDb/2 — 500k 30 Typ. VDDb/2 — — — — 2M — Max. — — 0.3VDDb — VDDb/2 5M 75 Unit V V V V V Ω MHz Feed current where IOH = –9mA Pull-in current where IOL = 9mA VIN = VDDb or VSS — Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN Conditions — — — fmax 75MHz sine wave Min. — 0.7VDDb — 0.3 Typ. VDDb/2 — — — Max. — — 0.3VDDb — Unit V V V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML V L t o VM V M t o VH V L t o VH V M t o VL V H t o VM V H to V L Conditions (VH = 15.0V, VM = GND, VL = –7.0V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. See the CCD image sensor data sheet for details. –7– CXD3607R Switching Waveforms TTMH 90% TTHM VH 90% V2A, V2B TTLM 10% 90% 10% 90% TTML VM 10% 10% VL TTLM 90% V1, V3, V4 10% 90% TTML VM 10% VL TTLH 90% 90% TTHL VH SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –8– CXD3607R AC Characteristics AC characteristics between the serial interface clocks SSI 0.2VDDb 0.8VDDb SSI 0.8VDDb 0.2VDDb ts1 0.2VDDb ts3 SEN ts2 0.2VDDb th1 0.2VDDb 0.8VDDb SCK SEN (Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns ts1 th1 ts2 ts3 Serial interface clock internal loading characteristics Example: During FINE mode HD 0.2VDDb 8H 0.2VDDb 9H V2 ts1 th1 SCK 0.8VDDb SEN 0.8VDDb ∗ Be sure to maintain a constantly high SEN logic level from around the falling edge of the HD 8H after the falling edge of VD to around the 9H falling edge and during that horizontal period. (Within the recommended operating conditions) Symbol Definition Second SCK clock setup time after the rising edge of SEN, activated by the falling edge of HD SEN hold time, activated by the falling edge of 9H HD –9– Min. 5 30 Typ. Max. Unit ns µs ts1 th1 CXD3607R Serial interface clock output variation characteristics The serial interface data “Standby setting” is loaded to the CXD3607R and controlled at the rising edge of the second SCK clock after the rising edge of SEN. SEN 0.8VDDb SCK Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. 10 Typ. Max. 100 Unit ns delay, activated by edge tpdPULSE Output signalclock after the risingthe rising SEN of the second SCK edge of RST loading characteristics RST 0.2VDDb tw1 0.2VDDb (Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns tw1 VD, HD and TRIG loading characteristics 0.8VDDb 0.2VDDb ts1 MCKO 0.2VDDb th1 0.8VDDb VD/HD/TRIG MCKO load capacitance = 16pF (Within the recommended operating conditions) Symbol Definition VD/HD/TRIG setup time, activated by the rising edge of MCKO VD/HD/TRIG hold time, activated by the rising edge of MCKO Min. 20 5 Typ. Max. Unit ns ns ts1 th1 – 10 – CXD3607R Output variation characteristics 0.8VDDb MCKO WEN tpd1 WEN load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition Time until WEN changes after the rise of MCKO Min. –6 Typ. Max. 0 Unit ns tpd1 – 11 – CXD3607R Description of Operation Pulses output from the CXD3607R are controlled mainly by the RST and SYNSL pins and by the serial interface data. Control by the RST Pin System reset is performed by setting the CXD3607R RST pin (Pin 2) low. After reset is canceled, the serial data block is “XSHP XSHD logic phase adjustment setting” D0 bit = 1 and all other bits = 0. , In addition, when RST = low, some circuit operations in the IC are stopped as shown in the Pin Status Table below. Pin Status Table (RST = low) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS4 RST SYNSL NC NC NC VDD4 TEST1 TEST2 RG VSS1 H1 H2 VDD1 VDD2 XSHD XSHP XCPDM XCPOB PBLK ADCLK MCKO CKO VSS2 I/O status — L ACT — — — — — — ACT — ACT ACT — — ACT ACT H H H ACT ACT ACT — Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKI OSCO OSCI VDD3 SSI SCK SEN VD HD TRIG WEN VSS3 VM V1 V4 V2A VH V2B NC NC VL NC V3 SUB I/O status ACT ACT ACT — DIS DIS DIS DIS DIS DIS L — — VL VL VM — VM — — — — VM VL Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. VM and VL indicate the voltage levels applied to VM (Pin 37) and VL (Pin 45), respectively. – 12 – CXD3607R Control by the SYNSL Pin The CXD3607R sync system can be switched by the CXD3607R SYNSL pin (Pin 3). Low: MCKO sync (Normally use with this system configuration.) Select this when sync signals VD and HD are generated by the MCKO output of the CXD3607R. The VD and HD inputs are loaded to the CXD3607R at the rising edge of the MCKO pulse. High: CKI sync Select this when sync signals VD and HD are generated by the CKI input of the CXD3607R. The VD and HD inputs are loaded to the CXD3607R at the rising edge of the CKI pulse, and the two MCKO logic phases (a) and (b) existing after power-on can be aligned at the initial HD input by resetting the internal clock. Low: MCKO sync High: CKI sync High: MCKO reset for CKI sync CKI MCKO CXD3607R Sync signal generator block VD/HD CXD3607R CKI HD CKI Sync signal generator block VD/HD MCKO (a) MCKO (b) Control by the Serial Interface Data The CXD3607R loads the serial interface data in the following format at the rising edge of the second SCK clock after the rising edge of SEN. ∗ Make sure that SCK does not stop even while SEN is high. SSI SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SCK SEN In addition, the data are actually reflected at the following positions. → Reflected at the falling edge of the HD 8H after the falling edge of VD. 2. Special drive data “SUB stop setting” → Reflected at the falling edge of the HD 9H after the falling edge of VD. 4. Shutter data “Shutter SUB setting” → Reflected at the falling edge of the HD 9H after the falling edge of VD. 5. TRIG data → Reflected at the falling edge of the HD 1H after the falling edge of TRIG. (Only when the TRIG function setting is 1: TRIG function enabled) 6. Other data “Standby setting” → Reflected at the rising edge of the second SCK clock after the rising edge of SEN. Data other than the following There are six categories of serial interface data: drive mode data, special drive data, logic phase adjustment data, shutter data, TRIG data and other data. The details of the data for each category are described below. ∗ After reset is canceled, the serial data block is “XSHP, XSHD logic phase adjustment setting” D0 bit = 1 and all other bits = 0. – 13 – CXD3607R 1. Drive mode data SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 1 1 1 0 1 1 0 X D2 D1 D0 Description of settings Drive mode setting, TRIG function setting 2. Special drive data SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 1 0 1 0 X X X X D1 D0 Description of settings SG and SUB stop settings 3. Logic phase adjustment data SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 1 0 1 0 1 D1 D0 0 0 0 0 0 1 0 1 0 D1 D1 D0 D0 0 0 0 0 0 0 0 0 0 0 Description of settings XSHP logic phase adjustment setting XSHD logic phase adjustment setting ADCLK logic phase adjustment setting 4. Shutter data SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 1 1 0 1 0 1 0 1 0 1 D5 D11 D5 D11 D4 D10 D4 D10 D3 D9 D3 D9 D2 D8 D2 D8 D1 D7 D1 D7 D0 D6 D0 D6 Description of settings Shutter V setting Shutter SUB setting 5. TRIG data SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 0 1 0 1 D3 D3 D7 X D3 D7 D2 D2 D6 D10 D2 D6 D1 D1 D5 D9 D1 D5 D0 D0 D4 D8 D0 D4 SUB setting SG generation position setting Description of settings SG and SUB stop settings High-speed sweep setting Clamp pulse stop setting 6. Other data SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 1 1 1 1 1 0 0 X X – 14 – X X D0 Description of settings Standby setting CXD3607R Detailed Description of each Data 1. Drive mode data (1) Drive mode setting The CXD3607R drive mode can be switched as follows. ∗ TRIGOUT mode is the mode which stops the SG pulse (ternary value output of the V2A and V2B pulses) and the corresponding V pulse of FINE mode. Note that this is different from the special drive data “SG stop setting”. D1 0 0 1 D0 0 1 X Description of operation DRAFT mode FINE mode TRIGOUT mode (2) TRIG function setting (valid in DRAFT, FINE and TRIGOUT modes) The CXD3607R random trigger shutter function disabled/enabled setting can be switched as follows. ∗ For details, see “Special Drive Sequence (Random trigger shutter drive)”. D2 0 1 Description of operation TRIG function disabled TRIG function enabled 2. Special drive data (1) SG stop setting (valid in DRAFT and FINE modes) SG pulse (ternary value output of the V2A and V2B pulses) stopped/not stopped can be selected by the D0 setting. ∗ When SG stopped is selected, the corresponding V pulse is not stopped. ∗ When SG stopped is selected, WEN becomes inactive during that VD period. D0 0 1 Description of operation SG not stopped SG stopped (2) SUB pulse stop setting (valid in DRAFT, FINE and TRIGOUT modes) SUB pulse stopped/not stopped can be selected by the D1 setting. D1 0 1 Description of operation SUB not stopped SUB stopped – 15 – CXD3607R 3. Logic phase adjustment data (1) XSHP and XSHD logic phase adjustment setting The XSHP and XSHD logic phase adjustment can be selected by the D1 and D0 setting. ∗ The default when reset is 90°. ∗ For details, see the high-speed phase timing chart. D1 0 0 1 1 D0 0 1 0 1 Description of operation 0° 90° (default) 180° 270° (2) ADCLK logic phase adjustment setting The ADCLK logic phase adjustment can be selected by the D1 and D0 setting. ∗ The default when reset is 0° (pulse delayed 90° relative to MCKO). ∗ For details, see the high-speed phase timing chart. D1 0 0 1 1 D0 0 1 0 1 Description of operation 0° (default) 90° 180° 270° – 16 – CXD3607R 4. Shutter data (1) Shutter V setting (valid in DRAFT and FINE modes) The SG stopped VD period, that is to say the exposure time, can be adjusted from 0 to 4095V in 1V units by the D11 to D0 setting. Setting all 0 results in the high-speed shutter corresponding to the shutter SUB setting. ∗ During the SG stopped VD period, data other than 5. TRIG data and 6. Other data are not reflected. ∗ During the SG stopped VD period, only the SG pulse is stopped, and the corresponding V pulse is not stopped. ∗ During the SG stopped VD period, PBLK, XCPOB and XCPDM are active, and WEN is inactive. The SG stopped VD period (V) for each serial setting value and the shutter V setting outline diagrams (for SG stopped VD periods 0V and 1V) are shown below. D11 D10 0 0 0 0 0 0 D9 0 0 0 D8 0 0 0 D7 0 0 0 D6 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 SG stopped VD period (V) 0 1 2 : 4094 4095 Shutter V setting: 0V = high-speed shutter VD V2A SUB Exposure time Serial data reflected Shutter V setting: 1V VD V2A SUB Exposure time Serial data reflected – 17 – CXD3607R (2) Shutter SUB setting (valid in DRAFT, FINE and TRIGOUT modes) The charge drain period by the SUB pulse can be adjusted from 1 to 4095H in 1H units by the D11 to D0 setting. The number of SUB pulses for each serial setting value is shown below. ∗ Setting values in excess of the maximum number of pulses per VD period (example: 1068 pulses for VD = 1068H) are fixed to the maximum number of pulses. ∗ When performing long-time exposure with the shutter V setting, setting values in excess of the maximum number of pulses per VD period are fixed to the maximum number of pulses. ∗ Setting all 1 results in all SUB output (ALL), for any VD period. D11 D10 0 0 0 0 0 0 0 0 D9 0 0 0 0 D8 0 0 0 0 D7 0 0 0 0 D6 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 D5 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 Number of SUB pulses 1 1 2 3 : 4093 4094 All 1H HD V2A Shutter SUB setting 0 1 2 3 : 4093 4094 4095 (All) 2H 3H 4H 4094H 4095H 4096H to – 18 – CXD3607R 5. TRIG data (1) SG stop setting (valid only during TRIG drive) SG pulse (ternary value output of the V2A and V2B pulses) stopped/not stopped during TRIG drive can be selected by the D0 setting. ∗ When SG stopped is selected, the corresponding V pulse is not stopped. D0 0 1 Description of operation SG not stopped (TRIG drive) SG stopped (TRIG drive) (2) SUB stop setting (valid only during TRIG drive) SUB pulse stopped/not stopped during TRIG drive can be selected by the D1 setting. D1 0 1 Description of operation SUB not stopped (TRIG drive) SUB stopped (TRIG drive) (3) High-speed sweep setting (valid only during TRIG drive) High-speed sweep on/off during TRIG drive can be selected by the D2 setting. (For details, see Chart-4 to Chart-7.) D2 0 1 Description of operation High-speed sweep on (TRIG drive) High-speed sweep off (TRIG drive) ∗ The number of V transfers (stages) for high-speed sweep differs according to the drive mode during TRIG pulse input. (For details, see Chart-12 and Chart-13.) DRAFT mode: 20 (stages/H) × 53 (H) = 1060 (stages) FINE/TRIGOUT mode: 5 (stages/H) × 210 (H) = 1050 (stages) (4) Clamp pulse stop setting (valid only during TRIG drive) XCPDM, XCPOB and PBLK stopped/not stopped from SG pulse generation until 7H after the falling edge of the next valid VD during TRIG drive can be selected by the D3 setting. (For details, see Chart-4 to Chart-7.) D3 0 1 Description of operation Clamp pulses not stopped (TRIG drive) Clamp pulses stopped (TRIG drive) – 19 – CXD3607R (5) SG generation position setting (valid only during TRIG drive) The SG pulse (ternary value output of the V2A and V2B pulses) generation position during TRIG drive can be selected from 2 to 2048H counting from the next HD after the falling edge of the TRIG pulse by the D10 to D0 setting. The SG generation position (H) for each serial setting value is shown below. (For details, see Chart-4 to Chart-7.) D10 0 0 0 0 D9 0 0 0 0 D8 0 0 0 0 D7 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 SG generation position (H) 2 2 3 4 : 2046 2047 2048 ∗ When high-speed sweep is on, a SG generation prohibited area exists. When this area is designated, the SG pulse is generated at the position indicated below. When the drive mode during TRIG pulse input is: DRAFT mode: When the prohibited area 2 to 57H is designated, the SG pulse is generated at 58H. FINE/TRIGOUT mode: When the prohibited area 2 to 214H is designated, the SG pulse is generated at 215H. ∗ VD input is not accepted until 2H after the SG generation position (H), and is accepted from 3H onward. (Example: When the SG generation position is 58H, VD input is not accepted from 1 to 59H, and is accepted from 60H onward.) (6) SUB setting (valid only during TRIG drive) The number of SUB pulses during TRIG drive can be selected by the D7 to D0 setting. The number of SUB pulses for each serial setting value is shown below. D7 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 0 0 : 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 1 1 0 1 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 Number of SUB pulses 1 1 2 3 : 213 214 215 ∗ When high-speed sweep is off, the number of SUB pulses is two regardless of the drive mode during TRIG pulse input and the SUB setting value. ∗ When high-speed sweep is on, the maximum number of SUB pulses is as follows according to the drive mode during TRIG pulse input. Setting values in excess of the maximum number of pulses are fixed to the maximum number of pulses. (For details, see Chart-4 to Chart-7.) DRAFT mode: Max. 58 pulses FINE/TRIGOUT mode: Max. 215 pulses – 20 – CXD3607R 6. Other data (1) Standby setting Standby operation can be selected by the D0 setting. The Pin Status Table during standby operation is shown below. ∗ The standby setting bit is loaded at the rising edge of the second SCK clock after the rising edge of SEN, and control is applied immediately. ∗ Serial data is loaded as normal during standby operation. D0 0 1 Description of operation Normal operation Standby operation Pin Status Table (Standby setting bit = 1) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS4 RST SYNSL NC NC NC VDD4 TEST1 TEST2 RG VSS1 H1 H2 VDD1 VDD2 XSHD XSHP XCPDM XCPOB PBLK ADCLK MCKO CKO VSS2 I/O status — ACT ACT — — — — — — L — L L — — L L L L L L ACT ACT — Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKI OSCO OSCI VDD3 SSI SCK SEN VD HD TRIG WEN VSS3 VM V1 V4 V2A VH V2B NC NC VL NC V3 SUB I/O status ACT ACT ACT — ACT ACT ACT DIS DIS DIS L — — VM VM VH — VH — — — — VM VH Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled state. VM and VL indicate the voltage levels applied to VM (Pin 37) and VL (Pin 45), respectively. – 21 – CXD3607R Detailed Description of Output Pins The CXD3607R generates special pulses that are used by signal processing circuits, etc. These details are described below. • WEN (Pin 30) The CXD3607R outputs a WEN signal that indicates the effective line period output from the CCD image sensor. The WEN signal is high during the vertical effective line period. For details, see the vertical timing charts for each drive mode. ∗ When SG stopped is selected by the SG stop setting, WEN is inactive during the SG stopped VD period. ∗ When performing long-time exposure with the shutter V setting, WEN is inactive during the SG stopped VD period. Special Drive Sequence (Random trigger shutter drive) Cameras using the CXD3607R can perform random trigger shutter drive which allows image capturing at an optional timing. The TRIG pulse is loaded from the TRIG pin at the rising edge of MCKO, and reflected from the falling edge of the next HD. The random trigger shutter drive sequence in DRAFT mode is shown below. (1) TRIG VD HD Not accepted Not accepted Mode DRAFT DRAFT (TRIG function enabled) TRIGOUT DRAFT (4) SG generation position setting V2A (2) High-speed sweep setting (6) SG and V pulse stopped (3) SUB setting SUB Exposure A CCDOUT Exposure B Main exposure Main exposure Exposure C Exposure Exposure C Exposure A (part-way) None (5) Clamp pulse stop setting XCPOB, XCPDM – 22 – CXD3607R (1) If the drive mode data “TRIG function setting” is 1: Enabled at the falling edge of the TRIG pulse, operation switches to TRIG drive. ∗ Operation cannot be guaranteed for a TRIG pulse low-active period of 2H or less. ∗ The TRIG pulse is valid when input with the falling edge synchronized to the falling edge of VD. ∗ The TRIG pulse is not accepted after switching to TRIG drive. ∗ The VD pulse is not accepted for until 2H after SG generation after switching to TRIG drive. Serial data is also not reflected by the falling edge of VD during this period. (Example: When SG is generated at 58H, VD is not accepted from 1 to 59H) (2) Operation switches to TRIG drive mode and high-speed sweep for vertical register block charge drain starts from the falling edge of the next HD after the falling edge of the input TRIG pulse. The number of high-speed sweep stages differs according to the drive mode at the falling edge of the TRIG pulse as follows. DRAFT: 20 (stages/H) × 53 (H) = 1060 (stages), FINE/TRIGOUT: 5 (stages/H) × 210 (H) = 1050 (stages). High-speed sweep off can also be selected by the TRIG data “High-speed sweep setting”. (3) The charge drain period using the SUB pulse can be selected by the TRIG data “SUB setting”. When high-speed sweep is on, the maximum number of SUB pulses is as follows according to the drive mode at the falling edge of the TRIG pulse. DRAFT: max. 58 pulses, FINE/TRIGOUT: max. 215 pulses. When high-speed sweep is off, the number of SUB pulses is two regardless of the drive mode at the falling edge of the TRIG pulse and the SUB setting value. (4) The SG pulse generation position can be selected by the TRIG data “SG generation position setting”. After SG pulse output, V transfer is not performed and standby mode is established until the next VD input. (5) The clamp pulses can also be stopped after SG pulse generation by the TRIG data “Clamp pulse stop setting”. (6) Be sure to drive in TRIGOUT mode during the next VD period after TRIG drive. (Operation in other modes can be not guaranteed.) ∗ TRIG drive ends at the first VD input 3H onward after SG pulse generation. Even when operation shifted to TRIG drive during long-time exposure using the “Shutter V setting”, note that serial data is always reflected at the first VD input 3H onward after SG pulse generation. Specifications for Each Drive Mode and A Table Corresponding Timing Charts Total High-speed Number of highFrame number sweep H speed sweep rate (s) of HD (H) period (H) stages (stage) 1/60 1/15 1/15 — 267 1068 1068 — 0 0 0 53 (fixed) 0 0 0 0 1060 (fixed) 0 Vertical timing chart Chart-1 Chart-3 Readout Normal High-speed block H transfer block sweep block chart H chart H chart Chart-8 — Chart-9 Chart-11 Chart-11 — — — — Chart-12 Drive mode DRAFT FINE TRIGOUT DRAFT → TRIG (high-speed sweep on) DRAFT → TRIG (high-speed sweep off) FINE/TRIGOUT → TRIG (high-speed sweep on) FINE/TRIGOUT → TRIG (high-speed sweep off) Chart-2 Chart-10 Chart-4 Chart-10 — — Chart-5 Chart-10 — — — — 210 (fixed) 1050 (fixed) Chart-6 Chart-10 — Chart-13 — — 0 0 Chart-7 Chart-10 — — – 23 – 1025 1028 1033 1036 1 1 4 1 4 9 12 17 20 25 28 33 36 41 44 49 52 57 60 65 68 73 76 81 84 89 92 977 980 985 988 993 996 1001 1004 1009 1012 1017 1020 1025 1028 1033 1036 1 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 4 1 4 9 12 17 20 25 28 33 36 41 44 49 52 57 60 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 – 24 – WEN HD VD XCPDM XCPOB OUT SUB V2B V2A V4 V3 V1 Drive mode setting DRAFT PBLK TRIG function setting TRIG function disabled Readout block (Chart-8) Normal transfer block (Chart-9) Chart-1 Vertical Timing Chart MODE DRAFT mode 260H 1/60s CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. DRAFT DRAFT 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 TRIG function disabled TRIG function disabled 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1033 1034 1035 1036 1037 1038 1039 1040 1 2 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 1 2 3 4 5 – 25 – Drive mode setting FINE FINE FINE XCPDM XCPOB PBLK WEN OUT V4 V3 V1 SUB V2B V2A HD VD Readout block (Chart-10) Normal transfer block (Chart-11) Chart-2 Vertical Timing Chart TRIG function setting TRIG function disabled TRIG function disabled TRIG function disabled MODE FINE mode 1/15s 1040H 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1033 1034 1035 1036 1037 1038 1039 1040 1 2 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 1 2 3 4 5 – 26 – Drive mode setting TRIGOUT TRIGOUT TRIGOUT XCPDM WEN V4 V3 V1 XCPOB PBLK OUT SUB V2B V2A HD VD TRIG function setting TRIG function disabled TRIG function disabled TRIG function disabled Normal transfer block (Chart-11) Chart-3 Vertical Timing Chart MODE TRIGOUT mode 1/15s 1040H 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Chart-4 Vertical Timing Chart MODE DRAFT mode → TRIG drive (High-speed sweep on, SG generation position: 58H, SUB setting: 58 pulses) ∗ The VD fall is not accepted until 2H after SG generation. (Example: When the SG generation position is 58H, VD input is not accepted from 1 to 59H, and is accepted from 60H onward.) TRIG VD HD 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 High-speed sweep block (Chart-12) Fixed to 53H (20 stages × 53H = 1060 stages) Readout block (Chart-10) Selectable in the range of 58 to 2048H by the SG generation position setting. (Example: 58H) V1 SG prohibited area (1 to 57H) V2A V2B V3 V4 SUB Selectable from 1 to 58 pulses by the SUB setting. (Example: 58 pulses) XCPOB XCPDM PBLK These pulses can be stopped by the clamp pulse stop setting. WEN 1025 1033 17 25 33 41 1028 1036 12 20 28 36 44 52 4 4 OUT 49 1 1 1 9 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 50 51 52 53 54 55 56 57 58 59 60 61 Drive mode setting DRAFT DRAFT TRIG function enabled TRIG fuction setting TRIG function disabled 240 241 242 243 244 245 246 247 248 249 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TRIG function disabled 1 2 3 4 5 6 7 8 1 2 3 4 5 240 241 242 243 244 245 246 247 248 249 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 50 51 52 53 54 55 56 57 58 59 60 61 – 27 – TRIGOUT CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. Chart-5 Vertical Timing Chart MODE DRAFT mode → TRIG drive (High-speed sweep off, SG generation position: 2H, SUB setting: fixed to 2 pulses) ∗ The VD fall is not accepted until 2H after SG generation. (Example: When the SG generation position is 2H, VD input is not accepted from 1 to 3H, and is accepted from 4H onward.) TRIG VD HD 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 Readout block (Chart-10) Selectable in the range of 2 to 2048H by the SG generation position setting. (Example: 2H) V1 V2A V2B V3 V4 SUB Fixed to two pulses regardless of the SUB setting. XCPOB XCPDM PBLK These pulses can be stopped by the clamp pulse stop setting. WEN 1025 1033 17 25 33 41 1028 1036 12 20 28 36 44 52 4 4 OUT 49 1 1 1 9 260 261 262 263 264 265 266 267 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 Drive mode setting DRAFT DRAFT TRIG function enabled TRIG fuction setting TRIG function disabled 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 1 2 3 4 5 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 – 28 – TRIGOUT TRIG function disabled CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. Chart-6 Vertical Timing Chart MODE FINE/TRIGOUT mode → TRIG drive (High-speed sweep on, SG generation position: 215H, SUB setting: 215 pulses) TRIG VD HD 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 ∗ The VD fall is not accepted until 2H after SG generation. (Example: When the SG generation position is 215H, VD input is not accepted from 1 to 216H, and is accepted from 217H onward.) High-speed sweep block (Chart-13) Fixed to 210H (5 stages × 210H = 1050 stages) Readout block (Chart-10) Selectable in the range of 215 to 2048H by the SG generation position setting. (Example: 215H) V1 SG prohibited area (1 to 214H) V2A V2B V3 V4 SUB Selectable from 1 to 215 pulses by the SUB setting. (Example: 215 pulses) XCPOB XCPDM PBLK These pulses can be stopped by the clamp pulse stop setting. WEN OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 Drive mode setting FINE FINE TRIG function enabled TRIG fuction setting TRIG function disabled 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 207 208 209 210 211 212 213 214 215 216 217 218 TRIG function disabled 1 2 3 4 5 6 7 8 1 2 3 4 5 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 207 208 209 210 211 212 213 214 215 216 217 218 – 29 – TRIGOUT CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. Chart-7 Vertical Timing Chart MODE FINE/TRIGOUT mode → TRIG drive (High-speed sweep off, SG generation position: 2H, SUB setting: fixed to 2 pulses) TRIG VD HD 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 Readout block (Chart-10) Selectable in the range of 2 to 2048H by the SG generation position setting. (Example: 2H) ∗ The VD fall is not accepted until 2H after SG generation. (Example: When the SG generation position is 2H, VD input is not accepted from 1 to 3H, and is accepted from 4H onward.) V1 V2A V2B V3 V4 SUB Fixed to two pulses regardless of the SUB setting. XCPOB XCPDM PBLK These pulses can be stopped by the clamp pulse stop setting. WEN OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 1061 1062 1063 1064 1065 1066 1067 1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 Drive mode setting FINE FINE TRIG function enabled TRIG fuction setting TRIG function disabled 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 1 2 3 4 5 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 – 30 – TRIGOUT TRIG function disabled CXD3607R ∗ The number of SUB pulses is determined by the serial interface data. Chart-8 Horizontal Timing Chart MODE DRAFT mode readout block (1790) 0 (1790) 0 50 1H 100 150 200 250 300 350 400 800 850 900 950 1000 1050 50 HD 0 180 1790 MCKO OUT H1 43 380 380 66 118 150 202 234 286 318 804 801 55 87 139 171 223 255 307 339 906 1000 1032 55 87 1011 1063 43 43 66 OB (40) DM (20) OB (40) 4 43 380 400 402 4 43 H2 43 V1 V2A – 31 – V2B 55 87 139 171 223 255 307 339 1000 1032 55 87 V3 76 108 160 192 244 276 328 360 1021 1053 76 V4 45 97 129 181 213 265 297 349 990 1042 45 97 SUB 150 276 PBLK XCPOB XCPDM 382 398 WEN CXD3607R ∗ The HD of this chart indicates the actual CXD3607R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. Chart-9 Horizontal Timing Chart MODE DRAFT mode normal transfer block (1790) 0 50 2H to 100 150 200 250 300 350 400 450 500 550 600 650 700 (1790) 0 50 HD 0 180 1790 MCKO OUT H1 43 380 380 66 118 150 202 234 286 318 370 43 43 66 OB (40) DM (20) OB (40) 4 43 380 400 402 4 43 H2 43 V1 V2A – 32 – 55 87 139 171 223 255 307 339 55 87 V2B 55 87 139 171 223 255 307 339 55 87 V3 76 108 160 192 244 276 328 360 76 V4 45 97 129 181 213 265 297 349 45 97 SUB 150 276 400 44 PBLK 44 XCPOB 12 42 382 398 12 42 XCPDM WEN 211 CXD3607R ∗ The HD of this chart indicates the actual CXD3607R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. Chart-10 Horizontal Timing Chart MODE FINE mode readout block (1790) 0 50 1H 100 150 200 250 300 350 400 800 850 900 950 1000 1050 (1790) 0 50 HD 0 180 1790 MCKO OUT H1 43 380 380 129 801 87 213 801 87 213 906 87 804 906 87 43 43 OB (40) DM (20) OB (40) 4 43 380 400 402 4 43 H2 43 V1 V2A – 33 – V2B V3 171 297 V4 45 255 45 SUB 150 276 PBLK XCPOB XCPDM 382 398 WEN CXD3607R ∗ The HD of this chart indicates the actual CXD3607R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. Chart-11 Horizontal Timing Chart MODE FINE/TRIGOUT mode normal transfer block (1790) 0 50 2H to 100 150 200 250 300 350 400 450 500 550 600 650 700 (1790) 0 50 HD 0 180 1790 MCKO OUT H1 43 380 380 129 339 43 43 OB (40) DM (20) OB (40) 4 43 380 400 402 4 43 H2 43 V1 V2A – 34 – 87 213 87 V2B 87 213 87 V3 171 297 V4 45 255 45 SUB 150 276 400 44 PBLK 44 XCPOB 12 42 382 398 12 42 XCPDM WEN 211 CXD3607R ∗ The HD of this chart indicates the actual CXD3607R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. Chart-12 Horizontal Timing Chart MODE DRAFT mode → TRIG drive high-speed sweep block (1790) 0 50 After the fall of TRIG 100 150 1H to 200 250 300 350 400 450 500 1600 1650 1700 1750 (1790) 0 50 HD 0 180 1790 MCKO OUT H1 43 380 43 OB (40) DM (20) OB (40) 4 43 380 400 402 4 43 H2 43 #1 66 118 150 #2 202 234 #3 286 318 #4 380 370 402 #5 454 486 #19 1578 1630 1662 #20 1714 43 66 #1 V1 V2A 55 87 139 171 223 255 307 339 391 423 475 1567 1599 1651 1683 – 35 – 55 87 V2B 55 87 139 171 223 255 307 339 391 423 475 1567 1599 1651 1683 55 87 V3 76 108 160 192 244 276 328 360 412 444 496 1588 1620 1672 1704 76 V4 45 97 129 181 213 265 297 349 381 433 465 1557 1609 1641 1693 45 97 SUB 150 276 PBLK 44 XCPOB 12 42 XCPDM WEN 211 CXD3607R ∗ The HD of this chart indicates the actual CXD3607R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. Chart-13 Horizontal Timing Chart MODE FINE/TRIGOUT mode → TRIG drive high-speed sweep block (1790) 0 50 After the fall of TRIG 100 150 1H to 200 250 300 350 400 450 500 550 1650 1700 1750 (1790) 0 50 HD 0 180 1790 MCKO OUT H1 43 380 43 OB (40) DM (20) OB (40) 4 43 380 400 402 4 43 H2 43 #1 129 339 380 465 #2 #5 1683 43 #1 V1 V2A – 36 – 87 213 423 549 87 V2B 87 213 423 549 87 V3 171 297 507 1641 V4 45 255 381 45 SUB 150 276 PBLK 44 XCPOB 12 42 XCPDM WEN 211 CXD3607R ∗ The HD of this chart indicates the actual CXD3607R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. Chart-14 High-Speed Phase Timing Chart MODE DRAFT/FINE/TRIGOUT mode HD HD' CKI CKO 1 2 3 4 5 6 7 40 41 42 43 44 45 46 377 378 379 380 381 382 MCKO – 37 – H1 H2 RG XSHP (Logical phase 90˚) XSHD (Logical phase 90˚) ADCLK (Logical phase 0˚) CXD3607R ∗ HD’ indicates the HD which is the actual CXD3607R load timing. (when MCKO sync is selected) ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phases of XSHP, XSHD and ADCLK can be specified by the serial interface data. CXD3607R Application Circuit Block Diagram CCD ICX285 CCD OUT Digital OUT CDS/ADC Block XCPDM XCPOB H1 H2 RG V1 V2A V2B V3 V4 SUB 16 17 18 19 20 21 12 13 10 38 40 42 47 39 48 25 26 27 OSCO CKI OSCI ADCLK XSHD XSHP PBLK 22 23 35 32 TG CXD3607R V-Dr 2 3 33 34 MCKO CKO WEN VD HD TRIG Signal Processor Block RST SYNSL 8 TEST1 9 TEST2 29 30 31 SSI SCK SEN Controller This block diagram shows the connection relationship with each block, and is not an actual circuit diagram. See the CCD image sensor data sheet for a concrete example of circuit connection with a CCD image sensor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes for Power-on Of the four –7.0V, +15.0V, +3.3V, +5.0V power supplies, be sure to start up the –7.0V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential. 15V t1 20% 20% t2 t2 ≥ t1 0V –7.0V – 38 – CXD3607R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 12 13 B (0.22) + 0.05 0.127 – 0.02 0.13 M 0.1 0.1 ± 0.1 0.127 ± 0.04 0.5 ± 0.2 S 0.18 ± 0.03 0.5 ± 0.2 0˚ to 10˚ DETAIL B: PALLADIUM DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 P-LQFP48-7x7-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g – 39 – Sony Corporation