CXD3611R

CXD3611R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD3611R is a timing generator IC which generates the timing pulses for performing progressive scan readout using the ICX414/415/424 CCD image sensors. Features • Base oscillation frequency 24.545451MHz (ICX414, 424)/ 29.500000MHz (ICX415) (When in double speed drive mode: 49.090902/59.000000MHz) • Electronic shutter function • Trigger shutter function • Supports central scanning mode (two types)/ double speed drive mode • Horizontal driver for CCD image sensor (However, uses external driver for double speed drive mode.) • Vertical driver for CCD image sensor Applications Monitoring/image analysis Structure Silicon gate CMOS IC Applicable CCD Image Sensors • ICX414 (Type 1/2, 330K pixels) • ICX415 (Type 1/2, 460K pixels) • ICX424 (Type 1/3, 330K pixels) 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD Vss – 0.3 to +7.0 V VL –10.0 to Vss V VH VL – 0.3 to +26.0 V • Input voltage VI Vss – 0.3 to VDD + 0.3 V • Output voltage VO1 Vss – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V VO3 VL – 0.3 to VH + 0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDDa, VDDb 3.0 to 5.5 VDDc 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75 V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02561-PS CXD3611R Block Diagram VDD2 XSHD XSHP 15 16 17 18 14 OSCI OSCO 32 20 21 22 19 27 VSS3 31 Selector VDD3 26 ADCLK 23 PBLK 24 CLPDM 25 OBCLP 41 WEN 34 RDM 35 TRG 36 ESG 52 V1 54 V2 58 V3 62 SUB 50 VM 56 VH 60 VL Vss2 CKI 30 Selector Pulse Generator 1/2 1/2 MCKO 29 SNCSL 2 Selector Latch SSI 38 SCK 39 SEN 40 PS 37 HDRS 11 CDSRS 12 CCD MD1 MD2 MD3 SMD1 SMD2 4 5 6 7 8 9 SSG V Driver Register SMD3 10 SSGSL 3 49 RST 64 TEST 1 28 48 Vss1 Vss4 Vss5 13 33 VDD1 VDD4 43 SYNC 42 BLK 47 HDO 46 VDO 45 VDI 44 HDI Notes) 1. CKI must always be input below amplitude VDD with a sine wave. 2. The system block diagram above is an example using an oscillator. –2– RG H1 H2 XRS CXD3611R Pin Configuration SYNC WEN 48 RST VM NC V1 NC V2 NC VH NC V3 NC VL NC SUB NC TEST 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 VSS1 47 46 45 44 43 42 41 40 39 38 37 RDM ESG TRG 36 35 34 33 32 OSCI 31 OSCO 30 CKI 29 MCKO 28 Vss4 27 Vss3 26 ADCLK 25 OBCLP 24 CLPDM 23 PBLK 22 XRS 21 XSHD 20 XSHP 19 VDD3 18 VDD2 17 H2 2 SNCSL 3 SSGSL 4 CCD 5 MD1 6 MD2 7 MD3 8 SMD1 9 SMD2 10 SMD3 11 HDRS 12 CDSRS 13 VDD1 14 RG 15 VSS2 16 H1 ∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible. –3– VDD4 VSS5 HDO VDO SEN SCK BLK HDI VDI SSI PS CXD3611R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VSS1 SNCSL SSGSL CCD MD1 MD2 MD3 SMD1 SMD2 SMD3 HDRS I/O — I I I I I I I I I I GND Control input used to switch sync system High: CKI sync, Low: MCKO sync. With pull-down resistor Description Pin used to switch external reset High: External sync has priority, Low: Internal sync has priority With pull-down resistor Control input used to switch CCD High: ICX415, Low: ICX414/424 Control input 1 used to switch drive mode See the section on parallel control Control input 2 used to switch drive mode See the section on parallel control Control input 3 used to switch drive mode See the section on parallel control Control input 1 used to switch exposure time See the section on parallel control Control input 2 used to switch exposure time See the section on parallel control Control input 3 used to switch exposure time See the section on parallel control Control input used to switch H system pulse polarity H1 and H2 are targeted (Default is positive polarity.) High: For external Dr, Low: For internal Dr With pull-down resistor With pull-down resistor With pull-down resistor With pull-down resistor With pull-down resistor With pull-down resistor With pull-down resistor With pull-down resistor 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CDSRS VDD1 RG VSS2 H1 H2 VDD2 VDD3 XSHP XSHD XRS PBLK CLPDM OBCLP ADCLK VSS3 I — O — O O — — O O O O O O O — Control input used to switch CDS system pulse polarity XSHP XSHD, XRS, OBCLP CLPDM are targeted. , , High: Positive polarity, Low: Negative polarity With pull-down resistor 3.3V power supply. (Power supply for common logic block) CCD reset gate pulse output GND CCD horizontal register clock output CCD horizontal register clock output 3.3V power supply. (Power supply for H1/H2/RG) 3.3V power supply. (Power supply for CDS) CCD precharge level sample-and-hold pulse output CCD data level sample-and-hold pulse output Sample-and-hold pulse output for analog/digital conversion phase alignment Pulse output for horizontal and vertical blanking period pulse cleaning CCD dummy signal clamp pulse output CCD optical black signal clamp pulse output Clock output for analog/digital conversion IC Logical phase can be adjusted using serial interface data. GND –4– CXD3611R Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VSS4 MCKO CKI OSCO OSCI VDD4 RDM TRG ESG PS SSI SCK SEN WEN BLK SYNC HDI VDI VDO HDO VSS5 RST VM NC VI NC V2 NC VH NC V3 NC VL I/O — O I O I — I I I I I I I O O O I I O O — I — — O — O — — — O — — GND Description System clock output for signal processing IC Inverter input Inverter output for oscillation; should be open or C grounded when not in use. Inverter input for oscillation; should be fixed to Low when not in use. 3.3V power supply. (Power supply for common logic block) Trigger control, normally fixed to VDD. See the section on trigger shutter function. Trigger control, normally fixed to VDD. See the section on trigger shutter function. Readout pulse position control, normally fixed to VDD. See the section on trigger shutter function. Control input used to switch serial and parallel High: Parallel, Low: Serial Serial interface data input for internal mode settings. Serial interface clock input for internal mode settings. Serial interface strobe input for internal mode settings. Memory writing timing pulse output Blank pulse output SYNC pulse output Horizontal sync reset signal input Vertical sync reset signal input Vertical sync signal output Horizontal sync signal output GND Input pin for internal system reset Normally, apply reset during power-on. High: Normal operation, Low: Reset control GND (Ground for vertical driver) No connection CCD vertical register clock output No connection CCD vertical register clock output No connection 15.0V power supply. (Power supply for vertical driver) No connection CCD vertical register clock output No connection –7.5V power supply. (Power supply for vertical driver) –5– With pull-up resistor With pull-up resistor With pull-up resistor With pull-up resistor With pull-up resistor With pull-up resistor Schmitt trigger input Schmitt trigger input Schmitt trigger input Schmitt trigger input CXD3611R Pin No. 61 62 63 64 NC Symbol I/O — O — I No connection Description SUB NC TEST CCD electronic shutter pulse output No connection Pin for IC test, normally fixed GND. With pull-down resistor –6– CXD3611R Electrical Characteristics DC Characteristics Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage 1∗1 Pins VDD3 VDD2 VDD1, VDD4 RST, SSI, SCK, SEN Symbol VDDa VDDb VDDc Vt+ Vt– 0.7VDDC 0.3VDDC 0.7VDDC 0.3VDDC Feed current where IOH = –14.0mA VDDb – 0.8 Pull-in current where IOL = 9.6mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA V1, V2, V3 = –8.25V V1, V2, V3 = –0.25V V2, V3 = 0.25V V2, V3 = 14.75V SUB = –8.25V SUB = 14.75V 5.4 –4.0 5.0 –7.2 10.0 –5.0 VDDc – 0.8 0.4 VDDc – 0.8 0.4 VDDa – 0.8 0.4 VDDb – 0.8 0.4 0.4 Conditions (Within the recommended operating conditions) Min. 3.0 3.0 3.0 0.8VDDc 0.2VDDc Typ. 3.3 3.3 3.3 Max. 5.5 5.5 3.6 Unit V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA Input voltage 2∗2 SNCSL, SSGSL, TEST, VIH1 CCD, MD1 to 3, SMD1 to 3, VIL1 HDRS, CDSRS RDM, TRG, ESG, PS, VDI, HDI H1, H2 RG XSHP XSHD, , PBLK, XRS, OBCLP , CLPDM, ADCLK MCKO WEN, BLK, SYNC, VDO, HDO VIH2 VIL2 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 IOL Input voltage 3∗3 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output current 1 V1, V2, V3 IOM1 IOM2 IOH IOSL IOSH Output current 2 SUB ∗1 These input pins are Schmitt trigger inputs. ∗2 These input pins are with a pull-down resistor in the IC. ∗3 These input pins are with a pull-up resistor in the IC. Note) The table above indicates the condition for 3.3V drive. –7– CXD3611R Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI OSCO OSCI, OSCO OSCI, OSCO Symbol LVth VIH VIL VOH VOL RFB f Conditions (Within the recommended operating conditions) Min. 0.7VDDc 0.3VDDc Typ. VDDc/2 Max. Unit V V V V 0.4 500k 20 2M 5M 50 V Ω MHz Feed current where IOH = –3.6mA VDDc – 0.8 Pull-in current where IOL = 2.4mA VIN = VDDc or VSS Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDc 0.3VDDc Conditions Min. Typ. VDDc/2 Max. Unit V V V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Symbol TTLM Rise time TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML Conditions VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL (VH = 15.0V, VM = GND, VL = –7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V Notes) 1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –8– CXD3611R Switching Waveforms TTMH 90% TTHM VH 90% V3 (V2) TTLM 10% 90% 10% 90% TTML VM 10% 10% VL TTLM 90% V1 10% 90% TTML VM 10% VL TTLH 90% 90% TTHL VH SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –9– Measurement Circuit Serial interface data VDI HDI +3.3V –7.5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 R1 53 54 55 C2 57 R1 59 C2 61 62 C3 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 63 60 58 56 CXD3611R 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C5 C6 C6 C6 C6 C6 C6 C6 CKI C6 +15.0V R1 C2 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 – 10 – C2: 560pF R2: 10Ω C3: 820pF C4: 6pF C5: 107pF C2 C2 C2 R1 C1 C2 C2 C1 C1 C2 R2 R1 C4 C5 CXD3611R C1: 3300pF R1: 30Ω C6: 10pF CXD3611R AC Characteristics AC characteristics between the serial interface clocks 0.8VDDc SSI SCK SEN SEN ts2 0.2VDDc 0.8VDDc 0.2VDDc ts1 0.2VDDc ts3 0.8VDDc th1 (Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns ts1 th1 ts2 ts3 Serial interface clock internal loading characteristics Example: Progressive Scan Mode VDO HDO V2 Enlarged view HDO 0.2VDDc V2 ts1 SEN 0.8VDDc 0.2VDDc th1 ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HDO in the horizontal period during which V2 and V3 values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HDO SEN hold time, activated by the falling edge of HDO Min. 0 32 Typ. Max. Unit ns µs ts1 th1 ∗ Restrictions in the progressive scan mode when the ICX415 operating frequency is set to 29.5MHz. – 11 – CXD3611R Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3611R at the timing shown in the section "Serial interface clock internal loading characteristics". However, one exception to this is when the data such as CKMD is loaded to the CXD3611R and controlled at the rising edge of SEN. See "Description of Operation". SEN Output signal 0.8VDDc tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns tpdPULSE Output signal delay, activated by the rising edge of SEN RST loading characteristics RST 0.2VDDc tw1 0.2VDDc (Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns tw1 VDI and HDI phase characteristics VDI 0.2VDDc ts1 HDI th1 0.2VDDc 0.2VDDc (Within the recommended operating conditions) Symbol Definition VDI setup time, activated by the falling edge of HDI VDI hold time, activated by the falling edge of HDI Min. 0 0 Typ. Max. Unit ns ns ts1 th1 – 12 – CXD3611R HDI loading characteristics HDI 0.2VDDc ts1 MCKO th1 0.8VDDc 0.2VDDc MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition HDI setup time, activated by the rising edge of MCKO HDI hold time, activated by the rising edge of MCKO Min. 16 0 Typ. Max. Unit ns ns ts1 th1 Output variation characteristics MCKO 0.8VDDc WEN tpd1 WEN load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition Time until the above outputs change after the rise of MCKO Min. 25 Typ. Max. 55 Unit ns tpd1 – 13 – CXD3611R Description of Operation Pulses output from the CXD3611R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol VSS1 SNCSL SSGSL CCD MD1 MD2 MD3 SMD1 SMD2 SMD3 HDRS CDSRS VDD1 RG VSS2 H1 H2 VDD2 VDD3 XSHP XSHD XRS ACT ACT ACT ACT ACT — — ACT ACT ACT ACT — ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT — ACT CAM — ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT RST Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol PBLK CLPDM OBCLP ADCLK VSS3 VSS4 MCKO CKI OSCO OSCI VDD4 RDM TRG ESG PS SSI SCK SEN WEN BLK SYNC HDI ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT — ACT ACT ACT ACT DIS DIS DIS L L L ACT CAM ACT ACT ACT ACT — — ACT ACT ACT ACT RST H H H ACT Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol VDI VDO HDO VSS5 RST VM NC V1 NC V2 NC VH NC V3 NC VL NC SUB NC TEST ACT — — ACT — — — VL ACT — — — VL ACT — VM ACT — — VL CAM ACT ACT ACT — L RST ACT H H Note) CAM means normal operation and RST means a state wherein control is applied by the RST pin (Pin 49). ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H indicates a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 56), VM (Pin 50) and VL (Pin 60), respectively, in the controlled status. – 14 – CXD3611R Parallel Interface Control The CXD3611R has several pin control systems. Specifically, they are SNCSL (Pin 2), SSGSL (Pin 3), CCD (Pin 4), MD1 , MD2 , MD3 (Pins 5 to 7), SMD1 , SMD2 , SMD3 (Pins 8 to 10), HDRS (Pin 11), CDSRS (Pin 12), RDM (Pin 34), TRG (Pin 35), ESG (Pin 36), PS (Pin 37), HDI (Pin 44), VDI (Pin 45), and RST (Pin 49). See "Pin Description" for details regarding: SNCSL , SSGSL , CCD , HDRS , CDSRS , PS , RST . When parallel control is selected in the PS pin (Pin 37), the control indicated below takes priority over the serial control, described later. Note that (double) indicates that the base oscillation frequency ratio is doubled and it has entered a low speed drive. When a double speed drive is entered, it means that drive at a normal speed can be used. Also, a single field 1 means only the ODD sided field is repeated so half of the 0.5H is applied to that V frequency. Single field 2 means only the ODD sided field simultaneously, but has 1H units for that V frequency. MD2/MD1 MD3 Low High Low/Low Progressive scan Progressive scan (Double) Low/High Central scan 1 Central scan 2 High/Low Single field 1 Single field 2 High/High Interlace Interlace (Double) ∗ See the section relating to serial interface control and drive mode, describe later, for details. SMD3 Low Low Low Low High High High High SMD2 Low Low High High Low Low High High SMD1 Low High Low High Low High Low High ICX414/424 Progressive scan No SUB 000h 1/100 16Fh 1/250 1CDh 1/500 1EDh 1/1000 1FCh 1/2000 204h 1/4000 208h All SUB 20Dh Interlace No SUB 000h 1/100 068h 1/250 0C7h 1/500 0E6h 1/1000 0F6h 1/2000 0FEh 1/4000 102h All SUB 106h ICX415 Progressive scan No SUB 000h 1/120 1FEh 1/250 232h 1/500 251h 1/1000 260h 1/2000 268h 1/4000 26Ch All SUB 270h Interlace No SUB 000h 1/120 0B5h 1/250 0F9h 1/500 118h 1/1000 128h 1/2000 130h 1/4000 134h All SUB 138h Unit — s s s s s s — ∗ Uses progressive scan mode and interlace mode as standards. Central scan mode and single field mode are not strictly combined. – 15 – CXD3611R TRG , RDM , ESG use the trigger shutter function. The trigger shutter function relates to serial control and the electronic shutter function, and as such is described later. The functions for HDI and VDI are switched by SSGSL . VDI is received as V-reset when the internal SSG priority is set to ( SSGSL = L). However, basically, VDI / HDI are fixed at high so substantially, it is an internal SSG drive. VDO is V-Reset by VD1 , when the external sync priority is set to ( SSGSL = H). This IC simply repeats idle transfers of V when a 1V operation is cut and a longer cycle is applied. Also, H-Reset occurs for HDO by HDI . Note that for external sync priority, operations without a VDI / HDI reset input are not guaranteed. In the interlace system mode, when a falling edge of the VDI input from an external source is detected, it determines whether it is ODD or EVEN. If ODD, a V-Reset is applied on the falling edge of the HDO and the midway of the HDO if EVEN, so that the VDO falls. VDI requires a pulse width of over 2H. Also, in all, an H-Reset is applied when a falling edge of an HDI reset signal is detected and HDO falls with the falling edge after 9MCKO. The minimum reset pulse width of the HDI is 10MCKO. V-Reset VDI 9H VDO HDO H-Reset MCKO HDI HDO – 16 – CXD3611R Field Identification (When VDI is input in the interlace system mode) VDI 1 2 HDO tp1 tp2 tp3 fhd (internal pulse) tp4 tp5 VDO 1 ODD VDO 2 EVEN Symbol Definition Region to reset to ODD Region to reset to EVEN Region to reset to ODD Prohibited region Prohibited region ICX414/424 (ck) 273 384 — 4 4 ICX415 (ck) 329 465 — 4 4 tp1 tp2 tp3 tp4 tp5 ∗ There are no particular standards because HDO periods can be any value according to the HDI reset. ∗ Clock unit is MCKO. – 17 – CXD3611R Serial Interface Control The CXD3611R can be controlled by the serial interface data transmitted in the format below, for controls other than those that are applied by MD1 , MD2 , MD3 (Pins 5 to 7) and SMD1 , SMD2 , SMD3 (Pins 8 to 10) when serial control or parallel control is selected in the PS (Pin 37). Serial interface data latches with the rising edge of the SEN for each 1 category and reflects taking in at the falling edge of the HDO in the readout field. The readout field indicates horizontal period during which V2 and V3 values take the ternary value. SSI SCK SEN 00 01 02 03 04 05 06 07 08 31 32 33 34 35 36 37 38 39 Note that there are three main categories in serial interface data. Specifically, they are: CXD3611R drive control data (control data), electronic shutter data (shutter data) and trigger shutter data (trigger data). The following describes each in detail. – 18 – CXD3611R Control Data Data D00 to D07 Name CHIP Function Chip enable Category switching — Drive mode switching Base oscillation frequency division switching∗1 — OBCLP waveform pattern switching ADCLK logic phase switching Vertical direction width OBCLP generation switching∗2 RG pulse inversion switching — — Data = 0 Data = 1 RST All 0 0 0 — 0 0 All 0 0 All 0 1 0 1 0 0 0 All 0 10000001 → Enabled Other values → Disabled 00 → CTL D08, CTG D09 D10, D11 D12 to D14 D15 D16 to D19 — MODE CKMD — See the section on drive mode 2 frequency division — 4 frequency division — D20, PTOB D21 D22, LDAD D23 D24 D25 D26 to D39 FGOB RGRS — See the section on OBCLP waveform patterns See the section on ADCLK logic phase ON Posotive polarity — OFF Negative polarity — ∗1 See the section on drive mode ∗2 See the section on wide OBCLP generation – 19 – CXD3611R Shutter Data Data D00 to D07 Name CHIP Function Chip enable Category switching — Electronic shutter mode switching∗1 HTSG control switching∗1 Electronic shutter vertical period specification Electronic shutter horizontal period specification — — OFF OFF Data = 0 Data = 1 RST All 0 0 0 — ON ON 0 0 0 All 0 All 0 All 0 10000001 → Enabled Other values → Disabled 01 → SHT D08, CTG D09 D10, D11 D12 D13 D14 to D23 D24 to D33 D34 to D39 — SMD HTSG SVT See the section on electronic shutter SHT See the section on electronic shutter — — — ∗1 See the section on electronic shutter Trigger Data Data D00 to D07 Name CHIP Function Chip enable Category switching — Trigger shutter horizontal period specification — TSINT function switching∗1 Trigger shutter fine adjustment specification Data = 0 Data = 1 RST All 0 0 0 — All 0 All 0 0 0 All 0 10000001 → Enabled Other values → Disabled 10 → TRIG — D08, CTG D09 D10 to D23 D24 to D33 D34 D35 D36 to D39 — TSG — TFINT TSINT See the section on trigger shutter — OFF — ON See the section on trigger shutter ∗1 See the section on trigger shutter – 20 – CXD3611R Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD3611R by the serial interface, the CXD3611R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 0 0 1 1 D08 0 1 0 1 Description of operation Loading to control data register Loading to shutter data register Loading to trigger data register Test mode Note that the CXD3611R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D20 to D21 PTOB [OBCLP waveform pattern] This indicates the OBCLP waveform pattern. The default is "Normal". See the timing chart for details regarding decode values. D21 0 0 1 1 D20 0 1 0 1 Waveform pattern (Normal) (Shifted forward) (Shifted rearward) (Wide) ICX414/424 11 to 31 9 to 29 13 to 33 9 to 33 ICX415 11 to 36 9 to 34 14 to 39 9 to 39 Control data: D24 FGOB [Vertical direction wide OBCLP generation] This controls wide OBCLP generation during the vertical OPB period. When this function is turned ON, D20 and D21 PTOB specification is disabled for the output. See the Timing Charts for the actual operation. The default is "ON". D24 0 1 Description of operation Vertical direction wide OBCLP generation ON Vertical direction wide OBCLP generation OFF Control data: D22 to D23 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO. D23 0 0 1 1 D22 0 1 0 1 Degree of adjustment (°) 0 90 180 270 – 21 – CXD3611R Control data: [Drive mode] CXD3611R realizes various drive modes using the control data D12 to D14 MODE and CCD pins (Pin 4). The following gives detailed descriptions. First, the basic drive modes are shown below. This uses of the control data MODE D12 and D13 . D13 0 0 1 1 D12 0 1 0 1 Description of operation Progressive scan mode (default) Central scan mode Single field mode Interlace mode The progressive scan mode is a drive mode that reads out all of the line data of the CCD image sensor. The central scan mode is a drive mode that uses the progressive scan mode as a base to read out the central image in a high frame rate. The interlace mode is a drive mode for outputting according to TV standards. The single field mode is a drive mode for reading only single field of the aforementioned interlace mode. Base on these, it uses MODE D14 to realize the following variations. D13/D12 D14 0 1 0/0 Progressive Scan Single field 3 0/1 Central scan 1 Central scan 2 1/0 Single field 1 Single field 2 1/1 Interlace Single field 4 If D14 is allotted while D12 and D13 are in the central scan mode, it behaves in the following manner. When D14 is "0", it drives in the pattern called central scan mode 1. When D14 is "1" it drives in the pattern called central scan mode 2. Other patterns are variations of the single field mode. To describe the items of the table, single field 1 drives by repeating the ODD side of the interlace mode. Single field 3 drives by repeating the EVEN side of the interlace mode. Single field 2 repeats the ODD side of the interlace mode, but if an NTSC standard CCD is used, it enters a pattern to drive cutting the field applying 262.5H into HD units of 262H. Single field 4, in the same way, enters a pattern to drive the EVEN side of the interlace mode in 262H units. However, these last two modes are actually controls for the internal SSG, so when using an external sync, this function is not guaranteed. Depending on the pin control CCD, it switches to the ICX414/424 for NTSC (EIA) standard systems and to ICX415 for PAL (CCIR) standard systems. See the timing chart for details regarding either drive mode. Finally, as for the double-speed mode, it switches according to the D15 CKMD, but when realizing this drive mode, set the base oscillation frequency to two times the normal speed. By switching using the parameters above, normal and double speeds can be dually used. To switch this parameter with the base oscillation frequency at its normal state, operation is in 1/2 speed drive mode, but the CCD operates outside of its guarantee. – 22 – CXD3611R Control data/shutter data: [Electronic shutter] The CXD3611R realizes various electronic shutter functions by using shutter data D12 SMD, D13 HTSG, D14 to D23 SVT, and D24 to D33 SHT. These functions are described in detail below. First, the various modes are shown below. These modes are switched using shutter data D12 SMD. D12 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode The electronic shutter data is expressed as shown in the table below using D24 to D35 SHT as an example. MSB D33 D32 D31 D30 0 ↓ 1 1 1 1 ↓ C D29 D28 D27 D26 0 0 0 0 ↓ 3 1 LSB D25 D24 1 → Expressed as IC3h . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [Electronic shutter mode] During this mode, the shutter data items have the following meanings. Name SVT SHT Data Shutter: D14 to D23 Shutter: D24 to D33 Description Number of vertical periods specification (000h ≤ SVT ≤ 3FFh) Number of horizontal periods specification (000h ≤ SHT ≤ 3FFh) Note) The bit data definition area is assured in terms of the CXD3611R functions, and does not assure the CCD characteristics. The period during which SVT and SHT are specified together is the shutter speed. The exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVT × (1V period) + {(number of HD per 1V) – (SHT + 1)} × (1H period) + (the distance from SUB falling edge of the readout period to the SG falling edge) Concretely, when specifying high-speed shutter, SVT is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVT is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHT can be considered as (number of SUB pulses – 1). Also, the readout period is the normal horizontal period during which V2 and V3 values take the ternary value and SG indicates the readout pulse for the third value. – 23 – CXD3611R VDO SHT V3 SVT SUB WEN SMD SVT SHT 1 002h 10Fh 1 000h 050h Exposure time [HTSG control mode] This mode controls the V2, V3 ternary values output (readout pulse block) using D13 HTSG. However, when D12 SMD is in the electronic shutter mode, note that this operation is not guaranteed. D13 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode VDO V3 SUB WEN SMD HTSG 1 0 0 1 1 0 Exposure time – 24 – CXD3611R Trigger data: [Trigger shutter] The CXD3611R realizes trigger shutter functions by using trigger data D24 TSG, D35 TFINT and D36 to D39 TSINT and RDM (Pin 34), TRG (Pin 35) and ESG (Pin 36). These functions are described in detail below. First, the basic sequences of the trigger shutter function are shown below. Trigger shutter period WAIT RDM TRG ESG VDO V3 SUB Exposure period Transfer period Exposure time Initially, it enters a WAIT period from a horizontal period immediately following the falling edge of the RDM to begin high speed sweeping. At this time, SUB also generates horizontal periods simultaneously. Next, immediately following the falling edge of TRG, it enters the exposure period from the horizontal period. High speed sweeping that had been generated up to that point is stopped whereat normal transfers begin. Simultaneously, SUB also ceases. The final SUB pulse specified is generated immediately following the falling edge of TRG. At this time, the settings of D36 to D39 TSINT are reflected enabling fine adjustments of the ultra-high speed shutter exposure time. However, only when D35 TFINT is set to ON, this function enables the internal counter and allows its use. See the table below for details regarding the adjustment data. Next, immediately following the falling edge of the ESG, a readout pulse is generated in the horizontal period to set the exposure time. Then, data transfer occurs in sync to the next VD period, but normal transfers stop up to that point. Also, the readout pulse position can be specified using serial control. The positions counted as 0, 1, 2, ... from the horizontal period immediately following the falling edge of TRG, while the ESG is fixed to a high state, are specified using D24 to D33 TSG. However, parallel control has priority, so when executed from serial to parallel, it is possible to output the readout pulse twice in the same exposure time. However, operations in this situation are not guaranteed, so be careful of the sequences. Note that it is presumed that the drive mode specified in the transfer period is either the progressive scan mode or the central scan mode systems. If the drive mode is set to something else, operations are not guaranteed. Furthermore, be aware that readout pulse outputs will be aborted. Normal SUB output is accepted from the transfer period. Also, this IC will not respond even if only TRG is applied. Always combine a sequence that uses RDM and TRG as a set. In other words, when omitting the high speed sweeping, RDM and TRG should be applied simultaneously. – 25 – CXD3611R [Trigger shutter fine adjustment data] 0 HDO SUB A B C D E H I J K L 780 or 944 [For ICX414/424] Position D39 A B C D E F G H I J K L — 0 0 0 0 0 0 0 0 1 1 1 1 D38 D37 D36 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Ascending position 72∗1 137 202 267 332 397 462 527 592 657 722 7 ∗2 — Descending position 95∗1 160 225 290 355 420 485 550 615 680 745 30∗2 — Remainder is invalid [For ICX415] Position D39 A B C D E F G H I J K L — 0 0 0 0 0 0 0 0 1 1 1 1 D38 D37 D36 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Ascending position 99∗1 177 255 333 411 489 567 645 723 801 879 13∗3 — Descending position 122∗1 200 278 356 434 512 590 668 746 824 902 36∗3 — Remainder is invalid Note) Position data represents the counted values from the falling edge of the HRO to the rising edge of the MCKO. ∗1 Default timings for each drive mode. ∗2 This timing has a variable point in the 780ck cycle HDO. ∗3 This timing has a variable point in the 944ck cycle HDO. – 26 – Chart-1 Progressive Scan Mode (Non-interlace) • ICX414/424 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 518 524 0 1 6 8 9 10 15 23 516 519 524 0 1 6 SUB A A V1 V2 CCD OUT PBLK OBCLP CLPDM WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VR in this chart is described in 525H (1H: 780ck) units. 490 491 492 493 494 491 492 493 494 – 27 – 1234567812 V3 9 10 HDO 1234567812 CXD3611R Chart-2 Central Scan 1 Mode • ICX414/424 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 8 9 10 13 14 16 23 29 31 253 261 0 1 253 254 261 0 1 7 9 SUB A B C A B C V1 V2 V3 1 136 137 356 357 1 – 28 – PBLK OBCLP CLPDM WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 262H (1H: 780ck) units. ∗ Valid line count in this drive mode: 222 lines 355 356 357 CCD OUT 15 HDO CXD3611R Chart-3 Central Scan 2 Mode • ICX414/424 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 6 9 10 15 16 35 38 130 0 1 6 113 114 129 130 0 1 113 114 9 SUB A B C A B C V1 V2 1 282 283 284 209 210 211 PBLK OBCLP CLPDM WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 131H (1H: 780ck) units. ∗ Valid line count in this drive mode: 76 lines 282 283 284 CCD OUT 1 – 29 – V3 15 16 HDO CXD3611R Chart-4 Pixel Add Mode (Interlace) • ICX414/424 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 520 524 0 1 2 6 8 9 10 13 16 262 263 264 270 274 SUB D D V1 V2 V3 1357135 2468246 2468246 1357135 489 490 491 492 493 494 PBLK OBCLP CLPDM WEN SYNC BLK ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 262H (1H: 780ck) units. 489 490 491 492 493 494 – 30 – CCD OUT 278 HDO CXD3611R Chart-5 Progressive Scan Mode 50 78 100 120 150 200 Horizontal Direction Timing Chart • ICX414/424 MODE Applicable CCD image sensor (780) 0 HDO MCKO 35 107 123 125 4 H1 H2 35 71 V1 47 83 V2 59 72 95 95 V3 – 31 – 35 120 31 29 33 33 33 123 109 119 93 SUB PBLK 11 OBCLP (1) 9 OBCLP (2) 13 OBCLP (3) 9 OBCLP (4) Wide OBCLP CLPDM CXD3611R WEN Chart-6 • ICX414/424 Horizontal Direction Timing Chart (Frame shift: B) (High speed sweeping: C) 50 78 100 120 150 200 MODE Central Scan 1 Mode, Central Scan 2 Mode Applicable CCD image sensor (780) 0 HDO MCKO 35 107 123 125 4 H1 H2 35 71 107 143 179 215 V1 47 83 119 155 191 V2 59 95 131 167 203 – 32 – #1 72 95 V3 #2 #3 SUB PBLK OBCLP CLPDM WEN Frame Shift High Speed Sweep #167 (16H) #255 (24H) Central Scan 1 #142 (14H) CXD3611R Central Scan 2 #215 (20H) Chart-7 Pixel Add Mode (Interlace Mode) 50 78 100 120 150 200 Horizontal Direction Timing Chart • ICX414/424 MODE Applicable CCD image sensor (780) 0 HDO MCKO 35 107 123 125 4 H1 H2 35 53 71 89 V1 41 59 95 77 V2 47 65 83 101 V3 72 35 120 95 – 33 – 31 29 33 33 33 123 109 119 93 SUB PBLK 11 OBCLP (1) 9 OBCLP (2) 13 OBCLP (3) 9 OBCLP (4) Wide OBCLP CLPDM CXD3611R WEN Chart-8 Applicable CCD image sensor • ICX414/424 Horizontal Direction Timing Chart (Readout: A) MODE Progressive Scan Mode 35 47 59 71 83 95 107 520 582 632 35 47 59 71 83 95 (780) 0 (780) 0 HDO V1 V2 – 34 – V3 107 CXD3611R Chart-9 Applicable CCD image sensor • ICX414/424 Horizontal Direction Timing Chart Readout: D MODE Pixel Add Mode (Interlace) 35 41 47 53 59 65 71 77 83 89 95 101 107 113 119 125 131 137 520 582 632 (780) 0 (780) 0 HDO V1 V2 V3 Even Field (780) 0 (780) 0 HDO V1 V2 V3 CXD3611R 35 41 47 53 59 65 71 77 83 89 95 101 107 113 Odd Field – 35 – Chart-10 Applicable CCD image sensor • ICX414/424 Horizontal Direction Timing Chart (SSG Pulse) MODE Pixel Add Mode (Interlace) (780) 0 78 78 (780) 0 HDO 132 132 BLK 18 78 18 78 HSYNC 408 438 18 48 EQ 348 408 738 18 VSYNC – 36 – ∗ HSYNC, EQ and VSYNC are combined and output from the SYNC pin. They are not individual pulses output externally. CXD3611R Chart-11 Progressive Scan Mode (Non-Interlace) • ICX415 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 8 9 10 14 20 28 609 611 624 0 1 9 10 14 20 28 609 SUB E E V1 V2 CCD OUT PBLK OBCLP CLPDM WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 625H (1H: 944ck) units. 578 579 580 581 582 581 582 – 37 – 1234567812 V3 624 0 HDO 1234567812 CXD3611R Chart-12 Central Scan 1 Mode • ICX415 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 311 20 14 303 311 0 1 8 9 14 20 37 40 303 0 1 8 9 37 SUB E F G E F G V1 V2 V3 1 1 160 161 162 422 423 PBLK OBCLP CLPDM WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 312H (1H: 944ck) units. ∗ Valid line count in this drive mode: 264 lines 157 CCD OUT 421 422 423 40 HDO – 38 – CXD3611R Chart-13 Central Scan 2 Mode • ICX415 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 15 6 9 136 155 0 1 8 9 14 20 46 49 136 137 SUB E F G E G V1 V2 1 333 334 335 248 249 250 PBLK OBCLP CLPDM WEN ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 156H (1H: 944ck) units. ∗ Valid line count in this drive mode: 88 lines 333 334 335 CCD OUT 1 – 39 – V3 155 0 1 HDO CXD3611R Chart-14 Pixel Add Mode (Interlace) • ICX415 Vertical Direction Timing Chart MODE Applicable CCD image sensor VDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 8 10 14 17 21 312 313 314 320 327 331 335 312 18 SUB H H V1 V2 V3 1357135 2468246 2468246 1357135 577 578 579 580 581 582 PBLK OBCLP CLPDM WEN SYNC BLK ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ VDO in this chart is described in 3125H (1H: 944ck) units. 577 578 579 580 581 582 – 40 – CCD OUT 624 0 1 2 HDO CXD3611R Chart-15 Progressive Scan Mode 50 102 80 100 120 150 200 Horizontal Direction Timing Chart • ICX415 MODE Applicable CCD image sensor (944) 0 HDO MCKO 42 144 163 166 205 4 H1 H2 42 90 V1 58 106 V2 74 122 V3 99 122 – 41 – 42 36 34 39 39 39 120 SUB 155 PBLK 11 OBCLP (1) 9 OBCLP (2) 14 OBCLP (3) 9 OBCLP (4) 163 Wide OBCLP 145 155 CLPDM CXD3611R WEN Chart-16 • ICX415 Horizontal Direction Timing Chart (Frame shift: F) (High speed sweeping: G) MODE Central Scan 1 Mode, Central Scan 2 Mode Applicable CCD image sensor (944) 0 50 102 80 100 120 150 200 HDO MCKO 42 144 163 166 4 H1 H2 42 138 90 186 V1 58 106 154 202 V2 74 122 170 – 42 – #1 99 122 V3 #2 SUB PBLK OBCLP CLPDM WEN Frame Shift High speed Sweep #197 (20H) #299 (31H) Central Scan 1 #166 (17H) CXD3611R Central Scan 2 #254 (26H) Chart-17 Pixel Add Mode (Interlace) 50 102 80 100 120 150 200 Horizontal Direction Timing Chart • ICX415 MODE Applicable CCD image sensor (944) 0 HDO MCKO 42 144 163 166 205 4 H1 H2 42 114 66 90 V1 50 74 98 122 V2 58 82 106 130 V3 99 122 – 43 – 42 36 34 39 39 39 120 SUB 155 PBLK 11 OBCLP (1) 9 OBCLP (2) 14 OBCLP (3) 9 OBCLP (4) 163 Wide OBCLP 145 155 CLPDM CXD3611R WEN Chart-18 Applicable CCD image sensor • ICX415 Horizontal Direction Timing Chart (Readout: E) MODE Progressive Scan Mode 42 58 74 90 106 122 138 627 701 775 42 58 74 90 106 122 (944) 0 (944) 0 HDO V1 V2 – 44 – V3 138 CXD3611R Chart-19 Applicable CCD image sensor • ICX415 Horizontal Direction Timing Chart (Readout: H) MODE Pixel Add Mode (Interlace) 42 50 58 66 74 82 90 98 106 114 122 130 138 146 154 162 170 178 627 701 775 (944) 0 (944) 0 HDO V1 V2 V3 Even Field (944) 0 (944) 0 HDO V1 V2 V3 CXD3611R 42 50 58 66 74 82 90 98 106 114 122 130 138 146 Odd Field – 45 – Chart-20 Applicable CCD image sensor • ICX415 Horizontal Direction Timing Chart (SSG Pulse) MODE Pixel Add Mode (Interlace) (944) 0 102 102 (944) 0 HDO 177 177 BLK 22 95 22 95 HSYNC 494 530 22 58 22 58 EQ 421 494 893 22 22 – 46 – VSYNC ∗ HSYNC, EQ and VSYNC are combined and output from the SYNC pin. They are not individual pulses output externally. CXD3611R Chart-21 • ICX414/424/415 High-Speed Phase Timing Chart MODE Applicable CCD image sensor HDI HDO CKI ADCLK 1 35/42 107/144 MCKO – 47 – H1 H2 RG XSHP XSHD XRS ∗ HDO indicates the logical positional relationship when an H-Reset is applied to CXD3611R by HDI. The actual output requires a delay. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output, a delay is added to each pulse. ∗ The logical ADCLK can be specified by the serial interface data. ∗ Pin settings are in default. CXD3611R CXD3611R Application Circuit Block Diagram CCD ICX414/415/424 CCD OUT CDS/ADC CXD3301R Digital OUT CLPDM OBCLP ADCLK XSHD XSHP TEST PBLK RDM 20 21 22 23 24 25 26 H-Dr∗1 H1 H2 RG V1 V2 V3 15V SUB 16 17 14 52 54 58 TG CXD3611R 62 XRS 64 34 35 36 29 44 45 46 47 42 43 41 49 2 3 11 HDI VDI VDO HDO BLK SYNC WEN RST SNCSL SSGSL HDRS CDSRS Signal Processor Block ESG TRG MCKO ∗1 H-Dr is required when actually using a double speed drive mode. ∗2 Always input CKI using a sine wave below amplitude VDD. ∗3 The figure shows an application circuit block diagram corresponding to the use of an oscillator. 12 32 OSCI 31 OSCO 30 CKI∗2 38 39 40 37 4 SMD1 to 3 MD1 to 3 CCD SEN SCK SSI PS Micon Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes on Power-on Of the three –7.5V, +15.0V, +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential. 15.0V t1 20% 0V 20% t2 t2 ≥ t1 –7.5V – 48 – CXD3611R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 48 49 10.0 ± 0.1 33 32 A 64 1 0.5 b 16 0.13 M + 0.2 1.5 – 0.1 17 (0.22) 0.5 ± 0.2 0.1 EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.3g 0.1 ± 0.1 b = 0.18 ± 0.03 0˚ to 10˚ 0.5 ± 0.2 DETAIL B: PALLADIUM DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 P-LQFP64-10x10-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS 0.125 ± 0.04 (11.0) – 49 – Sony Corporation