CXG1040TN

CXG1040TN High Isolation DPDT Switch Description The CXG1040TN is a DPDT (Dual Pole Dual Throw) antenna switch MMIC used in Personal Communication handsets such as PCS. This IC is designed using the Sony’s GaAs J-FET process and operates with CMOS input. Features • CMOS input control • Insertion loss 0.5 dB (Typ.) at 2.0 GHz • High isolation 25 dB (Typ.) at 2.0 GHz • Small Package TSSOP-10pin Applications DPDT switch for digital cellular telephones such as PCS handsets. Structure GaAs J-FET MMIC 10 pin TSSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD 7 V • Control voltage Vctl 5 V • Input power Pin 25 dBm • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E99144-TE CXG1040TN Pin Configuration Unit : mm Block Diagram RF3 1 CTLA RF4 VDD GND RF3 5 10pin TSSOP (PLASTIC) 6 10 CTLB RF1 GND GND RF2 SW6 SW3 RF4 SW2 SW4 SW1 RF2 RF1 SW5 Recommended Circuit Rctl 1kΩ CTLA C1 100pF RF4 C2 100pF VDD C1 100pF Rctl 1kΩ 1 10 C1 100pF CTLB 2 9 C2 100pF RF1 3 CXG1040TN 8 Rrf 220kΩ 4 C2 100pF RF3 7 5 Rrf 220kΩ 6 C2 100pF RF2 When using the CXG1040TN, the following external components should be used: C1: This is used for signal line filtering 100 pF is recommended. C2: This is used for RF De-coupling and must be used in all applications. 100 pF is recommended. Rctl: This is used to give improved ESD performance. Rrf: This resistor is used to stabilize the dc operating point at high power levels. A value of 220 kΩ is recommended. —2— CXG1040TN Truth Table CTLA H H L L CTLB H L H L RF1 - RF2 ON RF2 - RF3 ON RF3 - RF4 ON RF4 - RF1 ON SW1 H L H L SW2 L H L H SW3 H L H L SW4 L H L H SW5 L H H L SW6 H L L H Operating Condition Control voltage (High) Control voltage (Low) Bias voltage Symbol Vctl (H) Vctl (L) VDD Min. 2.5 0 2.7 Typ. (Ta=–35 °C to +85 °C) Max. 3.6 0.5 4 Unit. V V V —3— CXG1040TN Electrical Characteristics (1) VDD=3 V, Vctl (L)=0 V, Vctl (H)=2.8 V±3 %, @2 GHz, Pin=10 dBm, Impedance at all ports : 50 Ω Item Insertion loss Isolation VSWR Input power for 1 dB compression 3rd order input intercept point Switching speed Bias current Control current ∗1 two-tone input power up to 10 dBm Symbol IL Iso VSWR P1dB IP3 Tsw IDD Ictl Min. 20 20 45 Typ. 0.5 25 1.3 24 1 0.7 80 Max. 0.8 1.5 (Ta=25 °C) Unit dB dB dBm dBm µs mA µA ∗1 5 1.1 150 Electrical Characteristics (2) VDD=3 V, Vctl (L)=0 V, Vctl (H)=2.8 V±3 %, @2 GHz, Pin=10 dBm, Impedance at all ports : 50 Ω Item Insertion loss Isolation VSWR Input power for 1 dB compression 3rd order input intercept point Switching speed Bias current Control current ∗1 two-tone input power up to 10 dBm Symbol IL Iso VSWR P1dB IP3 Tsw IDD Ictl Min. 20 20 45 Typ. 0.5 25 1.3 24 1 0.7 80 (Ta=–35 °C to +85 °C) Max. 1.0 1.5 dBm dBm µs mA µA Unit dB dB ∗1 5 1.3 180 —4— CXG1040TN Package Outline Unit : mm 10PIN TSSOP(PLASTIC) 1.2MAX ∗2.8 ± 0.1 10 6 0.1 ∗2.2 ± 0.1 + 0.15 0.1 – 0.05 3.2 ± 0.2 1 5 0.5 0.25 0° to 10° + 0.08 0.22 – 0.07 0.1 M (0.2) + 0.08 0.22 – 0.07 DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-10P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02g —5— (0.1) + 0.025 0.12 – 0.015 A 0.45 ± 0.15