CXG1045N

CXG1045N High Power DPDT Switch for GSM For the availability of this product, please contact the sales office. Description The CXG1045N is a DPDT (Dual Pole Dual Throw) antenna switch MMIC used in personal communication handsets such as GSM, GSM1800 or dualband. This IC is designed using the Sony's GaAs J-FET process. Features • Low insertion loss: 8 pin SSOP (Plastic) 0.4dB (Typ.) @900MHz 0.7dB (Typ.) @1.8GHz • High power switching P1dB: 38dBm (Typ.) @900MHz 37dBm (Typ.) @1.8GHz • Small package SSOP-8pin: (3 × 6.4 × 1.25mm) • Low current: 200µA (Typ.) Application • GSM900 or GSM1800 handsets • GSM900/GSM1800 dualband handsets Structure GaAs J-FET MMIC Operating Condition Control voltage: Vctl (H) – Vctl (L): 2.5 to 5V @Ta = 25°C ∗ GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98902A92-PS CXG1045N Block Diagram RF1 RF4 RF2 RF3 VCTLA High Low VCTLB Low High RF1 – RF2, RF3 – RF4 ON RF2 – RF3, RF4 – RF1 OFF RF1 – RF2, RF3 – RF4 OFF RF2 – RF3, RF4 – RF1 ON Electrical Characteristics (1) Item Insertion loss Symbol ∗3, ∗4 IL ∗1, ∗2, ∗5 ∗3, ∗4 Isolation VSWR 2nd harmonics ISO VSWR 2fo ∗1, ∗2, ∗5 ∗1 to ∗5 ∗1, ∗2 ∗3 ∗1, ∗2 3rd harmonics 3fo ∗3 ∗3 Input power for 1dB compression Switching time Control current ∗1 ∗2 ∗3 ∗4 ∗5 P1dB TSW I CTL 0/5V control ∗1, ∗2 36 35 38 37 100 200 18 15 Condition Min. Typ. 0.4 0.7 21 17 1.2 1.4 (Ta = 25°C) Max. 0.7 1.0 Unit dB dB dB dB –31 –31 –31 –31 dBm dBm dBm dBm dBm dBm 500 350 ns µA RF Input terminal is RF2. (RF2 → RF1, RF2 → RF3), Pin = 32dBm, 1710 to 1785MHz, 0/5V control RF Input terminal is RF4. (RF4 → RF1, RF4 → RF3), Pin = 32dBm, 1710 to 1785MHz, 0/5V control RF Input terminal is RF4. (RF4 → RF1, RF4 → RF3), Pin = 34.5dBm, 880 to 915MHz, 0/5V control Pin = 10dBm, 925 to 960MHz, 0/5V control Pin = 10dBm, 1805 to 1880MHz, 0/5V control –2– CXG1045N Electrical Characteristics (2) Item Insertion loss Symbol ∗3, ∗4 IL ∗1, ∗2, ∗5 ∗3, ∗4 Isolation VSWR 2nd harmonics ISO VSWR 2fo ∗1, ∗2, ∗5 ∗1 to ∗5 ∗1, ∗2 ∗3 ∗1, ∗2 3rd harmonics 3fo ∗3 ∗3 Input power for 1dB compression Switching time Control current ∗1 ∗2 ∗3 ∗4 ∗5 P1dB TSW I CTL 0/5V control ∗1, ∗2 36 35 38 37 100 200 18 15 Condition Min. Typ. 0.4 0.7 21 17 1.2 (Ta = –20 to +70°C) Max. 1.0 1.3 Unit dB dB dB dB 1.4 –31 –31 –31 –31 dBm dBm dBm dBm dBm dBm 500 400 ns µA RF Input terminal is RF2. (RF2 → RF1, RF2 → RF3), Pin = 32dBm, 1710 to 1785MHz, 0/5V control RF Input terminal is RF4. (RF4 → RF1, RF4 → RF3), Pin = 32dBm, 1710 to 1785MHz, 0/5V control RF Input terminal is RF4. (RF4 → RF1, RF4 → RF3), Pin = 34.5dBm, 880 to 915MHz, 0/5V control Pin = 10dBm, 925 to 960MHz, 0/5V control Pin = 10dBm, 1805 to 1880MHz, 0/5V control –3– CXG1045N Package Outline/Pin Configuration RF3 5 GND 6 CTLB 7 RF4 8 8-pin SSOP (PLASTIC) 4 RF2 3 GND 2 CTLA 1 RF1 Recommended Circuit CRF (100pF) RF3 47kΩ GND RCTL (1kΩ) CTLB Cbypass (100pF) RF4 CRF (100pF) 8 1 47kΩ 7 6 CXG1045N 2 3 Cbypass (100pF) RCTL (1kΩ) CTLA 5 4 CRF (100pF) GND RF2 RF1 CRF (100pF) ∗ Recommended to use DC blocking capacitors (CRF) and bypass capacitors (Cbypass). ∗ Recommended to use control resistors (RCTL), when it is necessary to reduce the current consumption or to improve the electrostatic discharge (ESD) strength. Absolute Maximum Ratings • Control voltage Vctl • Operating temperature Topr • Storage temperature Tstg 7 –35 to +85 –65 to +150 V @Ta = 25°C °C °C –4– CXG1045N Package Outline Unit: mm 8PIN SSOP (PLASTIC) ∗3.0 ± 0.1 + 0.2 1.25 – 0.1 0.1 8 5 A ∗4.4 ± 0.1 1 4 0.65 + 0.08 0.24 – 0.07 B 0.25 0.13 M 0.1 ± 0.05 6.4 ± 0.2 (0.22) (0.15) + 0.025 0.17 – 0.015 + 0.08 0.24 – 0.07 0° to 10° DETAIL A DETAIL B NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-8P-L01 SSOP008-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER ALLOY 0.04g –5– (0.5) 0.6 ± 0.15