CXG1050TN

CXG1050TN Receiving Dual-Band Mixer Description The CXG1050TN is a receiving dual-band mixer MMIC. This IC is designed using the Sony's GaAs JFET process. Features • High conversion gain Gc = 9.5dB (Typ.) • Low noise figure NF = 4.9 to 5.2dB (Typ.) • Low distortion Input IP3 = –0.5 to 0dBm (Typ.) • Single 2.7V power supply operation • Low LO input power operation PLO = –15dBm • 16-pin TSSOP small package Applications 800MHz Japan digital cellular telephones (PDC) Structure GaAs J-FET MMIC 16 pin TSSOP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 4.5 V • Input power PIN +5 dBm • Current consumption IDD (Mixer block) 20 mA • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C Recommended Operating Conditions • Supply voltage VDD 2.7 to 3.3 • Control voltage VCTL (H) VCTL (L) 2.4 to 3.3 0 to 0.3 V V V Block Diagram Pin Configuration RFIN1 RFIN1 9 8 RFIN2 9 8 7 6 5 4 3 2 1 RFIN2 GND VDD2 CAP CAP CTL2 LOIN OPT GND 10 VDD1 11 CAP 12 CAP 13 IFOUT 15 2 LOIN CTL1 14 IFOUT/VDD3 15 NC 16 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98432-PS CXG1050TN Electrical Characteristics Conditions: VDD = 2.7V, VCTL (H) = 2.7V, VCTL (L) = 0V, fRF1 = 820MHz, fRF2 = 870MHz, fLO = fRF – 130MHz, PLO = –15dBm, unless otherwise specified (Ta = 25°C) Item Current consumption Control current Symbol Path VDD1, VDD2 VDD3 → GND CTL1 → GND CTL2 → GND RFIN1 → IFOUT Conversion gain GC RFIN2 → IFOUT RFIN1 → IFOUT RFIN2 → IFOUT RFIN1 → IFOUT Input IP3 IIP3 RFIN2 → IFOUT LO to RF leak level LOIN → RFIN1 LOIN → RFIN2 L H L H L H –3 — — –0.5 –37 –37 — –30 –30 Control pin condition VCTL1 H L H L H L H L H L H VCTL2 L H L H L H L H L H L 7 — — 7 — — –2.5 9.5 –16 –13 9.5 4.9 5.2 0 12 –12 –9 12 6.5 6.5 — dB PRF = –25dBm, offset = 100kHz Conversion by dBm the IM3 suppression ratio for twowave input dBm fLO = 690MHz fLO = 740MHz dB When a small signal Min. Typ. Max. Unit Measurement condition IDD — 6.3 7.5 mA When no signal ICTL — 18 35 µA Noise figure NF PLK Note) The values shown above are the specified values on the Sony's recommended evaluation board. –2– CXG1050TN Recommended Evaluation Circuit L6 L7 10 R1 VDD1 (LO AMP 1) C11 L4 12 C9 13 C7 CTL1 IFOUT 50Ω VDD3 (MIX) C2 C5 L1 15 L2 C3 C1 R3 16 1 2 C4 L3 14 3 C6 LOIN 50Ω 4 C8 CTL2 5 C10 11 6 L5 C12 7 R2 VDD2 (LO AMP 2) C13 9 8 L9 C14 L8 RFIN1 50Ω RFIN2 50Ω L1 L2 L3 L4 L5 L6 L7 L8 L9 82nH 39nH 27nH 47nH 39nH 39nH 10nH 33nH 8.2nH C1 C2 C3 C4 C5 C6 C7 C8 C9 12pF 1000pF 1000pF 100pF 100pF 100pF 1000pF 1000pF 100pF C10 C11 C12 C13 C14 R1 R2 R3 100pF 100pF 100pF 2pF 2pF 680Ω 680Ω 820Ω –3– CXG1050TN Example of Representative Characteristics (Ta = 25°C) Path RFIN1 → IFOUT Gc, NF vs. fRF 12 Gc – Conversion gain, NF – Noise figure [dB] Gc – Conversion gain, NF – Noise figure [dB] VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fLO = fRF – 130MHz PLO = –15dBm 12 Path RFIN2 → IFOUT Gc, NF vs. fRF VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fLO = fRF – 130MHz PLO = –15dBm 10 Gc 10 Gc 8 8 6 NF 4 6 NF 4 2 800 820 840 860 880 900 2 800 820 840 860 880 900 fRF – RF frequency [MHz] fRF – RF frequency [MHz] Path RFIN1 → IFOUT POUT, IM3 vs. PIN 20 20 Path RFIN2 → IFOUT POUT, IM3 vs. PIN POUT – IF output power [dBm] POUT –20 POUT – IF output power [dBm] 0 0 POUT –20 –40 IM3 –60 –80 –40 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF1 = 820MHz fRF2 = 820.1MHz fLO = 690MHz PLO = –15dBm –10 0 –40 IM3 –60 –30 –20 –80 –40 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF1 = 870MHz fRF2 = 870.1MHz fLO = 740MHz PLO = –15dBm –10 0 –30 –20 PIN – RF input power [dBm] PIN – RF input power [dBm] –4– CXG1050TN Path RFIN1 → IFOUT Gc, NF vs. PLO 12 Gc – Conversion gain, NF – Noise figure [dB] Gc 10 Gc – Conversion gain, NF – Noise figure [dB] 12 Path RFIN2 → IFOUT Gc, NF vs. PLO Gc 10 8 6 NF 4 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz 8 6 NF VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz 4 2 –25 –20 –15 –10 –5 0 2 –25 –20 –15 –10 –5 0 PLO – LO input power [dBm] PLO – LO input power [dBm] Path RFIN1 → IFOUT IIP3, PLK vs. PLO 2 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz IIP3 0 –35 –25 2 Path RFIN2 → IFOUT IIP3, PLK vs. PLO –25 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz PLK – LO leak power [dBm] IIP3 – Input IP3 [dBm] IIP3 – Input IP3 [dBm] 1 –30 1 –30 0 IIP3 –35 –1 PLK –40 –1 PLK –40 –2 –25 –20 –15 –10 –5 0 –45 –2 –25 –20 –15 –10 –5 0 –45 PLO – LO input power [dBm] PLO – LO input power [dBm] –5– PLK – LO leak power [dBm] CXG1050TN Example of Characteristics for Option Resistance R3 Changed (Ta = 25°C) IDD3 vs. R3 10 IDD3 – Mixer block current consumption [mA] 8 6 4 2 VDD = 2.7V VCTL1 = 2.7V, VCTL2 = 0V or VCTL1 = 0V, VCTL2 = 2.7V 1.5k 820 470 270 R3 – Option resistance [Ω] 150 0 OPEN Path RFIN1 → IFOUT Gc, NF vs. R3 12 Gc – Conversion gain, NF-Noise figure [dB] Gc – Conversion gain, NF-Noise figure [dB] 12 Path RFIN2 → IFOUT Gc, NF vs. R3 10 Gc VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz PLO = –15dBm NF 10 Gc VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz PLO = –15dBm NF 8 8 6 6 4 4 2 OPEN 1.5k 820 470 270 R3 – Option resistance [Ω] 150 2 OPEN 1.5k 820 470 270 R3 – Option resistance [Ω] 150 Path RFIN1 → IFOUT IIP3, PLK vs. R3 4 –25 4 Path RFIN2 → IFOUT IIP3, PLK vs. R3 –25 PLK – LO leak power [dBm] IIP3 – Input IP3 [dBm] IIP3 – Input IP3 [dBm] 2 –30 2 –30 IIP3 0 VDD = 2.7V VCTL1 = 2.7V VCTL2 = 0V fRF = 820MHz fLO = 690MHz PLO = –15dBm –35 IIP3 0 VDD = 2.7V VCTL1 = 0V VCTL2 = 2.7V fRF = 870MHz fLO = 740MHz PLO = –15dBm –35 PLK –2 PLK –2 –40 –40 –4 OPEN 1.5k 820 470 270 R3 – Option resistance [Ω] –45 150 –4 OPEN 1.5k 820 470 270 R3 – Option resistance [Ω] –45 150 –6– PLK – LO leak power [dBm] CXG1050TN Recommended Evaluation Board Front 25mm SONY CXG1050TN EVB RFIN1 L7 L6 C13 R1 C11 L4 C9 C7 C5 C1 L1 IFOUT C2 L2 C3 R3 C4 L3 LOIN C10 C8 C6 L9 L8 C14 L5 C12 R2 RFIN2 CTL1 VDD3 GND VDD1/2 CTL2 Back CTL2 VDD1/2 GND VDD3 CTL1 Glass fabric-base 4-layer epoxy board (thickness: 0.3mm × 2) GND for the 2nd and 3rd layers –7– CXG1050TN Package Outline Unit: mm 16PIN TSSOP(PLASTIC) 1.2MAX 4.1 2.05 A 16 X S B 9 X2 0.2 SAB 0.08 S 0.1 (3.0) 0.1 ± 0.05 0.25 2.9 0.1 X 0.5 0.1 SA B 0° to 8° 0.08 M S A B 0.2 ± 0.02 + 0.036 0.22 – 0.03 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-16P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.03g –8– 0.1 ± 0.01 + 0.026 0.12 – 0.02 0.45 ± 0.1 1 8 X4 3.9