CXG1172UR

CXG1172UR JPHEMT High Power DPDT Switch with Logic Control Description The CXG1172UR can be used in wireless communication systems, for example, CDMA handsets, W-CDMA handsets. The IC has on-chip logic for operation with 1 CMOS control input. The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit. Features • Low insertion loss: 0.3dB@900MHz, 0.45dB@2GHz • 1 CMOS compatible control line • Small package size: 12-pin UQFN Applications Antenna switch for cellular handsets W-CDMA, CDMA Structure GaAs JPHEMT MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD 7 V • Control voltage Vctl 5 V • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C 12 pin UQFN (Plastic) GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04522-PS CXG1172UR Block Diagram and Recommended Circuit RF3 GND CRF CRF RF2 6 5 4 GND 7 F3 CRF F2 F1 3 GND CRF 8 F4 2 RF1 RF4 GND 9 10 11 12 1 GND Cbypass (100pF) Cbypass (100pF) Rctl (1kΩ) VDD GND CTL When using this IC, the following external components should be used. Rctl: This resistor is used to improve ESD performance. 1kΩ is recommended. CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table CTL L H ON state RF1 – RF2, RF3 – RF4 RF2 – RF3, RF4 – RF1 OFF state RF2 – RF3, RF4 – RF1 RF1 – RF2, RF3 – RF4 F1 ON OFF F2 OFF ON F3 ON OFF F4 OFF ON –2– CXG1172UR DC Bias Condition Item Vctl (H) Vctl (L) VDD Min. 2.0 0 2.5 Typ. 2.85 — 2.85 (Ta = 25°C) Max. 3.6 0.4 3.6 Unit V V V Electrical Characteristics Item Insertion loss Symbol IL Condition 900MHz 1500MHz 2000MHz 900MHz Isolation VSWR Switching speed 1dB compression input power Input IP3 ACLR ISO. VSWR TSW P1dB IIP3 ACLR1 ACLR2 2fo Harmonics 3fo 2fo 3fo Bias current Control current IDD Ictl ∗1 , ∗ 2 ∗3 ∗1, ±5MHz ∗1, ±10MHz ∗1 ∗1 ∗2 ∗2 VDD = 2.85V Vctl (H) = 2.85V 33 50 60 –60 –60 –75 –75 –75 –75 25 15 1500MHz 2000MHz 50Ω 14 10 8 Min. Typ. 0.30 0.35 0.45 22 18 16 1.2 8 (Ta = 25°C) Max. 0.50 0.55 0.65 Unit dB dB dB dB dB dB 1.5 — µs dBm dBm –50 –55 –55 –55 –60 –60 50 25 dBc dBc dBc dBc dBc dBc µA µA ∗1 Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 1920 to 1980MHz ∗2 Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 900MHz ∗3 Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/2.85V control, VDD = 2.85V –3– CXG1172UR Pin Description Pin No. 2 4 6 8 10 12 1, 3, 5, 7, 9, 11 Symbol RF1 RF2 RF3 RF4 VDD CTL GND Description RF input/output. Connect capacitor (recommended value: 100pF) in use RF input/output. Connect capacitor (recommended value: 100pF) in use RF input/output. Connect capacitor (recommended value: 100pF) in use RF input/output. Connect capacitor (recommended value: 100pF) in use DC power supply Logic control GND –4– CXG1172UR Package Outline Unit: mm 12PIN UQFN (PLASTIC) x4 0.1 2.0 0.55 ± 0.05 0.4 ± 0.1 0.6 C 6 A B S A-B C 4-R0.2 9 10 7 2.0 12 1 3 4 0.4 PIN 1 INDEX 0.18 0.07 0.25 0.05 M S A-B C 0.14 0. 26 0.05 S S Solder Plating + 0.09 0.14 – 0.03 + 0.09 0.25 – 0.03 MAX0.02 S TERMINAL SECTION Note:Cutting burr of lead are 0.05mm MAX. SONY CODE EIAJ CODE JEDEC CODE UQFN-12P-01 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.01g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm –5– Sony Corporation