CXG1188UR

High Power DPDT Switch with Logic Control CXG1188UR Description The CXG1188UR can be used in wireless communication systems, for example, CDMA handsets with GPS. The IC has on-chip logic for operation with 1 CMOS control input. The Sony J-FET process is used for low insertion loss and on-chip logic circuit. (Applications: Dual-band cellular handsets, CDMA with GPS, dual-band CDMA) Features Low insertion loss: 0.30dB@900MHz, 0.45dB@1900MHz High linearity: IIP3 = 65dBm (Typ.) 1 CMOS compatible control line Package Small package size: 12-pin UQFN Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) Bias voltage Control voltage Operation temperature Storage temperature VDD Vctl Topr Tstg 7 5 –35 to +85 –65 to +150 V V °C °C This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E05465-PS CXG1188UR Block Diagram and Recommended Circuit RF3 GND CRF CRF RF2 6 5 4 GND 7 F3 CRF F2 F1 3 GND CRF 8 F4 2 RF1 RF4 GND 9 10 11 12 1 GND Cbypass (100pF) VDD GND CTL When using this IC, the following external components should be used: CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table CTL L H ON state RF1 – RF2, RF3 – RF4 RF2 – RF3, RF4 – RF1 OFF state RF2 – RF3, RF4 – RF1 RF1 – RF2, RF3 – RF4 F1 ON OFF F2 OFF ON F3 ON OFF F4 OFF ON DC Bias Conditions (Ta = 25°C) Item Vctl (H) Vctl (L) VDD Min. 2.0 0 2.7 Typ. 3.0 — 3.0 Max. 3.6 0.4 3.6 Unit V V V -2- CXG1188UR Electrical Characteristics (Ta = 25°C) Item Insertion loss Symbol IL Condition 900MHz 1.9GHz 900MHz 1.9GHz 50Ω *1 Min. Typ. 0.30 0.45 Max. 0.55 0.70 Unit dB dB dB dB — Isolation VSWR ISO. VSWR 2fo 18 14 21 16 1.2 –75 –75 –75 –75 –60 –60 –60 –60 dBc dBc dBc dBc dBm dBm dBm µs µA µA *3 *1 Harmonics 3fo *3 *2 Input IP3 1dB compression input power Switching speed Bias current Control current *1 *2 *3 *4 IIP3 P1dB TSW IDD Ictl 55 55 32 65 65 35 1 5 130 100 *4 VDD = 2.8V VDD = 3.0V Vctl (H) = 3.0V 55 40 Pin = 25dBm, 0/3V control, VDD = 3.0V, 900MHz Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/3V control, VDD = 3.0V Pin = 25dBm, 0/3V control, VDD = 3.0V, 1.9GHz Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/3V control, VDD = 3.0V Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol GND RF1 GND RF2 GND RF3 GND RF4 GND VDD GND CTL Description Control signal input RF signal input GND RF signal output GND RF signal input GND RF signal output GND Power supply input GND Control signal input -3- CXG1188UR Package Outline (Unit: mm) 12PIN UQFN PLASTIC x4 0.1 S A-B C 2.0 0.55 ± 0.05 0.4 ± 0.1 0.6 4-R0.2 C B 9 10 7 6 2.0 A 12 1 3 4 0.4 0.14 Thermal Die Pad 0.18 0.07 0.25 0.05 M S A-B C PIN 1 INDEX 0.05 S S Solder Plating + 0.09 0.14 – 0.03 + 0.09 0.25 – 0.03 MAX0.02 5-18µm S TERMINAL SECTION Note:Cutting burr of lead are 0.05mm MAX. SONY CODE EIAJ CODE JEDEC CODE UQFN-12P-01 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.01g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% -4- Sony Corporation