CXG7001FN

CXG7001FN Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS Description The CXG7001FN is a MMIC consisting of the power amplifier, antenna switch and low noise down conversion mixer. This IC is designed using the Sony’s GaAs J-FET process featuring a single positive power supply operation. Features • Operates at a single positive power supply: VDD = 3V • Small mold package: 26-pin HSOF • Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz) • High power gain: Gp = 39dB Typ. (POUT = 20.2dBm, f = 1.9GHz) • Low current consumption: IDD = 5.5mA Typ. (When no signal) • High conversion gain: Gc = 20.5dB Typ. (f = 1.9GHz) • Low distortion: Input IP3 = –13dBm Typ. (f = 1.9GHz) • High image suppression ratio: IMR = 40dBc Typ. (f = 1.9GHz) • High 1/2 IF suppression ratio: 1/2IFR = 44dBc Typ. (f = 1.9GHz) Applications Japan digital cordless telephones (PHS) Structure GaAs J-FET MMIC 26 pin HSOF (Plastic) Absolute Maximum Ratings • Supply voltage VDD • Voltage between gate and source VGSO • Gain control voltage VPCTL • Drain current IDD • Allowable power dissipation PD Control voltage • Supply voltage • Input power 6 1.5 2.5 550 3 V V V mA W VCTL 6 V VDD PRF 6 +10 V dBm • Channel temperature Tch • Operating temperature Topr • Storage temperature Tstg 150 –35 to +85 –65 to +150 °C °C °C Recommended Operating Conditions • Supply voltage VDD • Gain control voltage VPCTL • Control voltage (H) • Control voltage (L) 2.7 to 3.3 V to VDD–1.0 V Notes on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. VCTL (H) 2.9 to 3.3 VCTL (L) 0 to 0.2 V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04139-PS CXG7001FN Block Diagram and External Circuit 2.2nH PIN 14 13 (VGG1) 1kΩ 15 12 100pF VPCTL VDD1 1nF VDD2 1nF VDD3 10nF 18nH 16 1nF 11 2.2nH VGG2 18nH 17 30pF 18 10 1pF 9 30pF (POUT) 1.8nH (TX) 19 8 100pF VCTL1 (RX) 30pF VCTL2 100pF (RFIN) 10nH 6.8nH 20 7 30pF ANT 21 6 22 10pF 5 3.9nH VDD (RF AMP) 23 13pF 24 4 13pF 3 1nF 25 100nF VDD (IF AMP, MIX) 1nF 26 82nH 5pF 2 18pF 1 1nF VDD (LO AMP) LOIN IFOUT Pin Configuration PIN 14 GND 15 VDD1 16 VDD2 17 VDD3 18 GND 19 RX 20 VCTL2 21 RFIN 22 CAP 23 GND 24 CAP 25 IFOUT/VDD (IF AMP, MIX) 26 13 VGG1 12 VPCTL 11 VGG2 10 POUT 9 8 7 6 5 4 3 2 1 Tx VCTL1 ANT GND GND VDD (RF AMP) GND VDD (LO AMP) LOIN 26 pin – HSOF (Plastic) –2– CXG7001FN Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol LOIN GND GND GND ANT VCTL1 TX POUT VGG2 VPCTL VGG1 PIN GND VDD1 VDD2 VDD3 GND RX VCTL2 RFIN CAP GND CAP IFOUT/VDD (IF AMP, MIX) LO signal input. GND. GND. GND. Antenna switch. Either ANT-Tx or ANT-Rx is depending on whether the setting is VCTL1 or VCTL 2. Antenna switch control Pin 1. Tx. Input the signal into the antenna switch when ANT-Tx. Power amplifier output. Power amplifier (the final-stage FET) gate voltage adjustment Pin 2. The first-stage FET control pin for the power amplifier. Power amplifier (the first-stage FET, the second-stage FET) gate voltage adjustment Pin 1. Signal input into the power amplifier. GND. Power amplifier (the first-stage FET) VDD1. Power amplifier (the second-stage FET) VDD2. Power amplifier (the final-stage FET) VDD3. GND. Rx. Output ANT input signal into Rx when ANT-Rx. Antenna switch control Pin 2. RF signal input. Connector for the external capacitor. Connected to LNA FET source. Self-vibration frequency becomes 1.9GHz by this capacitor (Typ. 13pF). GND. Connector for the external capacitor. IF AMP distortion is corrected by this capacitor. IF output and IF AMP, MIX VDD. VDD (LO AMP) LO AMP VDD. VDD (RF AMP) RF AMP VDD. Description –3– CXG7001FN Electrical Characteristics 1. Control Pin Logic for Antenna Switch Conditions of control pins VCTL1 = 3V, VCTL2 = 0V VCTL1 = 0V, VCTL2 = 3V ANT – TX ON OFF ANT – RX OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are those when the Sony's recommended evaluation board, shown on page 7, is used. Unless otherwise specified: VDD = 3V, VPCTL = 2V, VCTL1 = 3V, VCTL2 = 0V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz, Ta = 25°C Item Current consumption Gate voltage adjustment value Output power Power gain Adjacent channel leak power ratio (600 ± 100kHz) Adjacent channel leak power ratio (900 ± 100kHz) Occupied bandwidth 2nd-order harmonic level 3rd-order harmonic level IDD VGG POUT GP ACPR600kHz ACPR900kHz OBW — — Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin 20.2 36 39 –63 –70 250 Symbol Measurement conditions Min. Typ. Max. Unit 150 0.04 0.25 0.60 mA V dBm dB –55 dBc –60 dBc 275 kHz –25 dBc –25 dBc 3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block These specifications are those when the Sony's recommended evaluation board, shown on page 7, is used. Unless otherwise specified: VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF1 = 1.90GHz/–35dBm, LO = 1.66GHz/–15dBm, Ta = 25°C Item Current consumption Conversion gain Noise figure Input IP3 Image suppression ratio 1/2 IF suppression ratio 2 × LO–IF suppression ratio 2 × LO+IF suppression ratio LO to ANT leak PLK IDD GC NF IIP3 IMR 1/2IFR — — Symbol Measurement conditions When no signal When a small signal When a small signal ∗1 RF2 = 1.42GHz/–35dBm RF2 = 1.78GHz/–35dBm RF2 = 3.08GHz/–35dBm RF2 = 3.56GHz/–35dBm 17 Min. Typ. Max. Unit 5.5 20.5 4.2 –17.5 –13 30 39 39 24 40 44 47 62 –42 5.5 7.5 mA dB dB dBm dBc dBc dBc dBc –37 dBm ∗1 Conversion from IM3 suppression ratio during FR1 = 1.9000GHz/–35dBm and FR2 = 1.9006GHz/–35dBm input. –4– CXG7001FN Example of Representative Characteristics 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C) POUT, ACPR600kHz vs. PIN VDD = 3V, VPCTL = 2V, VGG = const., VCTL1 = 3V, VCTL2 = 0V IDD = 150mA (@POUT = 20.2dBm), PIN = var. 25 –40 Gp, ACPR600kHz vs. VPCTL VDD = 3V, VPCTL = var., VGG = const., VCTL1 = 3V, VCTL2 = 0V IDD = 150mA (@VPCTL = 2V), PIN = var., POUT = 20.2dBm 45 GP –40 ACPR600kHz – Adjacent channel leak power ratio [dBc] 20 –45 POUT 40 –45 15 –50 35 –50 10 –55 30 –55 5 ACPR600kHz 0 –60 25 ACPR600kHz 20 –60 –65 –65 –5 –40 –35 –30 –25 –20 –15 –70 –10 15 0 0.5 1.0 1.5 2.0 2.5 VPCTL – Gain control voltage [V] –70 3.0 PIN – Input power [dBm] POUT, ACPR600kHz vs. VDD VDD = var., VPCTL = 2V, VGG = const., VCTL1 = 3V, VCTL2 = 0V IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = –19.3dBm 23 –40 Gp, ACPR600kHz vs. IDD VDD = 3V, VPCTL = 2V, VGG = var., VCTL1 = 3V, VCTL2 = 0V IDD = var., PIN = var., POUT = 20.2dBm 42 –40 ACPR600kHz – Adjacent channel leak power ratio [dBc] 22 –45 POUT 41 –45 GP 21 –50 40 –50 20 ACPR600kHz –55 39 ACPR600kHz 38 –55 19 –60 –60 18 –65 37 –65 17 2.0 2.5 3.0 3.5 4.0 4.5 –70 5.0 36 100 120 140 160 180 200 –70 220 VDD – Supply voltage [V] IDD – Current consumption [mA] –5– ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT – Output power [dBm] Gp – Power gain [dB] ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT – Output power [dBm] Gp – Power gain [dB] CXG7001FN 2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C) GC, NF vs. PLO VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF = 1.90GHz/small signal, LO = 1.66GHz 22 5.50 POUT – IF output power, PIM3 – 3rd-order intermodulation distortion power [dBm] POUT, PIM3 vs. PIN VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz, LO = 1.66GHz/–15dBm 20 21 GC – Convertion gain [dB] 5.25 GC NF – Noise figure [dB] 0 POUT –20 20 5.00 19 4.75 –40 PIM3 –60 18 NF 17 4.50 4.25 –80 Input IP3 –100 –50 –40 –30 –20 –10 0 16 –25 4.00 –20 –15 –10 –5 0 PLO – Local input [dBm] PIN – RF input power [dBm] Input IP3, PLK vs. PLO VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF = 1.90GHz/–35dBm, LO = 1.66GHz –10 Input IP3 –12 –35 –30 PLK – LO to ANT leak level [dBm] Input IP3 [dBm] –14 –40 –16 PLK –18 –45 –50 –20 –55 –22 –25 –60 –20 –15 –10 –5 0 PLO – Local input [dBm] –6– CXG7001FN Recommended Evaluation Board Via Hole PAIN VPCTL VDD_PA VCTL2 VCTL1 VGG ANT VDD_LNA IFOUT VDD_IF Via Hole VDD_LO LOIN Glass fabric-base epoxy board (4 layers) Thickness between 1 and 2: 0.2mm Dimensions: 50mm × 50mm VCTL2 VDD (PA) VDD (LO) VCTL1 VPCTL VGG VDD (IF) VDD (LNA) Enlarged Diagram of External Circuit Block R1 R1 = 1k L1 = 1.8nH L2 = 2.2nH L3 = 3.9nH C1 L2 C6 C6 C3 C7 C4 L5 L4 C10 C2 C5 C8 L7 C4 C8 C7 C6 L3 C8 L6 C8 L2 C7 C8 C9 L6 C6 L1 L4 = 6.8nH L5 = 10nH L6 = 18nH L7 = 82nH C1 = 1pF C2 = 5pF C3 = 10pF C4 = 13pF C5 = 18pF C6 = 30pF C7 = 100pF C8 = 1nF C9 = 10nF C10 = 100nF C8 –7– CXG7001FN Package Outline Unit: mm HSOF 26PIN (PLASTIC) 0.9 ± 0.1 ∗5.6 ± 0.05 A 26 14 0.08 S 5.5 4.2 3.8 ± 0.05 4.4 ± 0.1 (1.5) (0.7) 0.5 1 0.4 0.07 M S A 13 S 0.2 4.4 0.2 Solder Plating 0.2 ± 0.05 B + 0.05 0.14 – 0.03 NOTE: Dimension “ ∗” does not include mold protrusion. DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE HSOF-26P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.06g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm (0.2) + 0.05 0.2 0 0.4 –8– (1.75) Sony Corporation 0.45 ± 0.15