CXK581000AP-70LL

CXK581000ATM/AYM/AM/AP -55SL/70SL/10SL 131072-word × 8-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. Description The CXK581000ATM/AYM/AM/AP is a high speed CMOS static RAM organized as 131072-words by 8 bits. A polysilicon TFT cell technology realized extremely low stand- by current and higher data retention stability. Special feature are low power consumption, high speed and broad package line-up. The CXK581000ATM/AYM/AM/AP ia a suitable RAM for portable equipment with battery back up. Features • Fast access time: CXK581000ATM/AYM/AM/AP (Access time) -55LL/55SL 55ns (Max.) -70LL/70SL 70ns (Max.) -10LL/10SL 100ns (Max.) • Low standby current: CXK581000ATM/AYM/AM/AP -55LL/70LL/10LL 20µA (Max.) -55SL/70SL/10SL 12µA (Max.) • Low data retention current CXK581000ATM/AYM/AM/AP -55LL/70LL/10LL 12µA (Max.) -55SL/70SL/10SL 4µA (Max.) • Single +5V supply: +5V ±10% • Low voltage data retention: 2.0V (Min.) • Broad package line-up • CXK581000ATM/AYM 8mm × 20mm 32 pin TSOP package • CXK581000AM 525mil 32 pin SOP package • CXK581000AP 600mil 32 pin DIP package Functions 131072-word × 8-bit static RAM Structure Silicon gate CMOS IC CXK581000ATM 32 pin TSOP (Plastic) CXK581000AYM 32 pin TSOP (Plastic) -55LL/70LL/10LL CXK581000AM 32 pin SOP (Plastic) CXK581000AP 32 pin DIP (Plastic) Block Diagram A10 A11 A9 A8 A13 A15 A16 A14 A12 A7 VCC Buffer Row Decoder Memory Matrix 1024 × 1024 GND A6 A5 A4 A3 A2 A1 A0 Buffer I/O Gate Column Decoder OE Buffer WE I/O Buffer CE1 CE2 I/O 1 I/O 8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92756D53-PP CXK581000ATM/AYM/AM/AP Pin Configuration (Top View) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 Pin Description OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 V CC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 Symbol A0 to A16 CE1, CE2 WE OE Vcc GND NC Description Address input Chip enable 1, 2 input Write enable input Output enable input Power supply Ground No connection I/O1 to I/O8 Data input output CXK581000ATM (Standard Pinout) 26 25 24 23 22 21 20 19 18 17 A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CXK581000AYM (Mirror Image Pinout) A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE GND CXK581000AM CXK581000AP Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature Symbol VCC VIN VI/O PD Topr Tstg Tsolder CXK581000AP CXK581000ATM/AYM/AM (Ta = 25°C, GND = 0V) Rating –0.5 to +7.0 –0.5∗ to VCC +0.5 –0.5∗ to VCC +0.5 CXK581000AP CXK581000ATM/AYM/AM 1.0 0.7 0 to +70 –55 to +150 260 • 10 235 • 10 Unit V W °C °C • s ∗ VIN,VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE1 H × L L L CE2 × L H H H OE × × H L × WE × × H H L Mode Not selected Not selected Output disable Read Write I/O pin High Z High Z High Z Data out Data in VCC Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ×: "H" or "L" DC Recommended Operating Conditions Item Supply voltage Input high voltage Symbol VCC VIH Min. 4.5 2.2 –0.3∗ (Ta = 0 to +70°C, GND = 0V) Typ. 5.0 — — Max. 5.5 VCC +0.3 0.8 Unit V Input low voltage VIL ∗ VIL = –3.0V Min. for pulse width less than 50ns. –2– CXK581000ATM/AYM/AM/AP Electrical Characteristics • DC Characteristics Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO Test conditions VIN = GND to VCC (VCC = 5V ±10%, GND = 0V, Ta = 0 to = +70°C) Min. –1 –1 Typ.∗1 — — Max. 1 1 µA Unit CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL, VI/O = GND to VCC CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA Min. cycle Duty = 100% IOUT = 0mA Cycle time 1µs duty = 100% IOUT = 0mA CE1 ≤ 0.2V CE2 ≥ VCC – 0.2V VIL ≤ 0.2V VIH ≥ VCC – 0.2V 0 to +70°C CE2 ≤ 0.2V LL∗2 0 to +40°C +25°C 0 to +70°C SL∗3 0 to +40°C +25°C 55LL/55SL 70LL/70SL 10LL/10SL ICC1 — — — — 7 45 40 35 15 90 70 60 mA ICC2 Average operating current ICC3 — 10 20 — — — — — — — 2.4 — — — 0.7 — — 0.3 0.6 — — 20 4 2 12 2.4 1 3 — V 0.4 mA µA Standby current ISB1 or { CE2 ≥ V CE1 ≥ VCC – 0.2V CC – 0.2V ISB2 Output high voltage Output low voltage VOH VOL CE1 = VIH or CE2 = VIL IOH = –1.0mA IOL = 2.1mA ∗1 VCC = 5V, Ta = 25°C ∗2 For -55LL/70LL/10LL ∗3 For -55SL/70SL/10SL –3– CXK581000ATM/AYM/AM/AP I/O Capacitance Item Input capacitance I/O capacitance Symbol CIN CI/O Test conditions VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 7 8 Unit pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level input rise time input fall time Input and output reference level -55LL/55SL Output load conditions -70LL/70SL -10LL/10SL (VCC = 5V±10%, Ta = 0 to +70°C) Conditions VIH = 2.2V VIL = 0.8V TTL • Test circuit tr = 5ns tf = 5ns 1.5V CL∗ = 30pF, 1TTL CL∗ = 100pF, 1TTL CL ∗ CL includes scope and jig capacitances. –4– CXK581000ATM/AYM/AM/AP • Read cycle (WE = "H") -55LL/55SL Item Read cycle time Symbol Min. 55 — — — — 15 10 5 — — Max. — 55 55 55 30 — — — 25 25 -70LL/70SL Min. 70 — — — — 15 10 5 — — Max. — 70 70 70 40 — — — 25 25 -10LL/10SL Min. 100 — — — — 15 10 5 — — Max. — 100 100 100 50 — — — 35 35 ns Unit tRC tAA Address access time tCO1 Chip enable access time (CE1) tCO2 Chip enable access time (CE2) tOE Output enable to output valid tOH Output hold from address change tLZ1, tLZ2 Chip enable to output in low Z (CE1, CE2) tOLZ Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) tHZ1, tHZ2∗ tOHZ∗ Output disable to output in high Z (OE) ∗ referred to as output voltage levels. tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not • Write cycle -55LL/55SL Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z ∗ Symbol Min. 55 50 50 25 0 40 0 0 0 10 — Max. — — — — — — — — — — 25 -70LL/70SL Min. 70 60 60 30 0 50 0 0 0 10 — Max. — — — — — — — — — — 25 -10LL/10SL Min. 100 70 70 40 0 70 0 0 0 10 — Max. — — — — — — — — — — 30 ns Unit tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK581000ATM/AYM/AM/AP Timing Waveform • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE1 tCO1 tLZ1 CE2 tCO2 tLZ2 tHZ2 tHZ1 OE tOE tOLZ Data out High impedance Data valid tOHZ • Write cycle (1) : WE control tWC Address tAW OE tCW CE1 tCW CE2 tAS WE tDW Data in tWHZ Data out (∗2) High impedance (∗2) Data valid tOW tDH tWP (∗1) tWR –6– CXK581000ATM/AYM/AM/AP • Write cycle (2) : CE1 control tWC Address tAW OE tAS CE1 tCW CE2 tWP WE tDW Data in Data valid tDH tCW tWR1 (∗3) Data out High impedance • Write cycle (3) : CE2 control tWC Address tAW OE tCW CE1 tAS CE2 tWP WE tDW Data in Data valid tDH tOW CW tWR1 (∗3) Data out High impedance ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while the I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. –7– CXK581000ATM/AYM/AM/AP Data Retention Waveform • Low supply voltage data retention waveform (1) : CE1 control tCDRS VCC 4.5V 2.2V VDR CE1 GND CE1 ≥ V – 0.2V CC Data retention mode tR • Low supply voltage data retention waveform (2) : CE2 control Data retention mode VCC 4.5V CE2 VDR 0.4V GND tCDRS tR CE2 ≤ 0.2V Data Retention Characteristics Item Data retention voltage Symbol VDR ∗1 LL∗2 ICCDR1 Data retention current VCC = 3.0V∗1 SL∗3 ICCDR2 VCC = 2.0V to 5.5V∗1 Data retention setup time Recovery time LL∗2 SL∗3 0 to +70°C 0 to +40°C +25°C 0 to +70°C 0 to +40°C +25°C Test conditions Min. 2.0 — — — — — — — — 0 5 (Ta = 0 to +70°C) Typ. — — — 0.4 — — 0.15 0.7 0.3 — — Max. 5.5 12 2.4 1.2 4 0.8 0.3 20 12 — — ns ms µA Unit V tCDRS tR Chip disable to data retention mode Note) ∗1 CE1 ≥ VCC – 0.2V, CE2 ≥ VCC – 0.2V [CE1 Control] or CE2 ≤ 0.2V [CE2 Control] ∗2 For -55LL/70LL/10LL ∗3 For -55SL/70SL/10SL –8– CXK581000ATM/AYM/AM/AP Example of Representative Characteristics Supply current vs. Supply voltage 1.5 1.2 Supply current vs. Ambient temperature lCC1, ICC2 — Supply current (Relative Value) ICC1, ICC2 — Supply current (Relative Value) 1.25 1.1 ICC2 (Read) 1.0 ICC2 1.0 ICC2 (Write) ICC1 0.75 ICC1 0.9 VCC = 5.0V Ta = 25°C 0.5 4.5 5 4.75 5.25 VCC — Supply voltage (V) 5.5 0.8 0 40 20 60 Ta — Ambient temperature (°C) 80 Supply current vs. Frequency 1.0 100ns 70ns 55ns TAA, TCO1, TCO2, TOE — Access time (Relative Value) Access time vs. Load capacitance 2.0 1.8 1.6 1.4 TAA, TCO1, TCO2 TOE ICC2 — Supply current (Relative Value) Write 0.8 Read 0.6 0.4 1.2 1.0 0.8 0.6 0 100 200 300 400 CL — Load capacity (pF) VCC = 5.0V Ta = 25°C 0.2 VCC = 5.0V Ta = 25°C 0 0 4 8 12 16 20 Frequency (1/tRC, 1/tWC) (MHz) TAA, TCO1, TCO2, TOE — Access time (Relative Value) TAA, TCO1, TCO2, TOE — Access time (Relative Value) Access time vs. Supply voltage 1.4 Access time vs. Ambient temperature 1.4 1.2 TOE 1.2 TOE 1.0 TAA, TCO1, TCO2 1.0 TCO1, TCO2, TAA 0.8 Ta = 25°C 0.8 VCC = 5.0V 0.6 4.5 4.75 5 5.25 5.5 0.6 0 VCC — Supply voltage (V) 60 20 40 Ta — Ambient temperature (°C) 80 –9– CXK581000ATM/AYM/AM/AP Standby current vs. Supply voltage 2.0 20 Standby current vs. Ambient temperature ISB1 — Standby current (Relative value) ISB1, ISB2 — Standby current (Relative value) 10 5 1.5 1.0 2 1 ISB1 ISB2 0.5 Ta = 25°C 0.5 VCC = 5.0V 0 2.0 3.0 4.0 5.0 6.0 0.2 0 20 40 60 80 VCC — Supply voltage (V) Ta — Ambient temperature (°C) Input voltage level vs. Supply voltage 1.2 1.4 Standby current vs. Ambient temperature ISB2 — Standby current (Relative value) VIL, VIH — Input voltage (Relative value) 1.1 VIL, VIH 1.2 1.0 1.0 0.9 Ta = 25°C 0.8 VCC = 5.0V 0.8 4.5 5.25 5 4.75 VCC — Supply voltage (V) 5.5 0.6 0 20 40 60 Ta — Ambient temperature (°C) 80 Output high current vs. Output high voltage 1.4 Output low current vs. Output low voltage IOL — Output low current (Relative value) IOH — Output high current (Relative value) 1.8 1.2 1.4 1.0 1.0 0.8 VCC = 5.0V Ta = 25°C 0.6 VCC = 5.0V Ta = 25°C 0.6 1 3 2 4 VOH — Output high voltage (V) 5 0 0.2 0.4 0.6 0.8 VOL — Output low voltage (V) – 10 – CXK581000ATM/AYM/AM/AP Package Outline Unit: mm CXK581000ATM 32PIN TSOP (I) (PLASTIC) 8.0 ± 0.2 32 17 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 0° to 10° DETAIL A A + 0.08 0.2 – 0.03 1 0.08 M 16 0.5 + 0.05 0.02 0.127 – NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP (I) -32P-L01 TSOP (I) 032-P-0820-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY CXK581000AYM 32PIN TSOP (PLASTIC) 8.0 ± 0.2 17 32 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 A 16 + 0.08 0.2 – 0.03 1 0.08 M 0.5 0.5 ± 0.1 0.1 ± 0.1 + 0.05 0.127 – 0.02 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-32P-L01R TSOP032-P-0820-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g – 11 – 0.5 ± 0.1 0.1 ± 0.1 CXK581000ATM/AYM/AM/AP CXK581000AM 32PIN SOP (PLASTIC) 525mil + 0.4 20.5 – 0.1 32 17 0.1 + 0.3 11.2 – 0.1 14.0 ± 0.4 + 0.15 2.9 – 0.25 11.9 A 1 0.4 ± 0.1 1.27 16 + 0.1 0.15 – 0.05 0° to 10° 0.12 M DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-32P-L02 ∗SOP032-P-0525-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY CXK581000AP 32PIN DIP (PLASTIC) 600mil + 0.1 05 0.25 – 0. + 0.4 40.2 – 0.1 32 17 15.24 + 0.3 13.5 – 0.1 1 2.54 16 0.5 ± 0.1 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-32P-01 ∗DIP32-P-0600-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 4.5g – 12 – 3.0 MIN 0.5 MIN + 0.4 4.6 – 0.1 0.8 ± 0.2 0° to 15° 0.2 ± 0.1