CXK582000TM-10LL

CXK582000TM/YM/M -85LL/10LL 262144-word × 8-bit High Speed CMOS Static RAM Description The CXK582000TM/YM/M is a high speed CMOS static RAM organized as 262144-words by 8 bits. A polysilicon TFT cell technology realized extremely low stand-by current and higher data retention stability. Special feature are low power consumption and high speed and board package line-up. The CXK582000TM/YM/M is a suitable RAM for portable equipment with battery back up. Features • Fast access time (Access time) -85LL 85ns (Max.) -10LL 100ns (Max.) • Low standby current 40µA (Max.) • Low data retention current 24µA (Max.) • Single +5V supply: 4.5V to 5.5V. • Low voltage date retention : 2.0V (Min.) • Broad package line-up CXK582000TM/YM 8mm × 20mm 32 pin TSOP Package CXK582000M 525mil 32 pin SOP Package Function 262144 word x 8 bit static RAM Structure Silicon gate CMOS IC Preliminary CXK582000YM 32 pin TSOP (PIastic) For the availability of this product, please contact the sales office. CXK582000TM 32 pin TSOP (PIastic) CXK582000M 32 pin SOP (PIastic) Block Diagram A10 A11 A9 A8 A13 A15 A17 A16 A14 A12 A7 Buffer Row Decoder Memory Matrix 2048 × 1024 VCC GND A6 A5 A4 A3 A2 A1 A0 OE WE CE1 CE2 Buffer I /O Gate Column Decoder Buffer I /O Buffer I/O1 I/O8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94234-ST CXK582000TM/YM/M Pin Configuration (Top View) A11 A9 A8 A13 WE CE2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 CE2 WE A13 A8 A9 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 OE 31 A10 30 CE1 29 I/O8 28 I/O7 27 I/O6 Pin Description Symbol A17 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 32 Vcc 31 A15 30 CE2 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE1 21 I/O8 20 I/O7 19 I/O6 18 I/O5 17 I/O4 Description Address input Data input output Chip enable 1, 2 input Write enable input Output enable input Power supply Ground A0 to A17 I/O1 to I/O8 CE1, CE2 WE OE VCC GND CXK582000TM (Standard Pinout) 26 I/O5 25 I/O4 24 GND 23 I/O3 22 I/O2 21 20 19 18 17 I/O1 A0 A1 A2 A3 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 A3 18 A2 19 A1 20 A0 21 I/O1 22 I/O2 23 I/O3 24 GND 25 I/O4 26 I/O5 27 I/O6 28 I/O7 29 I/O8 30 CE1 31 A10 32 OE I/O1 13 I/O2 14 I/O3 15 GND 16 CXK582000YM (Mirror image Pinout) CXK582000M Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature · time Symbol VCC VIN VI/O PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +7.0 –0.5∗ to VCC + 0.5 –0.5∗ to VCC + 0.5 0.7 0 to +70 –55 to +150 235 · 10 Unit V V V W °C °C °C · s ∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE1 CE2 H × L L L × L H H H OE × × H L × WE × × H H L Mode Not selected Not selected Output disable Read Write I/O pin High Z High Z High Z Data out Data in VCC Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ×: “H” or “L” –2– CXK582000TM/YM/M DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min. 4.5 2.2 –0.3∗ (Ta = 0 to +70°C, GND = 0V) Typ. 5.0 — — Max. 5.5 VCC + 0.3 0.8 Unit V V V ∗ VIL = –3.0V Min. for pulse width less than 50ns. Electrical Characteristics • DC Characteristics Item Input leakage current Output leakage current Symbol ILI ILO (VCC = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) Test conditions VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA Min. cycle duty = 100% IOUT = 0mA Cycle time 1µs duty = 100% IOUT = 0mA CE1 ≤ 0.2V CE2 ≥ Vcc – 0.2V VIL ≤ 0.2V VIH ≥ Vcc – 0.2V 0 to +70°C CE2 ≤ 0.2V CE1 ≥ Vcc – 0.2V 0 to +40°C or CE2 ≥ Vcc – 0.2V +25°C -85LLX -10LLX Min. –1 –1 Typ.∗ — — Max. +1 +1 Unit µA µA Operating power supply current ICC1 — — — 7 45 40 15 80 70 mA ICC2 mA Average operating current ICC3 — 12 24 mA — — — — 2.4 — — — 1.4 0.6 — — 40 8 4 3 — 0.4 mA V V µA Standby current ISB1 { ISB2 Output high voltage Output low voltage ∗ VCC = 5V, Ta = 25°C VOH VOL CE1 = VIH or CE2 = VIL IOH = –1.0mA IOL = 1.0mA –3– CXK582000TM/YM/M I/O capacitance Item Input capacitance I/O capacitance Symbol Test conditons CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 7 8 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level Input rise time Input fall time (VCC = 5V ± 10%, Ta = 0 to +70°C) Conditions VIH = 2.2V VIL = 0.8V TTL tr = 5ns tf = 5ns 1.5V CL∗ = 100pF, 1TTL CL Input and output reference level Output load conditions ∗ CL includes scope and jig capacitances. –4– CXK582000TM/YM/M • Read cycle (WE = “H”) Item Read cycle time Symbol -85LL Min. Max. — 85 85 85 45 — — — 25 25 (Ta = 0 to +70°C) -10LL Min. 100 — — — — 15 10 5 — — Max. — 100 100 100 50 — — — 35 35 ns ns ns ns ns ns ns ns ns ns Unit tRC tAA Address access time tCO1 Chip enable access time (CE1) tCO2 Chip enable access time (CE2) tOE Output enable to output valid tOH Output hold from address change Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2 tOLZ Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) tHZ1, tHZ2∗ tOHZ∗ Output disable to output in high Z (OE) 85 — — — — 15 10 5 — — ∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z Symbol -85LL Min. Max. — — — — — — — — — — 25 (Ta = 0 to +70°C) -10LL Min. 100 70 70 45 0 70 0 5 5 10 — Max. — — — — — — — — — — 30 ns ns ns ns ns ns ns ns ns ns ns Unit tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗ 85 65 65 35 0 60 0 5 5 10 — ∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK582000TM/YM/M Timing Waveform • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE1 tCO1 ttHZ HZ1 tLZ1 CE2 tCO2 tLZ2 tHZ2 OE tOE tOLZ Data out High impedance Data valid tOHZ –6– CXK582000TM/YM/M • Write cycle (1) : WE control tWC Address tAW OE tCW CE1 tCW CE2 tAS WE tDW Data in tWHZ tOW Data out (∗2) High impedance Data valid tDH tWP (∗1) tWR (∗2) • Write cycle (2) : CE1 control tWC Address tAW OE tAS CE1 tCW CE2 tCW tWR1 (∗3) tWP WE tDW Data in Data valid tDH Data out High impedance –7– CXK582000TM/YM/M • Write cycle (3) : CE2 control tWC Address tAW OE tCW CE1 tAS CE2 tCW tWR1 (∗3) tWP WE tDW Data in Data valid tDH Data out High impedance ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. –8– CXK582000TM/YM/M Data retention waveform • Low supply voltage data retention waveform (1) (CE1 control) tCDRS VCC 4.5V 2.2V VDR CE1 GND CE1 ≥ V – 0.2V CC Data retention mode tR • Low supply voltage data retention waveform (2) (CE2 control) Data retention mode VCC 4.5V CE2 VDR 0.4V GND tCDRS tR CE2 ≤ 0.2V Data Retention Characteristics Item Data retention voltage Symbol VDR ∗ 0 to +70°C Data retention current ICCDR1 VCC = 3.0V∗1 VCC = 2.0 to 5.5V∗ Chip disable to data retention mode 0 to +40°C +25°C ICCDR2 Data retention setup time tCDRS Recovery time tR Test conditions Min. 2.0 — — — — 0 5 Typ. — — — 0.8 1.4 — — (Ta = 0 to +70°C) Max. 5.5 24 4.8 2.4 40 — — µA ns ms µA Unit V ∗ CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control) –9– CXK582000TM/YM/M Package Outline Unit: mm CXK582000TM 32PIN TSOP (I) (PLASTIC) 8.0 ± 0.2 32 17 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 0° to 10° DETAIL A A + 0.08 0.2 – 0.03 1 0.08 M 16 0.5 + 0.05 0.02 0.127 – NOTE : ∗NOT INCLUDE MOLD FINS. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-32P-L01 TSOP032-P-0820-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY CXK582000YM 32PIN TSOP (PLASTIC) 8.0 ± 0.2 17 32 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 A 16 + 0.08 0.2 – 0.03 1 0.08 M 0.5 + 0.05 0.127 – 0.02 0.1 ± 0.1 0° to 10° NOTE > Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-32P-L01R TSOP032-P-0820-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g – 10 – 0.5 ± 0.1 0.5 ± 0.1 0.1 ± 0.1 CXK582000TM/YM/M CXK582000M 32PIN SOP (PLASTIC) 525mil + 0.4 20.5 – 0.1 32 17 0.1 + 0.15 2.9 – 0.25 + 0.3 11.2 – 0.1 14.0 ± 0.4 11.9 A 1 0.4 ± 0.1 1.27 16 + 0.1 0.15 – 0.05 0° to 10° 0.12 M DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-32P-L02 ∗SOP032-P-0525-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY – 11 – 0.8 ± 0.2 0.2 ± 0.1