CXK5T16100TM-12LLX

CXK5T16100TM -12LLX 65536-word × 16-bit High Speed CMOS Static RAM Description The CXK5T16100TM is a general purpose high speed CMOS static RAM organized as 65536words by 16-bits. Special feature are low power consumption and high speed. The CXK5T16100TM is a suitable RAM for portable equipment with battery back up. Features • Extended operating temperature range: –25 to +85°C • Wide supply voltage range operation: 2.7 to 3.6V • Fast access time: (Access time) 3.0V operation 120ns (max.) 3.3V operation 100ns (max.) • Low power consumption operation: Standby / DC operation 1.6µW (typ.) / 3.3mW (typ.) 100µW (max.) / 11mW (max.) • Fully static memory ··· No clock or timing strobe required • Equal access and cycle time • Common data input and output: three state output • Directly LVTTL compatible: All inputs and outputs • Low voltage data retention: 2.0V (min.) • 400mil 44pin TSOP (type II) package Function 65536-word x 16-bit static RAM Structure Silicon gate CMOS IC Preliminary For the availability of this product, please contact the sales office. 44 pin TSOP (PIastic) Block Diagram A1 A0 A7 A6 A5 A4 A3 A2 A15 A14 GND Buffer Vcc Memory Matrix 512 × 1024 Row Decoder Memory Matrix 512 × 1024 Vcc GND CE UB LB OE WE Control I/O Gate Column Decoder Pre Decoder I/O Gate Column Decoder A13 A12 A11 A10 A9 A8 I/O Buffer I/O Buffer Buffer I/O1 I/O8 I/O9 I/O16 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– PE96405-ST CXK5T16100TM Pin Configuration (Top View) A4 1 A3 2 A2 3 A1 4 A0 5 CE 6 I/O1 7 I/O2 8 I/O3 9 I/O4 10 Vcc 11 GND 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A15 18 A14 19 A13 20 A12 21 NC 22 44 A5 43 A6 42 A7 41 OE 40 UB 39 LB 38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 GND 33 Vcc 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC Pin Description Symbol A0 to A15 I/O1 to I/O16 CE LB UB WE OE VCC GND NC Address input Data input/output Chip enable input Byte enable input (I/O1 to I/O8) Byte enable input (I/O9 to I/O16) Write enable input Output enable input Power supply Ground No connection Description Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature · time Symbol VCC VIN VI/O PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +4.6 –0.5∗1 to VCC + 0.5 –0.5∗1 to VCC + 0.5 0.7 –25 to +85 –55 to +150 235 · 10 Unit V V V W °C °C °C · s ∗1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE H OE × WE × LB × L L L H L H L L × L L H L L H × H × × H UB × L H L L H L × H I/O1 to I/O8 Not selected Read Read High-Z Write Write Not Write/Hi-Z High-Z High-Z I/O9 to I/O16 Not selected Read High-Z Read Write Not Write/Hi-Z Write High-Z High-Z Vcc Current ISB1, ISB2 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ×: “H” or “L” –2– CXK5T16100TM DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL VCC = 2.7 to 3.6V Min. 2.7 2.4 –0.3∗1 Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.4 Min. 3.0 2.0 –0.3∗1 (Ta = –25 to +85°C, GND = 0V) VCC = 3.3V ± 0.3V Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.8 V Unit ∗1 VIL=–3.0V Min. for pulse width less than 50ns. Electrical Characteristics DC and operating characteristics Item Input leakage current Output leakage current Operating power supply current Symbol ILI Test condition VIN = GND to VCC CE = VIH or UB = VIH or LB = VIH or OE = VIH or WE = VIL VI/O = GND to VCC CE = VIL VIN = VIH or VIL IOUT = 0mA Min. cycle Duty = 100% IOUT = 0mA Cycle time 1µs Duty = 100% IOUT = 0mA CE ≤ 0.2V VIL ≤ 0.2V VIH ≥ VCC – 0.2V –25 to +85°C Standby current ISB1 CE ≥ VCC – 0.2V –25 to +70°C +25°C ISB2 Output high voltage Output low voltage VOH VOL CE = VIH IOH = –2.0mA IOL = 2.0mA (VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C) Min. –1 Typ.∗2 — Max. 1 Unit µA ILO –1 — 1 µA ICC1 — 1 3 mA ICC2 Average operating current ICC3 — 35 50 mA — 10 20 mA — — — — 2.4 — — — 0.48 0.03 — — 28 14 — 0.6 — 0.4 mA V V µA ∗2 VCC = 3.3V, Ta = 25°C –3– CXK5T16100TM I/O capacitance Item Input capacitance I/O capacitance Symbol Test conditions CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 8 10 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level Input rise time Input fall time Input and output reference level Output load conditions VIH = 2.4V VIL = 0.4V (Ta = –25 to +85°C) Conditions VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V VIH = 2.2V VIL = 0.6V TTL tr = 5ns tf = 5ns tr = 5ns tf = 5ns CL 1.4V 1.4V ∗1 = 100pF, 1TTL CL∗1 = 100pF, 1TTL CL ∗1 CL includes scope and jig capacitances. –4– CXK5T16100TM • Read cycle (WE = “H”) VCC = 2.7 to 3.6V Item Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in high Z (CE) Chip disable to output in high Z (OE) Byte disable to output in high Z (UB, LB) ∗1 Symbol Min. 120 — — — — 10 10 5 5 — — — Max. — 120 120 60 60 — — — — 40 35 35 VCC = 3.3V ± 0.3V Min. 100 — — — — 10 10 5 5 — — — Max. — 100 100 50 50 — — — — 40 35 35 ns ns ns ns ns ns ns ns ns ns ns ns Unit tRC tAA tCO tBO tOE tOH tLZ tOLZ tBLZ tHZ∗1 tOHZ∗1 tBHZ∗1 tHZ, tOHZ and tBHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle VCC = 2.7 to 3.6V Item Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE, UB, LB) Output active from end of write Write to output in high Z ∗2 Symbol Min. 120 100 100 100 50 0 70 0 5 5 5 — Max. — — — — — — — — — — — 40 VCC = 3.3V ± 0.3V Min. 100 80 80 80 40 0 70 0 5 5 5 — Max. — — — — — — — — — — — 40 ns ns ns ns ns ns ns ns ns ns ns ns Unit tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage levels. –5– CXK5T16100TM Timing Waveform • Read cycle (1) : CE = OE = VIL, WE = VIH, UB and, or LB = VIL tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE tCO tLZ UB, LB tBLZ tBO tBHZ tHZ OE tOE tOLZ Data out Data valid High impedance tOHZ –6– CXK5T16100TM • Write cycle (1) : WE control tWC Address tWR tAW OE tCW CE tBW UB, LB tAS WE tDW Data in tWHZ tOW Data out (∗2) High impedance Data valid tDH tWP (∗1) (∗2) • Write cycle (2) : CE control tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data in Data valid tDH tCW ∗ tWR1 ( 3) Data out High impedance –7– CXK5T16100TM • Write cycle (3) : UB, LB control tWC Address tAW OE tCW CE tAS UB, LB tWP WE tDW Data in Data valid tDH tBW tWR1 (∗3) Data out High impedance ∗1 Write is executed when all of the CE, WE and (UB and, or LB) are at low simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 (for I/O1 to 8) is tested from either the rising edge of CE or LB, whichever comes earlier, until the end of the write cycle. tWR1 (for I/O9 to 16) is tested from either the rising edge of CE or UB, whichever comes earlier, until the end of the write cycle. –8– CXK5T16100TM Data Retention Waveform • Low supply voltage data retention waveform tCDRS VCC 2.7V 2.0V VDR CE GND Data retention mode tR CE ≥ VCC – 0.2V Data Retention Characteristics Item Data retention voltage Symbol VDR Test condition CE ≥ VCC – 0.2V –25 to +85°C Data retention current ICCDR1 VCC = 3.0V –25 to +70°C +25°C ICCDR2 Data retention setup time Recovery time VCC = 2.0 to 3.6V Chip disable to data retention mode Min. 2.0 — — — — 0 5 (Ta = –25 to +85°C) Typ. — — — 0.4 0.48∗1 — — Max. 3.6 24 12 — 28 — — µA ns ms µA Unit V tCDRS tR ∗1 VCC = 3.3V, Ta = 25°C –9– CXK5T16100TM Package Outline Unit : mm 44PIN TSOP (II) (PLASTIC) 400mil 1.2 MAX ∗18.41 ± 0.1 44 23 0.1 ∗10.16 ± 0.1 11.76 ± 0.2 A 1 0.8 B 0.3 ± 0.1 22 0.13 M + 0.05 0.125 – 0.02 + 0.1 0.1 – 0.05 0.32 ± 0.08 (0.3) 0.145 ± 0.055 (0.125) 0° to 10° DETAIL A DETAIL B NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE TSOP (II) -44P-L01 TSOP (II) 044-P-0400-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.5g – 10 – 0.5 ± 0.1