CXK5T8257BTM-12LLX

CXK5T8257BTM/BYM/BM -10LLX/12LLX 32768-word × 8-bit High Speed CMOS Static RAM Preliminary For the availability of this product, please contact the sales office. Description The CXK5T8257BTM/BYM/BM is 262,144 bits high speed CMOS static RAM organized as 32768-words by 8 bits. Special feature are low power consumption and high speed. The CXK5T8257BTM/BYM/BM is a suitable RAM for portable equipment with battery back up. Features • Extended operating temperature range: –25 to +85°C • Wide supply voltage range operation: 2.7 to 3.6V • Fast access time: (Access time) 3.0V operation -10LLX 100ns (Max.) -12LLX 120ns (Max.) 3.3V operation -10LLX 85ns (Max.) -12LLX 100ns (Max.) • Low standby current: 7.0µA (Max.) • Low power data retention: 2.0V (Min.) • Available in many packages CXK5T8257BTM/BYM 8mm × 13.4mm 28 pin TSOP Package CXK5T8257BM 450mil 28 pin SOP Package Function 32768-word × 8 bit static RAM Structure Silicon gate CMOS IC CXK5T8257BTM 28 pin TSOP (Plastic) CXK5T8257BYM 28 pin TSOP (Plastic) CXK5T8257BM 28 pin SOP (Plastic) Block Diagram A14 A13 A12 A11 A9 A8 A7 A6 A5 Buffer Row Decoder Memory Matrix 512 × 512 VCC GND A10 A4 A3 A2 A1 A0 Buffer I/O Gate Column Decoder OE Buffer WE I/O Buffer CE I/O1 I/O8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– PE96509-ST CXK5T8257BTM/BYM/BM Pin Configuration (Top View) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 7 6 5 4 3 2 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE A10 I/O1 11 I/O2 12 I/O3 13 GND 14 28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4 Pin Description Symbol A0 to A14 I/O1 to I/O8 CE WE OE VCC GND Description Address input Data input/output Chip enable input Write enable input Output enable input Power supply Ground CXK5T8257BTM (Standard Pinout) CXK5T8257BYM (Standard Pinout) CXK5T8257BM Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature · time Symbol VCC VIN VI/O PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +4.6 –0.5∗1 to VCC + 0.5 –0.5∗1 to VCC + 0.5 0.7 –25 to +85 –55 to +150 235 · 10 Unit V V V W °C °C °C · s ∗1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE H L L L OE × H L × WE × H H L Mode Not selected Output disable Read Write I/O1 to I/O8 High Z High Z Data out Data in VCC Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ×: "H" or "L" –2– CXK5T8257BTM/BYM/BM DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL VCC = 2.7 to 3.6V Min. 2.7 2.4 –0.3∗1 Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.4 Min. 3.0 2.2 –0.3∗1 (Ta = –25 to +85°C, GND = 0V) VCC = 3.3V ± 0.3V Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.6 V Unit ∗1 VIL=–3.0V Min. for pulse width less than 50ns. Electrical Characteristics • DC characteristics Item Symbol (VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C) Test Conditions VIN = GND to VCC CE = VIH OE = VIH or WE = VIL VI/O = GND to VCC CE = VIL VIN = VIH or VIL IOUT = 0mA Min. cycle duty = 100%, IOUT = 0mA CE ≥ VCC – 0.2V CE = VIH IOH = –2mA IOL = 2.0mA 10LLX 12LLX –25 to +85°C –25 to +70°C +25°C Min. –0.5 –0.5 Typ.∗2 — — Max. 0.5 0.5 µA Unit Input leakage current ILI Output leakage current ILO Operating power supply current ICC1 — — — — — — — 2.4 — 0.9 18∗3 18 — — 0.12 0.06 — — 2 mA 35∗4 35 7.0 3.5 — 0.7 — V 0.4 µA mA Average operating ICC2 current ISB1 ISB2 Output high voltage Output low voltage VOH VOL Standby current ∗2 VCC = 3.3V, Ta = 25°C ∗3 ICC2 = 21mA for 3.3V operation (VCC = 3.3V ± 0.3V) ∗4 ICC3 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V) –3– CXK5T8257BTM/BYM/BM I/O capacitance Item Input capacitance I/O capacitance Symbol Test condition CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 8 10 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level Input rise time Input fall time Input and output reference level -10LLX Output load conditions -12LLX VIH = 2.4V VIL = 0.4V (Ta = –25 to +85°C) Conditions VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V VIH = 2.2V VIL = 0.6V TTL tr = 5ns tf = 5ns tr = 5ns tf = 5ns CL 1.4V 1.4V CL∗1 = 100pF, 1TTL CL∗1 = 30pF, 1TTL CL∗1 = 100pF, 1TTL CL∗1 = 100pF, 1TTL ∗1 CL includes scope and jig capacitances. –4– CXK5T8257BTM/BYM/BM • Read cycle (WE = “H”) VCC = 2.7 to 3.6V Item Symbol -10LLX Min. Max. VCC = 3.3V ± 0.3V -10LLX Min. Max. -12LLX Min. Max. -12LLX Min. Max. Unit tRC tAA Address access time tCO Chip enable access time (CE) tOE Chip enable to output valid tOH Chip hold from address change tLZ Chip enable to output in low Z (CE) tOLZ Output enable to output in low Z (OE) tHZ∗1 Chip disable to output in high Z (CE) Output disable to output in high Z (OE) tOHZ∗1 Read cycle time ∗1 100 — — — 20 10 10 — — — 100 100 50 — — — 35 35 120 — — — 20 10 10 — — — 120 120 60 — — — 40 35 85 — — — 20 10 10 — — — 85 85 50 — — — 35 35 100 — — — 20 10 10 — — — 100 100 50 — — — 35 35 ns tHZ and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle VCC = 2.7 to 3.6V Item Symbol -10LLX Min. Max. VCC = 3.3V ± 0.3V -10LLX Min. Max. -12LLX Min. Max. -12LLX Min. Max. Unit Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE) Output active from end of write Write to output in high Z ∗2 tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗2 100 80 80 35 0 60 0 0 0 10 — — — — — — — — — — — 35 120 100 100 50 0 70 0 0 0 10 — — — — — — — — — — — 40 85 80 80 35 0 60 0 0 0 10 — — — — — — — — — — — 35 100 80 80 35 0 60 0 0 0 10 — — — — — — — — — — — 35 ns tWHZ is defined as the time requied for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK5T8257BTM/BYM/BM Timing waveform • Read cycle (1) : CE = OE =VIL, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2): WE = VIH tRC Address tAA CE tCO tHZ tLZ OE tOE tOLZ Data out High impedance Data valid tOHZ • Write cycle (1) : WE contorl tWC Address tAW OE tCW CE tAS WE tDW Data in tWHZ tOW Data out High impedance [∗2] [∗2] Data valid tDH tWP [∗1] tWR –6– CXK5T8257BTM/BYM/BM • Write cycle (2): CE control tWC Address tAW OE tAS CE tWP WE tDW Data in Data valid tDH tCW tWR1 Data out High impedance ∗1 Write is executed when both CE and WE are at low simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is output condition. –7– CXK5T8257BTM/BYM/BM Data Retention Waveform • Low supply voltage data retention waveform tCDRS VCC 2.7V 2.2V VDR CE GND CE ≥ VCC – 0.2V Data retention mode tR Data Retention Characteristics Item Data retention voltage Symbol VDR Test conditions CE ≥ VCC – 0.2V –25 to +85°C ICCDR1 Data retention current ICCDR2 Data retention setup time Recovery time VCC = 3.0V CE ≥ 2.8V –25 to +70°C +25°C VCC = 2.0 to 3.6V CE ≥ VCC – 0.2V Chip disable to data retention mode Min. 2 — — — — 0 5 (Ta = –25 to +85°C) Typ. — — — 0.1 0.12∗1 — — Max. 3.6 6 3 — 7.0 — — ns ms µA Unit V tCDRS tR ∗1 VCC = 3.3V, Ta = 25°C –8– CXK5T8257BTM/BYM/BM Package Outline Unit: mm CXK5T8257BTM 28PIN TSOP (Plastic) ∗8.0 ± 0.1 21 8 1.2 MAX 0.1 ∗11.8 ± 0.1 13.4 ± 0.3 A 22 + 0.1 0.2 – 0.05 28 1 7 0.55 ± 0.1 + 0.07 0.127 – 0.02 + 0.1 0.05 – 0.05 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-28P-L01 TSOP028-P-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.2g CXK5T8257BYM 28PIN TSOP (Plastic) ∗8.0 ± 0.1 8 21 1.2 MAX 0.1 ∗11.8 ± 0.1 13.4 ± 0.3 A 0.5 ± 0.1 7 + 0.1 0.2 – 0.05 1 28 22 0.55 ± 0.1 + 0.1 0.05 – 0.05 + 0.07 0.127 – 0.02 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-28P-L01R TSOP028-P-0000-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.2g –9– 0.5 ± 0.1 CXK5T8257BTM/BYM/BM CXK5T8257BM 28PIN SOP (PLASTIC) + 0.4 18.0 – 0.1 28 15 + 0.4 2.3 – 0.15 0.15 + 0.2 0.1 – 0.05 11.8 ± 0.4 + 0.3 8.4 – 0.1 1 14 0.4 ± 0.1 1.27 0° to 10° 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-28P-L05 ∗SOP028-P-0450 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.7g – 10 – 1.0 ± 0.2 + 0.1 0.05 0.15 –