CXK5T8512TN-12LLX

CXK5T8512TM/TN -10LLX/12LLX 65536-word × 8-bit High Speed CMOS Static RAM Description The CXK5T8512TM/TN is a high speed CMOS static RAM organized as 65536-words by 8-bits. Special feature are low power consumption and high speed. The CXK5T8512TM/TN is a suitable RAM for portable equipment with battery back up. Features • Extended operating temperature range: –25 to +85°C • Wide supply voltage range operation: 2.7 to 3.6V • Fast access time: (Access time) 3.0V operation CXK5T8512TM/TN-10LLX 100ns (Max.) CXK5T8512TM/TN-12LLX 120ns (Max.) 3.3V operation CXK5T8512TM/TN-10LLX 85ns (Max.) CXK5T8512TM/TN-12LLX 100ns (Max.) • Low standby current: 14µA (Max.) • Low data retention current: 12µA (Max.) • Low power data retention: 2.0V (Min.) • Package line-up CXK5T8512TM 8mm × 20mm 32 pin TSOP package CXK5T8512TN 8mm × 13.4mm 32 pin TSOP package Function 65536-word × 8-bit static RAM Structure Silicon gate CMOS IC Preliminary CXK5T8512TN 32 pin TSOP (Plastic) For the availability of this product, please contact the sales office. CXK5T8512TM 32 pin TSOP (Plastic) Block Diagram A15 A13 A8 A11 A9 A7 A6 A5 A14 A12 Buffer Row Decoder Memory Matrix 1024 × 512 VCC GND A4 A3 A10 A0 A2 A1 OE Buffer I/O Gate Column Decoder Buffer WE CE1 CE2 I/O Buffer I/O1 I/O8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– PE96727-PS CXK5T8512TM/TN Pin Configuration (Top View) A11 A9 A8 A13 WE CE2 A15 Vcc NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 OE 31 A10 30 CE1 29 I/O8 28 I/O7 27 I/O6 26 I/O5 Pin Description Symbol A0 to A15 I/O1 to I/O8 CE1, CE2 WE OE VCC GND NC Description Address input Data input output Chip enable 1, 2 input Write enable input Output enable input Power supply Ground No connection CXK5T8512TM (Standard Pinout) 25 I/O4 24 GND 23 I/O3 22 I/O2 21 I/O1 20 A0 19 A1 18 A2 17 A3 A11 A9 A8 A13 WE CE2 A15 Vcc NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 OE 31 A10 30 CE1 29 I/O8 28 I/O7 27 I/O6 26 I/O5 CXK5T8512TN (Standard Pinout) 25 I/O4 24 GND 23 I/O3 22 I/O2 21 I/O1 20 A0 19 A1 18 A2 17 A3 Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature · time Symbol VCC VIN VI/O PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +4.6 –0.5∗1 to VCC + 0.5 –0.5∗1 to VCC + 0.5 0.7 –25 to +85 –55 to +150 235 · 10 Unit V V V W °C °C °C · s ∗1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE1 CE2 H × L L L × L H H H OE × × H L × WE × × H H L Mode Not selected Not selected Output disable Read Write I/O pin High Z High Z High Z Data out Data in VCC Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ×: “H” or “L” –2– CXK5T8512TM/TN DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL VCC = 2.7 to 3.6V Min. 2.7 2.4 –0.3∗1 Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.4 Min. 3.0 (Ta = –25 to +85°C, GND = 0V) VCC = 3.3V ± 0.3V Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.6 V Unit 2.2 –0.3∗1 ∗1 VIL = –3.0V Min. for pulse width less than 50ns. Electrical Characteristics • DC Characteristics Item Input leakage current Output leakage current Symbol ILI ILO (VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C) Test conditions VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA Min. cycle duty = 100% IOUT = 0mA Cycle time 1µs duty = 100% IOUT = 0mA CE1 ≤ 0.2V CE2 ≥ Vcc – 0.2V VIL ≤ 0.2V VIH ≥ Vcc – 0.2V –25 to +85°C CE2 ≤ 0.2V CE1 ≥ Vcc – 0.2V –25 to +70°C or CE2 ≥ Vcc – 0.2V +25°C 10LLX 12LLX Min. –1 –1 Typ.∗1 — — Max. +1 +1 Unit µA µA Operating power supply current ICC1 — — — 1 25∗2 25 3 35∗3 35 mA ICC2 mA Average operating current ICC3 — 5 10 mA — — — — 2.4 — — — 0.24 0.12 — — 14 7 — 1.4 — 0.4 mA V V µA Standby current ISB1 { ISB2 Output high voltage Output low voltage VOH VOL CE1 = VIH or CE2 = VIL IOH = –2.0mA IOL = 2.0mA ∗1 VCC = 3.3V, Ta = 25°C ∗2 ICC2 = 30mA for 3.3V operation (VCC = 3.3V ± 0.3V) ∗3 ICC2 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V) –3– CXK5T8512TM/TN I/O capacitance Item Input capacitance I/O capacitance Symbol Test conditions CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 8 10 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level Input rise time Input fall time Input and output reference level Output load conditions -10LLX -12LLX VIH = 2.4V VIL = 0.4V (Ta = –25 to +85°C) Conditions VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V VIH = 2.2V VIL = 0.6V TTL • Test circuit tr = 5ns tf = 5ns tr = 5ns tf = 5ns CL 1.4V 1.4V CL∗1 = 100pF, 1TTL CL∗1 = 30pF, 1TTL CL∗1 = 100pF, 1TTL CL∗1 = 100pF, 1TTL ∗1 CL includes scope and jig capacitances. –4– CXK5T8512TM/TN • Read cycle (WE = “H”) VCC = 2.7 to 3.6V Item Symbol -10LLX Min. Read cycle time Address access time Chip enable access time (CE1) Chip enable access time (CE2) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE1, CE2) Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) Output disable to output in high Z (OE) Max. — 100 100 100 50 — — — 40 35 -12LLX Min. 120 — — — — 10 10 5 — — Max. — 120 120 120 60 — — — 40 35 VCC = 3.3V ± 0.3V -10LLX Min. Max. 85 — — — — 10 10 5 — — — 85 85 85 40 — — — 35 30 -12LLX Min. 100 — — — — 10 10 5 — — Max. — 100 100 100 50 — — — 40 35 ns ns ns ns ns ns ns ns ns ns Unit tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1∗1 tHZ2∗1 tOHZ∗1 100 — — — — 10 10 5 — — ∗1 tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle VCC = 2.7 to 3.6V Item Symbol -10LLX Min. Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z 100 tWC 80 tAW 80 tCW 40 tDW 0 tDH 70 tWP 0 tAS 5 tWR 5 tWR1 5 tOW tWHZ∗2 — Max. — — — — — — — — — — 40 -12LLX Min. 120 100 100 50 0 70 0 5 5 5 — Max. — — — — — — — — — — 40 VCC = 3.3V ± 0.3V -10LLX Min. Max. 85 70 70 35 0 60 0 5 5 5 — — — — — — — — — — — 35 -12LLX Min. 100 80 80 40 0 70 0 5 5 5 — Max. — — — — — — — — — — 40 ns ns ns ns ns ns ns ns ns ns ns Unit ∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK5T8512TM/TN Timing Waveform • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE1 tCO1 ttHZ HZ1 tLZ1 CE2 tCO2 tLZ2 tHZ2 OE tOE tOLZ Data out High impedance Data valid tOHZ –6– CXK5T8512TM/TN • Write cycle (1) : WE control tWC Address tAW OE tCW CE1 tCW CE2 tAS WE tDW Data in tWHZ tOW Data out (∗2) High impedance Data valid tDH tWP (∗1) tWR (∗2) • Write cycle (2) : CE1 control tWC Address tAW OE tAS CE1 tCW CE2 tCW tWR1 (∗3) tWP WE tDW Data in Data valid tDH Data out High impedance –7– CXK5T8512TM/TN • Write cycle (3) : CE2 control tWC Address tAW OE tCW CE1 tAS CE2 tCW tWR1 (∗3) tWP WE tDW Data in Data valid tDH Data out High impedance ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. –8– CXK5T8512TM/TN Data retention waveform • Low supply voltage data retention waveform (1) (CE1 contol) tCDRS VCC 2.7V VIH VDR CE1 GND CE1 ≥ VCC – 0.2V Data retention mode tR • Low supply voltage data retention waveform (2) (CE2 contol) Data retention mode VCC 2.7V CE2 VDR VIL GND CE2 ≤ 0.2V tCDRS tR Data Retention Characteristics Item Data retention voltage Symbol VDR ∗1 –25 to +85°C Data retention current ICCDR1 VCC = 3.0V∗1 VCC = 2.0 to 3.6V∗1 Chip disable to data retention mode –25 to +70°C +25°C ICCDR2 Data retention setup time tCDRS Recovery time tR Test conditions Min. 2.0 — — — — 0 5 (Ta = –25 to +85°C) Typ. — — — 0.2 0.24∗2 — — Max. 3.6 12 6 — 14 — — µA ns ms µA Unit V ∗1 CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control) ∗2 Vcc = 3.3V, Ta = 25°C –9– CXK5T8512TM/TN Package Outline Unit: mm CXK5T8512TM 32PIN TSOP (PLASTIC) 8.0 ± 0.2 32 17 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 A 1 + 0.08 0.2 – 0.03 0.08 M 16 + 0.05 0.127 – 0.02 0.5 0.1 ± 0.1 0.5 ± 0.1 0° to 10° NOTE : “∗” Dimensions do not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-32P-L01 TSOP032-P-0820 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g CXK5T8512TN 32PIN TSOP (PLASTIC) ∗8.0 ± 0.1 32 17 1.2 MAX 0.1 ∗11.8 ± 0.1 13.4 ± 0.3 A 1 16 0.145 0.2 0.08 M 0.5 + 0.1 0.05 – 0.05 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-32P-L02 TSOP032-P-0813.4-C LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g – 10 – 0.5