CXK5V8512TM-10LLX

CXK5V8512TM -85LLX/10LLX 65536-word × 8-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. Description The CXK5V8512TM is a high speed CMOS static RAM organized as 65536-words by 8-bits. A polysilicon TFT cell technology realized extremely low stand-by current and higher data retention stability. Operating on a single 3.3V supply, and special feature are low power consumption, high speed. The CXK5V8512TM is a suitable RAM for portable equipment with battery back up. Features • Extended operating temperature range: –25 to +85°C • Fast access time: (Access time) -85LLX 85ns (Max.) -10LLX 100ns (Max.) • Low standby current: 14µA (Max.) • Low data retention current: 12µA (Max.) • Single 3.3V supply: 3.3V ± 0.3V • Low voltage data retention: 2.0V (Min.) • Package 8mm × 20mm 32 pin TSOP package Function 65536-word × 8-bit static RAM Structure Silicon gate CMOS IC 32 pin TSOP (Plastic) Block Diagram A15 A13 A8 A11 A9 A7 A6 A5 A14 A12 Buffer Row Decoder Memory Matrix 1024 × 512 VCC GND A4 A3 A10 A0 A2 A1 OE Buffer I/O Gate Column Decoder Buffer WE CE1 CE2 I/O Buffer I/O1 I/O8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95716-PP CXK5V8512TM Pin Configuration (Top View) Pin Description Symbol Description Address input Data input output Chip enable 1, 2 input Write enable input Output enable input Power supply Ground No connection 32 OE 31 A10 30 CE1 29 I/O8 28 I/O7 27 I/O6 26 I/O5 A11 A9 A8 A13 WE CE2 A15 Vcc NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 to A15 I/O1 to I/O8 CE1, CE2 WE OE VCC GND NC CXK5V8512TM 25 I/O4 24 GND 23 I/O3 22 I/O2 21 I/O1 20 A0 19 A1 18 A2 17 A3 Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC VIN VI/O PD Topr Tstg (Ta = 25°C, GND = 0V) Rating –0.5 to +4.6 –0.5∗ to VCC + 0.5 –0.5∗ to VCC + 0.5 0.7 –25 to +85 –55 to +150 Unit V V V W °C °C °C • s Soldering temperature · time Tsolder 235 • 10 ∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE1 CE2 H × L L L × L H H H OE × × H L × WE × × H H L Mode Not selected Not selected Output disable Read Write I/O pin High Z High Z High Z Data out Data in VCC Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ×: “H” or “L” DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min. 3.0 2.2 –0.3∗ (Ta = –25 to +85°C, GND = 0V) Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.6 Unit V V V ∗ VIL = –3.0V Min. for pulse width less than 50ns. –2– CXK5V8512TM Electrical Characteristics • DC Characteristics Item Input leakage current Output leakage current Symbol ILI ILO (VCC = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C) Typ.∗ Test conditions Min. Max. Unit VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA Min. cycle duty = 100% IOUT = 0mA Cycle time 1µs duty = 100% IOUT = 0mA CE1 ≤ 0.2V CE2 ≥ Vcc – 0.2V VIL ≤ 0.2V VIH ≥ Vcc – 0.2V –25 to +85°C CE2 ≤ 0.2V CE1 ≥ Vcc – 0.2V –25 to +70°C or CE2 ≥ Vcc – 0.2V +25°C 85LLX 10LLX –1 –1 — — +1 +1 µA µA Operating power supply current ICC1 — — — 1 30 25 3 40 35 mA ICC2 mA Average operating current ICC3 — 5 10 mA — — — — 2.4 — — — 0.24 0.12 — — 14 7 — 1.4 — 0.4 mA V V µA Standby current ISB1 { ISB2 Output high voltage Output low voltage ∗ VCC = 3.3V, Ta = 25°C VOH VOL CE1 = VIH or CE2 = VIL IOH = –2.0mA IOL = 2.0mA –3– CXK5V8512TM I/O capacitance Item Input capacitance I/O capacitance Symbol Test conditons CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 8 10 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level Input rise time Input fall time (VCC = 3.3V ± 0.3V, Ta = –25 to +85°C) Conditions VIH = 2.2V VIL = 0.6V TTL • Test circuit tr = 5ns tf = 5ns -85LLX -10LLX 1.4V CL∗ = 30pF, 1TTL CL∗ = 100pF, 1TTL CL Input and output reference level Output load conditions ∗ CL includes scope and jig capacitances. –4– CXK5V8512TM • Read cycle (WE = “H”) Item Read cycle time (Vcc = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C) Symbol -85LLX Min. Max. — 85 85 85 40 — — — 35 30 -10LLX Min. 100 — — — — 10 10 5 — — Max. — 100 100 100 50 — — — 40 35 ns ns ns ns ns ns ns ns ns ns Unit tRC tAA Address access time tCO1 Chip enable access time (CE1) tCO2 Chip enable access time (CE2) tOE Output enable to output valid tOH Output hold from address change Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2 tOLZ Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) tHZ1∗, tHZ2∗ tOHZ∗ Output disable to output in high Z (OE) 85 — — — — 10 10 5 — — ∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z (Vcc = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C) Symbol -85LLX Min. Max. — — — — — — — — — — 35 -10LLX Min. 100 80 80 40 0 70 0 5 5 5 — Max. — — — — — — — — — — 40 ns ns ns ns ns ns ns ns ns ns ns Unit tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗ 85 70 70 35 0 60 0 5 5 5 — ∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK5V8512TM Timing Waveform • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE1 tCO1 ttHZ1 HZ tLZ1 CE2 tCO2 tLZ2 tHZ2 OE tOE tOLZ Data out Data valid High impedance tOHZ –6– CXK5V8512TM • Write cycle (1) : WE control tWC Address tAW OE tCW CE1 tCW CE2 tAS WE tDW Data in tWHZ tOW Data out (∗2) High impedance Data valid tDH tWP (∗1) tWR (∗2) • Write cycle (2) : CE1 control tWC Address tAW OE tAS CE1 tCW CE2 tCW tWR1 (∗3) tWP WE tDW Data in Data valid tDH Data out High impedance –7– CXK5V8512TM • Write cycle (3) : CE2 control tWC Address tAW OE tCW CE1 tAS CE2 tCW tWR1 (∗3) tWP WE tDW Data in Data valid tDH Data out High impedance ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. –8– CXK5V8512TM Data retention waveform • Low supply voltage data retention waveform (1) (CE1 contol) tCDRS VCC 3.0V 2.2V VDR CE1 GND CE1 ≥ VCC – 0.2V Data retention mode tR • Low supply voltage data retention waveform (2) (CE2 contol) Data retention mode VCC 3.0V CE2 VDR 0.4V GND CE2 ≤ 0.2V tCDRS tR Data Retention Characteristics Item Data retention voltage Symbol VDR ∗ –25 to +85°C Data retention current ICCDR1 VCC = 3.0V∗ –25 to +70°C +25°C ICCDR2 Data retention setup time tCDRS Recovery time tR VCC = 2.0 to 3.6V Chip disable to data retention mode Test conditions Min. 2.0 — — — — 0 5 (Ta = –25 to +85°C) Typ. — — — 0.2 0.24 — — Max. 3.6 12 6 — 14 — — µA ns ms µA Unit V ∗ CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control) –9– CXK5V8512TM Package Outline Unit: mm 32PIN TSOP (I) (PLASTIC) 8.0 ± 0.2 32 17 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 0° to 10° DETAIL A A + 0.08 0.2 – 0.03 1 0.08 M 16 0.5 + 0.05 .02 .127 – 0 0 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP (I) -32P-L01 TSOP (I) 032-P-0820-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY – 10 – 0.5 ± 0.1 0.1 ± 0.1