CXK77P36E160GB-43E

SONY® CXK77P36E160GB / CXK77P18E160GB 4/42/43/44 Preliminary 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) 8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18) Description The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored. When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a “secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently. Data read from the secondary bank is NOT parity-checked. Data read from the write buffer is NOT parity-checked. All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock). During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered. During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered. The output drivers are series terminated, and the output impedance is programmable through an external impedance matching resistor RQ. By connecting RQ between ZQ and VSS, the output impedance of all DQ pins can be precisely controlled. Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol. Features • 4 Speed Bins -4 (-4A) (-4B) -42 (-42A) (-42B) -43 (-43A) (-43B) -44 Cycle Time / Access Time 4.0ns / 3.9ns (3.8ns) (3.7ns) 4.2ns / 4.2ns (4.1ns) (4.0ns) 4.3ns / 4.5ns (4.4ns) (4.3ns) 4.4ns / 4.7ns • • • • • • • • • • • • • • Single 3.3V power supply (VDD): 3.3V ± 5% Dedicated output supply voltage (VDDQ): 1.9V typical HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.85V typical Register - Latch (R-L) read operations Late Write (LW) write operations Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2) Full read/write coherency Byte Write capability One cycle deselect Differential input clocks (K/K) Programmable impedance output drivers Sleep (power down) mode via dedicated mode pin (ZZ) JTAG boundary scan (subset of IEEE standard 1149.1) 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 1 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB 512K x 36 Pin Assignment (Top View) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 SA SA (5) SA DQc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQd SA NC (1) TMS 3 SA SA SA V SS V SS V SS SBWc V SS VREF V SS SBWd V SS V SS V SS M1 (3) SA TDI 4 NC NC VDD ZQ SS G (6) NC NC VDD K K SW SA SA VDD SA TCK 5 SA SA SA V SS V SS V SS SBWb V SS VREF V SS SBWa V SS V SS V SS M2 (4) SA TDO 6 SA SA SA DQb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQa SA NC (1) RSVD (2) Preliminary 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Notes: 1. Pad Locations 2T and 6T are true no-connects. However, they are defined as SA address inputs in x18 LW SRAMs. 2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes. 3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device. 4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied “high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions as an Error-Correcting 8Mb R-L SRAM. 5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”. 6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 2 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB 1M x 18 Pin Assignment (Top View) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC (1b) VDDQ NC (1b) DQb VDDQ NC (1b) DQb VDDQ DQb NC (1b) NC NC VDDQ 2 SA SA (5) SA NC (1b) DQb NC (1b) DQb NC (1b) VDD DQb NC (1b) DQb NC (1b) DQb SA SA TMS 3 SA SA SA V SS V SS V SS SBWb V SS VREF V SS V SS V SS V SS V SS M1 (3) SA TDI 4 NC NC VDD ZQ SS G (6) NC NC VDD K K SW SA SA VDD NC (1a) TCK 5 SA SA SA V SS V SS V SS V SS V SS VREF V SS SBWa V SS V SS V SS M2 (4) SA TDO 6 SA SA SA DQa NC (1b) DQ6a NC (1b) DQa VDD NC (1b) DQa NC (1b) DQa NC (1b) SA SA RSVD (2) Preliminary 7 VDDQ NC NC NC (1b) DQa VDDQ DQa NC (1b) VDDQ DQa NC (1b) VDDQ NC (1b) DQa NC ZZ VDDQ Notes: 1a. Pad Location 4T is a true no-connect. However, it is defined as an SA address input in x36 LW SRAMs. 1b. Pad Locations 2D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, and 6P are true no-connects. However, they are defined as DQ data inputs / outputs in x36 LW SRAMs. 2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes. 3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device. 4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied “high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions as an Error-Correcting 8Mb R-L SRAM. 5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”. 6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 3 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Pin Description Preliminary Symbol SA DQa, DQb DQc, DQd Type Input I/O Description Synchronous Address Inputs - Registered on the rising edge of K. Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations. Driven from the falling edge of K during read operations. DQa - indicates Data Byte a DQb - indicates Data Byte b DQc - indicates Data Byte c DQd - indicates Data Byte d Differential Input Clocks Synchronous Select Input - Registered on the rising edge of K. specifies a write operation when SW = 0 SS = 0 specifies a read operation when SW = 1 specifies a deselect operation SS = 1 Synchronous Global Write Enable Input - Registered on the rising edge of K. specifies a write operation when SS = 0 SW = 0 specifies a read operation when SS = 0 SW = 1 Synchronous Byte Write Enable Inputs - Registered on the rising edge of K. SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0 SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0 SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0 SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0 Asynchronous Output Enable Input - Not supported. This control pin must be tied “low”. Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode. Read Operation Protocol Select 1 - This mode pin must be tied “high” to select Register - Latch read operations. Read Operation Protocol Select 2 - This mode pin must be tied “high” or “low”. M2 = 0 selects Error-Correcting 8Mb R-L functionality M2 = 1 selects conventional 16Mb R-L functionality Output Impedance Control Resistor Input 3.3V Core Power Supply - Core supply voltage. Output Power Supply - Output buffer supply voltage. Input Reference Voltage - Input buffer threshold voltage. Ground K, K SS Input Input SW Input SBWa, SBWb, SBWc, SBWd Input G ZZ M1 M2 Input Input Input Input ZQ VDD VDDQ VREF VSS TCK TMS TDI TDO RSVD NC Input Input Input Input Output JTAG Clock JTAG Mode Select JTAG Data In JTAG Data Out Reserved - This pin is used for Sony test purposes only. It must be left unconnected. No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS. 4 / 25 March 2, 2001 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •Clock Truth Table K X L→H L→H L→H L→H L→H ZZ H L L L L L SS (tn) X H L L L L SW (tn) X X H L L L SBW x (tn) X X X L X H Operation Sleep (Power Down) Mode Deselect Read Write All Bytes Write Bytes With SBWx = L Abort Write DQ (tn) Hi - Z Hi - Z Q(tn) Hi - Z Hi - Z Hi - Z DQ (tn+1) Hi - Z X X D(tn) D(tn) X •Dynamic M2 Mode Pin State Changes Although M2 is defined as a static input (that is, it must be tied “high” or “low” at power-up), in some instance (such as during device testing) it may be desirable to change its state dynamically (that is, without first powering off the SRAM) while preserving the contents of the memory array. If so, the following criteria must be met: 1. At least two (2) consecutive deselect operations must be initiated prior to changing the state of M2, to ensure that the most recent read or write operation completes successfully. 2. At least thirty-two (32) consecutive deselect operations must be initiated after changing the state of M2 before any read or write operations can be initiated, to allow the SRAM sufficient time to recognize the change in state. •Sleep (Power Down) Mode Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time (tZZR) must be met before the SRAM can resume normal operation. •Programmable Impedance Output Drivers These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor, RQ, connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See the DC Electrical Characteristics section for further information. The output impedance is updated whenever the output drivers are in a Hi-Z state. Consequently, impedance updates will occur during write and deselect operations. At power up, 8192 clock cycles followed by an impedance update via one of the three methods described above are required to ensure that the output impedance has reached the desired value. After power up, periodic impedance updates via write or deselect operations are also required to ensure that the output impedance remains within specified tolerances. •Power-Up Sequence For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 5 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •Absolute Maximum Ratings(1) Item Supply Voltage Output Supply Voltage Input Voltage (Address, Control, Data, Clock) Input Voltage (M1, M2) Input Voltage (TCK, TMS, TDI)) Operating Temperature Junction Temperature Storage Temperature (1) Symbol VDD VDDQ VIN VMIN VTIN TA TJ TSTG Rating -0.5 to +3.8 -0.5 to +2.3 -0.5 to VDDQ + 0.5 -0.5 to VDD + 0.5 (3.8V max.) -0.5 to +3.8V 0 to 85 0 to 110 -55 to 150 Units V V V V V °C °C °C Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. •BGA Package Thermal Characteristics Item Junction to Case Temperature Symbol ΘJC Rating 1.0 Units °C/W •I/O Capacitance Item Address Input Capacitance Control Clock Output Capacitance Data Symbol CADDR CCTRL CCLK CDATA Test conditions VIN = 0V VIN = 0V VIN = 0V VOUT = 0V Min --------- (TA = 25oC, f = 1 MHz) Max 4.2 4.2 3.5 4.8 Units pF pF pF pF Note: These parameters are sampled and are not 100% tested. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 6 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary (VSS = 0V, TA = 0 to 85oC) •DC Recommended Operating Conditions Item Supply Voltage Output Supply Voltage Input Reference Voltage Input High Voltage (Address, Control, Data) Input Low Voltage (Address, Control, Data) Input High Voltage (M1, M2) Input Low Voltage (M1, M2) Clock Input Signal Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Symbol VDD VDDQ VREF VIH VIL VMIH VMIL VKIN VDIF VCM Min 3.13 1.8 0.7 VREF + 0.1 -0.3 1.3 -0.3 -0.3 0.2 0.7 Typ 3.3 1.9 0.85 --------------- Max 3.47 2.0 1.0 VDDQ + 0.3 VREF - 0.1 VDD + 0.3 0.4 VDDQ + 0.3 VDDQ + 0.6 1.3 Units V V V V V V V V V V Notes 1 2 3 1. The peak-to-peak AC component superimposed on V REF may not exceed 5% of the DC component. 2. V IH (max) AC = VDDQ + 1.0V for pulse widths less than one-quarter of the cycle time (tCYC/4). 3. V IL (min) AC = -1.0V for pulse widths less than one-quarter of the cycle time (tCYC/4). 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 7 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •DC Electrical Characteristics Item Input Leakage Current (Address, Control, Clock) Input Leakage Current (M1, M2) Input Leakage Current (Data) Average Power Supply Operating Current Power Supply Standby Current Output High Voltage Symbol ILI IMLI IDLI IDD Test Conditions VIN = V SS to VDDQ VMIN = VSS to V DD VDIN = V SS to VDDQ IOUT = 0 mA SS = VIL, ZZ = VIL IOUT = 0 mA ZZ = VIH IOH = -6.0 mA RQ = 250 Ω IOL = 6.0 mA RQ = 250 Ω VOH, VOL = VDDQ/2 RQ < 125Ω Output Driver Impedance ROUT VOH, VOL = VDDQ/2 125Ω ≤ RQ ≤ 300Ω VOH, VOL = VDDQ/2 RQ > 300Ω Min -5 -10 -10 (VDD = 3.3V ± 5%, VSS = 0V, TA = 0 to 85oC) Typ ------Max 5 10 10 Units uA uA uA Notes --- --- 750 mA 1 ISB --- --- 250 mA VOH VDDQ-0.4 --- --- V Output Low Voltage VOL --- --- 0.4 27 (25*1.1) (RQ/5)* 1.1 --- V Ω Ω Ω --(RQ/5)* 0.9 54 (60*0.9) --- 2,4 RQ/5 4 --- 3,4 1. This parameter applies to all speed bins (-4, -42, -43, and -44) in both device configurations (x18 and x36). 2. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS. 3. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied to VDDQ. 4. This parameter is guaranteed by design through extensive corner lot characterization. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 8 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •AC Electrical Characteristics -4 Parameter Symbol Min K Cycle Time K Clock High Pulse Width K Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time K Clock High to Output Valid (“A” Sub-Bin) (“B” Sub-Bin) K Clock Low to Output Valid K Clock Low to Output Hold K Clock Low to Output Low-Z K Clock High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV 4.0 1.5 1.5 0.3 0.5 0.3 0.5 0.3 0.5 0.3 0.5 --Max ----------------------3.9 3.8 3.7 1.8 ----2.2 15 --Min 4.2 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 --Max ----------------------4.2 4.1 4.0 2.0 ----2.3 15 --Min 4.3 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 --Max ----------------------4.5 4.4 4.3 2.1 ----2.4 15 --Min 4.4 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 --Max ----------------------4.7 ns ns ns ns ns ns ns ns ns ns ns ns 1 2 1 2 1 2 1 2 -42 -43 -44 Units Notes tKLQV tKLQX tKLQX1 tKHQZ tZZE tZZR --0.5 0.5 1.2 --20 --0.5 0.5 1.2 --20 --0.5 0.5 1.2 --20 --0.5 0.5 1.2 --20 2.2 ----2.5 15 --- ns ns ns ns ns ns 3 3,4 3,4 3 3 All parameters are specified over the range TA = 0 to 85oC. All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted. 1. These parameters are measured from VREF ± 200mV to the clock mid-point (“-4” bin only). 2. These parameters are measured from VREF ± 200mV to the clock mid-point. 3. These parameters are sampled and are not 100% tested. 4. These parameters are measured at ± 50mV from steady state voltage. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 9 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •AC Electrical Characteristics (Guaranteed By Design) -4 Parameter K Clock High to Output High-Z Symbol Min tKHQZ tKHQV - 2.4 Max 2.0 ns 1,2,3 Units Notes 1. This parameter is applicable when tKHQV ≤ 3.8ns. 2. This parameter is measured at the gate of the output driver of the SRAM. 3. Please refer to the previous page (p. 9) of this document for information concerning to what specification this parameter is tested. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 10 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB (VDD = 3.3V ± 5%, VDDQ = 1.9V ± 0.1V, TA = 0 to 85°C) Item Symbol VREF VCAIH VCAIL VDIH VDIL Conditions 0.85 1.45 0.35 1.25 0.55 2.0 0.85 VKIH VKIL VCM 1.45 0.75 1.10 2.0 K/K cross 0.95 Units V V V V V V/ns V V V V V/ns V V Preliminary •AC Test Conditions Notes Input Reference Voltage Address / Control Input High Level Address / Control Input Low Level Data Input High Level Data Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Common Mode Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions VDIF = 0.7V VDIF = 0.7V Fig.1 RQ = 250Ω Figure 1: AC Test Output Load 0.95 V 16.7 Ω 50 Ω 5 pF DQ 16.7 Ω 0.95 V 16.7 Ω 50 Ω 5 pF 50 Ω 50 Ω 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 11 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Timing Diagram of Read-Write-Read Operations Synchronously Controlled via SW (SS = Low) Figure 2 Preliminary Read Read Read Read Write Write Write Read Read Read Read K K tKHKL tKLKH tKHKH tAVKH tKHAX SA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SS = VIL tWVKH tKHWX SW tWVKH tKHWX SBWx tKHQV tKLQV tKLQX tKHQZ tDVKH tKHDX tKLQX1 DQ Q1 Q2 Q3 Q4 D5 D6 D7 Q8 Q9 Q10 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 12 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Timing Diagram of Read-Write-Read Operations Synchronously Controlled via SS and Deselect Operations Figure 3 Preliminary Read Read Read Deselect Write Write Write Deselect Read Read Read K K tKHKL tKLKH tKHKH tAVKH tKHAX SA A1 A2 A3 A4 A5 A6 A7 A8 A9 tSVKH tKHSX SS tWVKH tKHWX SW tWVKH tKHWX SBWx tKHQV tKLQV tKLQX tKHQZ tDVKH tKHDX tKLQX1 DQ Q1 Q2 Q3 D4 D5 D6 Q7 Q8 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 13 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Timing Diagram of Sleep (Power-Down) Mode Operation Asynchronously Controlled via ZZ Figure 4 Preliminary Read (note 1) Deselect (note 2) Deselect (note 2) (note 3) Deselect (note 4) Read (note 5) Read (note 5) Read (note 5) K K SA A1 A2 A3 A4 SS SW SBWx tZZE Begin ISB tZZR ZZ DQ Q1 Q2 Q3 Note 1: This can be ANY valid operation. The depiction of a Read operation here is provided only as an example. Note 2: Before ZZ is asserted, at least two (2) Deselect operations must be initiated after the last Read or Write operation is initiated, in order to ensure the successful completion of the last Read or Write operation. Note 3: While ZZ is asserted, all of the SRAM’s address, control, data, and clock inputs are ignored. Note 4: After ZZ is deasserted, Deselect operations must be initiated until the specified recovery time (tZZR) has been met. Read and Write operations may NOT be initiated during this time. Note 5: This can be ANY valid operation. The depiction of a Read operation here is provided only as an example. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 14 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •Test Mode Description These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers). The TAP consists of the following four signals: TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Induces (clocks) TAP Controller state transitions. Inputs commands to the TAP Controller. Sampled on the rising edge of TCK. Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK. Outputs data serially from the TAP Registers. Driven from the falling edge of TCK. Disabling the TAP When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied “high” through a pull-up resistor or left unconnected. TDO should be left unconnected. Note: Operation of the TAP does not interfere with normal SRAM operation except when the SAMPLE-Z instruction is selected (see page 20 for further information). Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device. (VDD = 3.3V ± 5%, TA = 0 to 85°C) Min 1.4 -0.3 2.6 --2.3 ---10 Max 3.6 0.8 --0.1 --0.4 10 Units V V V V V V uA JTAG DC Recommended Operating Conditions Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Output High Voltage (CMOS) JTAG Output Low Voltage (CMOS) JTAG Output High Voltage (TTL) JTAG Output Low Voltage (TTL) JTAG Input Leakage Current Symbol VTIH VTIL VTOH VTOL VTOH VTOL ITLI Test Conditions ----ITOH = -100uA ITOL = 100uA ITOH = -8.0mA ITOL = 8.0mA VTIN = 0V to 3.6V JTAG AC Test Conditions Parameter JTAG Input High Level JTAG Input Low Level JTAG Input Rise & Fall Time JTAG Input Reference Level JTAG Output Reference Level JTAG Output Load Condition Symbol VTIH VTIL Conditions 3.0 0.0 1.0 1.5 1.5 (VDD = 3.3V ± 5%, TA = 0 to 85°C) Units V V V/ns V V See Fig.1 (page 11) Notes 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 15 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary JTAG AC Electrical Characteristics Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup Time TMS Hold TIme TDI Setup Time TDI Hold TIme TCK Low to TDO Valid TCK Low to TDO Hold Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLQV tTLQX 0 Min 100 40 40 10 10 10 10 20 Max Unit ns ns ns ns ns ns ns ns ns JTAG Timing Diagram Figure 5 tTHTL tTLTH tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV tTLQX TDO 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 16 / 25 March 2, 2001 SONY® TAP Registers CXK77P36E160GB / CXK77P18E160GB Preliminary TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers”, of which there is one- the Instruction Register, and “Data Registers”, of which there are three - the ID Register, the Bypass Register, and the Boundary Scan Register. Individual TAP registers are “selected” (inserted between TDI and TDO) when the appropriate sequence of commands is given to the TAP Controller. Instruction Register (3 bits) The Instruction Register stores the instructions that are executed by the TAP Controller when the TAP Controller is in the “Run-Test / Idle” state, or in any of the various “Data Register” states. It is loaded with the IDCODE instruction at powerup, or when the TAP Controller is in the “Test-Logic Reset” state or the “Capture-IR” state. It is inserted between TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed by the TAP Controller until the TAP Controller has reached the “UpdateIR” state. The Instruction Register is 3 bits wide, and is encoded as follows: Code (2:0) 000 001 010 Instruction BYPASS IDCODE SAMPLE-Z Description Inserts the Bypass Register between TDI and TDO. Inserts the ID Register between TDI and TDO. Captures the SRAM’s I/O ring contents in the Boundary Scan Register. Inserts the Boundary Scan Register between TDI and TDO. Disables the SRAM’s data output drivers. Inserts the Bypass Register between TDI and TDO. Captures the SRAM’s I/O ring contents in the Boundary Scan Register. Inserts the Boundary Scan Register between TDI and TDO. Do not use. Reserved for manufacturer use only. Inserts the Bypass Register between TDI and TDO. Inserts the Bypass Register between TDI and TDO. 011 100 101 110 111 BYPASS SAMPLE PRIVATE BYPASS BYPASS Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. ID Register (32 bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The ID Register is 32 bits wide, and is encoded as follows: Revision Number (31:28) xxxx xxxx Part Number (27:12) 0000 0000 0100 1010 0000 0000 0100 1011 Sony ID (11:1) 0000 1110 001 0000 1110 001 Start Bit (0) 1 1 Device 512K x 36 1M x 18 Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 17 / 25 March 2, 2001 SONY® Bypass Register (1 bit) CXK77P36E160GB / CXK77P18E160GB Preliminary The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic “0” when the BYPASS instruction has been loaded in the the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. Boundary Scan Register (70 bits for x36, 51 bits for x18) The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins) plus a number of place holder locations reserved for density and/or functional upgrades. The Boundary Scan Register is loaded with the contents of the SRAM’s I/O ring when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The Boundary Scan Register contains the following bits: 512K x 36 DQ SA K, K SS, SW, SBWx G, ZZ M1, M2 ZQ Place Holder 36 19 2 6 2 2 1 2 DQ SA K, K SS, SW, SBWx G, ZZ M1, M2 ZQ Place Holder 1M x 18 18 20 2 4 2 2 1 2 For deterministic results, all signals composing the SRAM’s I/O ring must meet setup and hold times with respect to TCK (same as TDI and TMS) when sampled. K/K are connected to a differential input receiver that generates a single-ended input clock signal to the device. Therefore, in order to capture specific values for these signals in the Boundary Scan Register, these signals must be at opposite logic levels when sampled. Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected to VSS internally, regardless of pin connection externally. The Boundary Scan Order Assignment table that follows depicts the order in which the bits from the table above are arranged in the Boundary Scan Register. In the notation, Bit 1 is the LSB bit of the register. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 18 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Boundary Scan Order Assignments (By Exit Sequence) 512K x 36 1M x 18 Signal SA SA (2) Preliminary Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 28 29 30 31 32 33 34 35 Signal M2 SA SA SA SA ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa SBWa K K G SBWb DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA SA SA SA Pad 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Bit 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pad 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 28 29 30 31 32 33 34 35 Signal M2 SA SA SA SA ZZ DQa DQa DQa DQa SBWa K K G DQa DQa DQa DQa DQa SA SA SA SA SA SA SA SA (2) Pad 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 1D 2E 2G 1H Bit 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal SBWb ZQ SS NC (1) Pad 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R SA SA SA SA DQc DQc DQc DQc DQc DQc DQc DQc DQc SBWc ZQ SS NC NC (1) (1) NC (1) SW DQb DQb DQb DQb DQb SA SA SA SA M1 SW SBWd DQd DQd DQd DQd DQd DQd DQd DQd DQd SA SA SA M1 SA SA SA SA DQb DQb DQb DQb Note 1: NC pins at pad locations 4G and 4H are connected to VSS internally, regardless of pin connection externally. Note 2: SA pin at pad location 2B has a small pull-down device. Consequently, if the pin is left unconnected, a logic level “0” will be read from this location in the Boundary Scan Register. However, if the pin is NOT left unconnected, the logic level applied to the pin will be read from this location in the Boundary Scan Register. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 19 / 25 March 2, 2001 SONY® TAP Instructions IDCODE CXK77P36E160GB / CXK77P18E160GB Preliminary IDCODE is the default instruction loaded into the Instruction Register at power-up, and when the TAP Controller is in the “Test-Logic Reset” state. When the IDCODE instruction is selected, a predetermined device- and manufacturer-specific identification code is loaded into the ID Register when the TAP Controller is in the “Capture-DR” state, and the ID Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Normal SRAM operation is not disrupted when the IDCODE instruction is selected. BYPASS When the BYPASS instruction is selected, a logic “0” is loaded into the Bypass Register when the TAP Controller is in the “Capture-DR” state, and the Bypass Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Normal SRAM operation is not disrupted when the BYPASS instruction is selected. SAMPLE When the SAMPLE instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring (see the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Normal SRAM operation is not disrupted when the SAMPLE instruction is selected. SAMPLE-Z When the SAMPLE-Z instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring (see the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Additionally, when the SAMPLE-Z instruction is selected, the SRAM’s data output drivers are disabled (that is, the DQ I/O buffers are forced to an input state). Consequently, normal SRAM operation is disrupted when the SAMPLE-Z instruction is selected. Read operations initiated while the SAMPLE-Z instruction is selected will fail. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 20 / 25 March 2, 2001 SONY® TAP Controller CXK77P36E160GB / CXK77P18E160GB Preliminary The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK. The TAP Controller enters the “Test-Logic Reset” state in one of two ways: 1. At power up. 2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK. The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. TAP Controller State Diagram Figure 6 1 Test-Logic Reset 0 0 Run-Test / Idle 1 Select DR-Scan 1 Select IR-Scan 1 0 1 Capture-DR 0 1 Capture-IR 0 Shift-DR 0 0 Shift-IR 0 1 1 Exit1-DR 1 1 Exit1-IR 0 Pause-DR 0 0 Pause-IR 0 1 Exit2-DR 1 0 Exit2-IR 0 1 Update-DR 1 Update-IR 1 0 1 0 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 21 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •Ordering Information Part Number CXK77P36E160GB-4E CXK77P36E160GB-4AE CXK77P36E160GB-4BE (-4F) (-4AF) (-4BF) (-4G) (-4AG) (-4BG) (-4H) (-4AH) (-4BH) VDD Size Speed (Cycle / Access Time) 4.0ns / 3.9ns 4.0ns / 3.8ns 4.0ns / 3.7ns 4.2ns / 4.2ns 4.2ns / 4.1ns 4.2ns / 4.0ns 4.3ns / 4.5ns 4.3ns / 4.4ns 4.3ns / 4.3ns 4.4ns / 4.7ns 4.0ns / 3.9ns 4.0ns / 3.8ns 4.0ns / 3.7ns 4.2ns / 4.2ns 4.2ns / 4.1ns 4.2ns / 4.0ns 4.3ns / 4.5ns 4.3ns / 4.4ns 4.3ns / 4.3ns 4.4ns / 4.7ns 3.3V 512K x 36 CXK77P36E160GB-42E (-42F) (-42G) (-42H) CXK77P36E160GB-42AE (-42AF) (-42AG) (-42AH) CXK77P36E160GB-42BE (-42BF) (-42BG) (-42BH) CXK77P36E160GB-43E (-43F) (-43G) (-43H) CXK77P36E160GB-43AE (-43AF) (-43AG) (-43AH) CXK77P36E160GB-43BE (-43BF) (-43BG) (-43BH) CXK77P36E160GB-44E CXK77P18E160GB-4E CXK77P18E160GB-4AE CXK77P18E160GB-4BE (-44F) (-4F) (-4AF) (-4BF) (-44G) (-4G) (-4AG) (-4BG) (-44H) (-4H) (-4AH) (-4BH) 3.3V 512K x 36 3.3V 3.3V 3.3V 512K x 36 512K x 36 1M x 18 CXK77P18E160GB-42E (-42F) (-42G) (-42H) CXK77P18E160GB-42AE (-42AF) (-42AG) (-42AH) CXK77P18E160GB-42BE (-42BF) (-42BG) (-42BH) CXK77P18E160GB-43E (-43F) (-43G) (-43H) CXK77P18E160GB-43AE (-43AF) (-43AG) (-43AH) CXK77P18E160GB-43BE (-43BF) (-43BG) (-43BH) CXK77P18E160GB-44E (-44F) (-44G) (-44H) 3.3V 1M x 18 3.3V 3.3V 1M x 18 1M x 18 Note: The last character of the Part Number (“E”, “F”, “G”, or “H”) is used to distinguish between 1) the revision of the device - Rev 1.0 or Rev 1.1, and 2) the fab location used to bump the device - Fujitsu Mie (F-MIE) or Fujitsu Tohoku Electronics (FTE). “E” indicates Rev 1.0 bumped at F-MIE. “F” indicates Rev 1.0 bumped at FTE. “G” indicates Rev 1.1 bumped at F-MIE. “H” indicates Rev 1.1 bumped at FTE. Please see the BGA Package Marking diagram on page 24 for further information. Note: These devices may be manufactured at two different fab locations - Wafertech and TSMC. Please see the BGA Package Marking diagram on page 24 for information concerning how to distinguish between devices manufactured at the two facilities. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 22 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary (7x17) 119 Pin BGA Package Dimensions 14.0 13.0 x4 0.15 S A 0.20 2.5 MAX 0.6 ± 0.1 0.15 S U T R P N M L K J H G F E D C B A 12345 67 7.62 A 0.35 S B 19.0 22.0 0. 15 S B 0. 7 4C S 1.27 119 - φ0.75 ± 0.15 φ0.15 M S AB P RELIMINARY PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE BGA-119P-021 BGA119-P-1422 BORAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 1.3g 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 23 / 25 March 2, 2001 20.32 C 40 1. SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary (7x17) 119 Pin BGA Package Marking SONY CCCCCCCCCCCCCCC DDDDD BBBBBBB F F’ Description 1) C Field: 2) D Field: Part Number Code (up to 15 characters). Speed Bin Code (up to 5 characters). Includes character for Revision and Bump Fab Plant Code. e.g. D = “-4AE” indicates “-4A” speed bin, Rev 1.0, Fujitsu Mie Bump Fab. e.g. D= “-4AF” indicates “-4A” speed bin, Rev 1.0, Fujitsu Tohoku Electronics Bump Fab. e.g. D = “-4AG” indicates “-4A” speed bin, Rev 1.1, Fujitsu Mie Bump Fab. e.g. D= “-4AH” indicates “-4A” speed bin, Rev 1.1, Fujitsu Tohoku Electronics Bump Fab. 3) B Field: 4) F Field: Lot Code (up to 7 characters). Wafer Fab Plant Code (1 character). e.g. F = “W” indicates Wafertech Fab. e.g. F = “” (blank) indicates TSMC Fab (no character is used for TSMC). 5) F’ Field: Revised Control Code (1 character). Example 1: Wafertech Fab Example 2: TSMC Fab SONY CXK77P18E160GB -4AE xxxxxxx W x SONY CXK77P18E160GB -4AE xxxxxxx x 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 24 / 25 March 2, 2001 SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary •Revision History Rev. # rev 0.0 rev 0.1 Rev. date 05/19/00 07/18/00 Initial Version 1. Removed Output Enable (G ) support and associated specifications. 2. Added BGA Package Thermal Characteristics (p. 6). 1.0 °C/W Junction to Case Temperature (ΘJC) 3. Modified DC Recommended Operating Conditions (p. 7). Removed Single-Ended clock support. Removed Clock Input Cross Point Voltage (VX) specification. 0.6V to 0.7V VREF, VCM (min) 1.1V to 1.3V VCM (max) 4. Modified DC Electrical Characteristics (p. 8). Removed 3 MHz Average Power Supply Operating Current (IDD3) specification. ±1uA to ±5uA ILI (min/max) 100mA to 200mA ISB (max) 5. Modified AC Electrical Characteristics (p. 9). Added note 1 regarding Address, Write Enables, Synchronous Select, and Data Input Setup Times that states “these parameters are measured from VREF ± 200mV to the clock mid-point (“-4” bin only)”. 6. Modified AC Test Conditions (p. 11). Indicated that x18 devices are tested in both conventional 16Mb R-L mode and Error-Correcting 8Mb R-L mode, whereas x36 devices are tested in conventional 16Mb R-L mode only. 7. Added BGA Package Dimensions (p. 23). 1. Modified I/O Capacitance (p. 6). 3.5pF to 4.2pF Address (CADDR) and Control (CCTRL) 4.5pF to 4.8pF Data (CDATA) 2. Modified DC Recommended Operating Conditions (p. 7). VREF + 0.3V to 1.3V VMIH (min) VREF - 0.3V to 0.4V VMIL (max) 3. Modified DC Electrical Characteristics (p. 8). 650mA to 750mA IDD (max) 200mA to 250mA ISB (max) 4. Modified AC Electrical Characteristics (p. 9). Added note 2 regarding Address, Write Enables, Synchronous Select, and Data Input Hold Times that states “these parameters are measured from VREF ± 200mV to the clock midpoint”. 5. Modified AC Test Conditions (p. 11). Removed notes indicating that x18 devices are tested in both conventional 16Mb R-L mode and Error-Correcting 8Mb R-L mode, whereas x36 devices are tested in conventional 16Mb R-L mode only. x18 and x36 devices are tested in both modes. 6. Modified JTAG DC Recommended Operating Conditions (p. 15). 2.7V to 2.6V VTOH (min) at ITOH = -100uA 2.4V to 2.3V VTOH (min) at ITOH = -8mA 7. Added BGA Package Marking (p. 24). 1. Modified Ordering Information (p. 22). Added “F”, “G”, and “H” Part Numbers. 2. Modified BGA Package Marking (p. 24). Updated “E” and added “F”, “G”, and “H” Speed Bin Code descriptions. 1. Added “8Mb LW R-L w/ EC” to document title (p. 1). Description of Modification rev 0.2 11/03/00 rev 1.0 12/18/00 rev 1.1 03/02/01 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 25 / 25 March 2, 2001