CXL1502M

CXL1502M CMOS-CCD Signal Processor For the availability of this product, please contact the sales office. Description The CXL1502M is a CMOS-CCD signal processor designed for 8-mm video signal processing. In combination with the 8-mm video Y/C signal processing IC CXA1200Q, this IC configures a comb filter for Y/C separation in recording an image, elimination of line crawling and crosstalk in playing back. Features • Single power supply 5V • Low power consumption • Built-in peripheral circuits • Completely adjustment free • Built-in triple progression PLL circuit • For PAL signals Functions • 1H comb filter, 2H comb filter output • Dropout compensation • PLL circuit (triple progression) • Clock driver • Autobias circuit • Sync tip clamp circuit • Sample and hold circuit • Delay time matching through output (THR) Structure CMOS-CCD 30 pin SOP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.4Vp-p Typ.) • Clock frequency fCLK 4.433619 MHz • Input clock waveform sine wave Input Signal Amplitude VSIG 575 mVp-p (Max.) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E80334-PS Block Diagram VCO OUT ADJY VDD ABP PC OUT CLK VSS VSS YD CCD3 VCO IN VDD VSS 30 25 24 22 20 21 17 16 29 28 27 26 23 19 18 VCO 1/3 divider Phase comparator φ1 φ2 Output circuit, S/H circuit 2H + D D Output circuit, S/H circuit Bias circuit (B) D Output circuit, S/H circuit Bias circuit (A) Clock driver Autobias circuit (P) Autobias circuit (N) D Output circuit, S/H circuit 1 3 4 7 8 2 5 6 9 10 11 12 13 14 VSS 15 NC NC TH VSS VDD VSS ABN VGGA VGGB ADJC CCDY CCD2-C CCD1 C-CD VSS Y-YD –2– CXL1502M CXL1502M Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VSS CCDY CCD2-C ADJC CCD1 NC VDD VSS NC ABN TH VGGA VGGB C-CD VSS Y-YD VSS VDD YD ADJY VSS VCO OUT VSS VSS CLK VDD PC OUT VCO IN ABP CCD3 I/O — I I O I — — — — O O O O O — O — — O O — O — — I — O I O I Reverse phase autobias DC output THR signal output (Forward phase signal) Gate bias (A) DC output Gate bias (B) DC output 2H comb filter signal output GND 1H comb filter signal output GND 5V power supply DOC signal output (Reverse phase signal) Reverse phase CCD bias DC output GND VCO output GND GND Clock input 5V power supply Phase comparator output VCO input Forward phase autobias DC output Signal input 3 (Forward phase signal) 2k to 5k > 100k 2k to 200k > 100k (at no clamp) 4k to 40k 40 to 500 600 to 2k 40 to 500 2k to 200k 40 to 500 2k to 10k 2k to 10k 40 to 500 5V power supply GND GND Signal input 4 (Reverse phase signal) Signal input 2 (Reverse phase signal) Forward CCD bias DC output Signal input 1 (Reverse phase signal) > 100k (at no clamp) > 100k (at no clamp) 600 to 2k > 100k (at no clamp) Description Impedance (Ω) –3– Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave) See the Electrical Characteristics Test Circuit. SW conditions 1 a — — — — 50 60 a a — — — — –5.0 a a c c c c b→c ← Bias conditions∗2 (V) 9 10 11 a —— a a a a b b b b b b b b a a a a b a d c c c c c — — — — 0 3 7 deg ∗7 d b a b b b c b VID VIY VIC VIT +0.25 –0.25 –0.25 –0.25 –3.0 –2.0 –1.0 dB ∗6 d b a b b b c b VID VIY VIC VIT +0.25 –0.25 –0.25 –0.25 –7.0 –5.0 –3.0 dB ∗5 d b a b b b –3.0 c b –1.0 dB ∗4 70 VBIAS 1 VBIAS 2 VBIAS 3 VBIAS 4 Min. Typ. Max. Unit Note mA ∗3 Item 2 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b b a a a b b b a a a b b b a a a b b b a a a b b b a a a b b b a a a b b b a a a b b b a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 3 4 5 6 7 8 Symbol Test conditions∗1 Supply current IDD — GLC Low frequency gain GLY GLD 203.126kHz 500mVp-p sine wave GLT GHC High frequency gain GHY GHD 4.437525MHz 150mVp-p sine wave –4– b→c ← b→c ← b→c ← GHT fc Frequency response fY fD fT h h h h h h h h 203.126kHz ← → 4.437525MHz 150mVp-p sine wave DGC Differential gain DGY DGD 5-staircase wave∗7 DGT DPC a a a a c b a d c c c c — — — — 0 3 7 deg ∗7 CXL1502M Differential phase DPY DPD 5-staircase wave∗7 DPT SW conditions 1 2 b b — — — — –56 –52 — b b b b b b b b b a a a d a b b b a a a a a VID +0.5 — — — — b b b a a a b a — b b b a a a c a 350 mVp-p ∗9 b b a a a a d d b b a a a a a d b b a a a a b d dB b b a a a a c d ∗8 3 4 5 6 7 8 9 10 11 —b —b —b —b —b VBIAS 1 VBIAS 2 VBIAS 3 VBIAS 4 Min. Unit Note Typ. Max. Bias conditions∗2 (V) Item Symbol Test conditions∗1 SNC S/N ratio SNY SND No-signal input∗8 SNT VPC S/H pulse coupling —b VPY VPD —b No-signal input — b VPT Chroma comb depth min. gain d→e ← CCD 4.437525MHz ← → 4.441431MHz 200mVp-p sine wave a a a a b b b b c b VID +0.3 VIC –0.3 VIY –0.3 VIT –0.3 — — –24 dB ∗10 –5– f→g ← Y-comb depth min. gain a a a a b b b b b b VID +0.3 YCD 2.000011MHz ← → 1.992198MHz 200mVp-p sine wave VIY –0.3 VIC –0.3 VIT –0.3 — — –15 dB ∗11 CXL1502M Electrical Characteristics Test Circuit 9V CLK fSC (4.43619MHz) 400mVp-p sine wave 0.1µ 9V 0.1µ 1k 1µ 3.3µ 29 24 20 28 25 22 21 17 16 27 26 23 19 18 0.01µ 3.3µ 0.01µ a Oscilloscope SW10 b c d SW11 b a 30 100 1µ 1.2k 1.2k –1 a SW2 b 1µ SW6 203.126kHz 500mVp-p sine wave a b a 1M 203.126kHz 150mVp-p sine wave b –1 a SW3 VSS VSS YD VDD VSS CCD3 VCO IN PC OUT 4.441431MHz 150mVp-p sine wave d CCD2-C CCDY VDD NC TH VGGA VSS CCD1 ABN ADJC NC 2.000011MHz 150mVp-p sine wave VSS 1 2 3 3.3µ 0.01µ 1µ 1µ 1µ 1µ 7 11 4 8 10 14 12 5 6 9 13 VGGB C-CD 15 VSS e SW1 VCOOUT b a ADJY Y-YD 4.437525MHz 150mVp-p sine wave ABP CLK VDD VSS c 1M b 1µ SW7 9V 1.2k Spectrum analyzer NOTE 1) ×3 c Vector LPF scope ×3 d Noise BPF meter NOTE 2) 1.992198MHz 150mVp-p sine wave f g SW8 1M a b –6– SW9 1M 5V a b [dB] 0 –3 V2 V3 V4 –50 0 5-staircase wave –1 a SW4 9V 1.2k b 1µ 4.433619MHz 500mVp-p sine wave h –1 a SW5 b 1µ 51k 51k 51k NOTE 1) LPF frequency response NOTE 2) BPF frequency response [dB] 0 –3 51k V1 –50 6M 13.3M Frequency [Hz] 0 200 6M 13.3M Frequency [Hz] VBIAS1 VBIAS3 VBIAS2 VBIAS4 Fig. 1 CXL1502M CXL1502M Notes) ∗1 Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an equal value, as well as the phase difference to a precise 180°. Also set the clock and input signal frequency accurately. ∗2 VIC, VIY, VID and VIT are defined as follows: VIC, VIY, VID and VIT are input signal clamp levels. They clamps the Video signal sync tip level. They are the pin voltages at no-input signal for pins 3, 2, 30 and 5, respectively. VID Input (CCD3) 30 L1502 2 Input (CCDY) VIY 3 5 VIT Input (CCD2-C) VIC Input (CCD1) Testing of VIC, VIY, VID and VIT is executed with a voltmeter under the following SW conditions: Item VIC VIY VID VIT SW conditions 1 — — — — 2 b b b b 3 b b b b 4 b b b b 5 b b b b 6 a a a a 7 a a a a 8 a a a a 9 a a a a 10 — — — — 11 — — — — Test point V3 V2 V1 V4 ∗3 This is the IC supply current value during clock and signal input. ∗4 GLC, GLY, GLD and GLT are output gains of C-CD, Y-YD, YD and TH pins when a 500mVp-p, 203.126kHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively. (Example of calculation) GLC = 20 log C-CD pin output voltage [mVp-p] 500 [mVp-p] [dB] –7– CXL1502M ∗5 GHC, GHY, GHD and GHT are output gains of C-CD, Y-YD, YD and TH pins when a 150mVp-p, 4.437525MHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively. Bias at input (VBIAS1, VBIAS2, VBIAS3 and VBIAS4) is tested respectively at VID + 0.25V, VIY – 0.25V, VIC – 0.25V and VIT – 0.25V. (Example of calculation) GHC = 20 log C-CD pin output voltage [mVp-p] 150 [mVp-p] [dB] ∗6 Indicates the dissipation at 4.437525MHz in relation to 203.126kHz. From the output voltage at TH, C-CD, Y-YD and YD pins when a 150mVp-p, 203.126kHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins, and from the output voltage at TH, C-CD, Y-YD and YD pins when a 150mVp-p, 4.437525MHz sine wave is simultaneously fed to same, calculation is made according to the following formula. The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is tested at VID + 0.25V, VIY – 0.25V, VIC – 0.25V and VIT – 0.25V, respectively. (Example of calculation) fT = 20 log TH pin output voltage (4.437525MHz) [mVp-p] TH pin output voltage (203.126kHz) [mVp-p] [dB] ∗7 The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: 150mV 275mV 500mV 150mV 1H 64µs CCD3 pin input waveform (the input waveform of CCD1, CCD2-C and CCDY pins is the inverted waveform of the figure above.) ∗8 The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap mode at BPF 100kHz to 5MHz. Vn [Vrms] The signal component is determined either by testing the output voltage (the same test system as that of noise level) at input of 350mVp-p, 203.126kHz, or by performing calculation from the values of GLT, GLC, GLY and GLD in accordance with the following formula. Vs [Vp-p] (Example of VS calculation) VS-T = 0.35 × 10 GLT 20 (VS-T: TH output voltage) (Example of S/N ratio calculation) SNT = 20 log VN-T (noise component) [Vrms] [dB] VS-T (signal component) [Vp-p] –8– CXL1502M ∗9 The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input block bias for VBIAS1 is tested at VID + 0.5V and VIC – 0.25V. Test value [mVp-p] ∗10 C-CD is calculated in accordance with the following formula from the C-CD pin output voltage when a 200mVp-p, 4.437525MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and from the C-CD pin output voltage when a 200mVp-p, 4.441431MHz sine wave is simultaneously fed to same. The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is set to VID + 0.3V, VIY – 0.3V, VIC – 0.3V and VIT – 0.3V, respectively. C-CD = 20 log C-CD pin output voltage (4.437525MHz) [dB] C-CD pin output voltage (4.441431MHz) ∗11 Y-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a 200mVp-p, 2.000011MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and from the Y-YD pin output voltage when a 200mVp-p, 1.992198MHz sine wave is simultaneously fed to same. The input block bias is set to the same conditions as in testing CCD. Y-CD = 20 log Y-YD pin output voltage (1.992198MHz) [dB] Y-YD pin output voltage (2.000011MHz) fsc (4.433619MHz) sine wave CLOCK 0.3Vp-p to 1.0Vp-p (0.4Vp-p Typ.) –9– Application Circuit Composite video signal input Signal output fSC 0.4Vp-p sine wave 0.1µ 1.2k YD output (Reverse phase signal) 1µ CCD3 input (forward phase signal) 0.1µ 1µ 1k 100 30 29 24 20 25 22 21 28 27 26 23 19 18 3.3µ 0.01µ 1µ 3.3µ 0.01µ 17 16 Y-YD output 1.2k 1M 1µ CCDY input (Reverse phase signal) CXL1502M – 10 – 1 2 3 1µ 1µ 3.3µ 0.01µ 1M 1M 1M 1.8k 5V 22 7 4 8 10 5 6 9 11 12 1µ 1µ 13 14 15 1.2k 1µ C-CD output CCD2-C input (Reverse phase signal) 1µ 5V 9V 2SC403 3fsc 1.8k THR output (forward phase signal) Transistor used : 2SA1175 When using pin 22 (3 fsc output) 1.2k CCD1 input (Reverse phase signal) CXL1502M Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL1502M Low frequency gain vs. Ambient temperature –1 High frequency gain vs. Ambient temperature –2 High frequency gain [dB] –3 Low frequency gain [dB] –4 –3 –5 –4 –6 –5 0 20 40 60 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] Frequency response vs. Ambient temperature 10 Differential gain vs. Ambient temperature Frequency response [dB] 0 8 Differential gain [%] –1 6 –2 4 –3 2 0 0 20 40 60 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] Chroma comb depth min. gain vs. Ambient temperature –10 Y comb depth min. gain vs. Ambient temperature –10 Chroma comb depth min. gain [dB] –20 Y comb depth min. gain [dB] –20 –30 –30 –40 –40 –50 0 20 40 60 Ta – Ambient temperature [°C] –50 0 20 40 60 Ta – Ambient temperature [°C] – 11 – CXL1502M Low frequency gain vs. Supply voltage –1 High frequency gain vs. Supply voltage –2 High frequency gain [dB] 5.25 –3 Low frequency gain [dB] –4 –3 –5 –4 –6 –5 4.75 5.00 VDD – Supply voltage [V] 4.75 5.00 VDD – Supply voltage [V] 5.25 Frequency response vs. Supply voltage 10 Differential gain vs. Supply voltage Frequency response [dB] 0 8 Differential gain [dB] –1 6 –2 4 –3 2 4.75 5.00 VDD – Supply voltage [V] 5.25 0 4.75 5.00 VDD – Supply voltage [V] 5.25 Chroma comb depth min. gain vs. Supply voltage –10 Y comb depth min. gain vs. Supply voltage –10 Chroma comb depth min. gain [dB] –20 Y comb depth min. gain [dB] 5.00 VDD – Supply voltage [V] 5.25 –20 –30 –30 –40 –40 –50 4.75 –50 4.75 5.00 VDD – Supply voltage [V] 5.25 – 12 – CXL1502M Chroma comb response (C-CD output) 0 0 Y comb response (Y-YD output) –10 –10 Gain [dB] Gain [dB] 4.4385M –20 –20 –30 –30 –40 4.4285M 4.4335M f – Frequency [Hz] –40 1.982M 1.992M f – Frequency [Hz] 2.002M Frequency response (TH, YD output) 0 –2 Gain [dB] –4 –6 –8 10k 100k f – Frequency [Hz] 1M – 13 – CXL1502M Package Outline Unit: mm 30PIN SOP (PLASTIC) + 0.4 18.8 – 0.1 30 16 + 0.4 2.3 – 0.15 0.15 + 0.2 0.1 – 0.05 10.3 ± 0.4 + 0.3 7.6 – 0.1 9.3 ± 0.3 1 0.45 ± 0.1 15 1.27 + 0.1 0.15 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-30P-L01 LEAD TREATMENT SOP030-P-0375 LEAD MATERIAL SOLDER PLATING 42 ALLOY 0.7g EPOXY RESIN – 14 – 0.5 ± 0.2