CXL1505M

CXL1503M/1505M CMOS-CCD Signal Processor Description CXL1503M/1505M are CMOS-CCD signal processors developed for CCD camera complementary color filter array processing system. CXL1503M 1H × 4 301.5 bit CCD delay line CXL1505M 1H × 4 453.5 bit CCD delay line Features • Single power supply 5V • Low power consumption CXL1503M 100mW (Typ.) CXL1505M 150mW (Typ.) • Built-in peripheral circuits • Built-in CDS (Correlated Double Sampling) circuit Function • Clock driver • Autobias circuit (center and black) • Pedestal clamp circuit • CDS circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) Item Clock voltage Low Clock voltage High CXL1503M Clock frequency CXL1505M fCL 7.16 MHz Symbol VL VH fCL Min. 0 VDD – 1.0 4.77 Typ. Max. 1.0 VDD Unit V V MHz NTSC: 910fH/3 CCIR: 908fH/3 NTSC: 455fH CCIR: 454fH Remarks 24 pin SOP (Plastic) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89174A03-PS CXL1503M/1505M Block Diagram XDL1 XDL2 VDD VDD VSS VDD VSS 19 ABCN 21 A. B CENTER TIMING GENERATOR ABBL 3 DCAB 23 5V IN A 22 CLP DL A A. B BLACK P. D P. D PG GEN. CDS-OUTPUT CIRCUIT PG GEN. IN B 24 CLP DL B PG GEN. IN C 2 CLP DL C CDS-OUTPUT CIRCUIT PG GEN. IN D 6 CLP DL D CDS-OUTPUT CIRCUIT 9 OUT D 11 OUT C CDS-OUTPUT CIRCUIT 13 OUT B 15 OUT A 18 4 8 1 16 20 17 Pin Configuration (Top View) VSS VSS 1 IN C 2 ABBL 3 VDD 4 IS 5 IN D 6 CLP 7 VDD 8 OUT D 9 VGG 10 OUT C 11 N.C. 12 24 IN B 23 DCAB 22 IN A 21 ABCN 20 VDD 19 XDL1 18 XDL2 17 VSS 16 VSS 15 OUT A 14 CDS 13 OUT B WAVE FORM 7 5 INPUT SOURCE 12 POTENTIAL CONTROL 10 14 BIAS. Pin Description No. Symbol I/O — I O — O I I O O O — O O O I I O I I I Signal output B channel DC output for CDS Signal output A channel Clock pulse input 2 Clock pulse input 1 Autobias DC output for C signal Signal input A channel DC bias input for A and B channel Signal input B channel –2– GND Signal input C channel Autobias DC output for Y signal 5V power supply Input source DC output Signal input D channel Clamp pulse input Signal output D channel Gate bias DC output Signal output C channel — 50 to 500 500 to 5k 50 to 500 > 100k > 100k 2k to 20k > 100k (at no clamp) > 100k > 100k (at no clamp) 5k > 100k (at no clamp) > 100k 50 to 500 2k to 10k 50 to 500 > 100k (at no clamp) 2k to 20k Description Impedance (Ω) 1, 16, 17 VSS 2 3 4, 8, 20 5 6 7 9 10 11 12 13 14 15 18 19 21 22 23 24 IN C ABBL VDD IS IN D CLP OUT D VGG OUT C N.C. OUT B CDS OUT A XDL2 XDL1 ABCN IN A DCAB IN B CDS CLP N.C. VGG IS Electrical Characteristics (Ta = 25°C, VDD = 5.0V, VSS = 0V) fCL = 4.77MHz (CXL1503M) fCL = 7.16MHz (CXL1505M) Min. Typ. Max. Unit 1.0 1.2 0.3 1.2 0.3 — V1 — 2.2 0.6 2.3 0.8 20 30 2.0 4.0 4.2 3.0 3.5 3.0 35 40 V V V V V mA Item V1 V2 V3 V4 V5 A1 b a a a a a a a a a a a a a a a a b a a a b a a Symbol Bias condition SW position Test Point SW1 SW2 SW3 SW4 to 7 E1 Conditions Autobias center level ABCN Autobias black level ABBL Input source level IS CDS source level CDS Output circuit bias level VGG Supply∗1 current V6 b b a to d a CXL1503M CXL1505M IDD Insertion gain IG A, Bch → V1 Output amplitude (mVp-p) 20 log C, Dch → –4.5 –3.5 –0.5 dB Input amplitude (SIN 100kHz, 100mVp-p) V2 – 0.2V ↓ 20 log –3– V6 V6 b b a to d a ↓ (Note 1) (Note 2) (Note 3) (Note 3) V6 a b a to d a→b ← A, Bch → V1 (Note 4) C, Dch → V2 – 0.2V c b a to d a Frequency∗1 response CXL1503M fG — — 0 0 0 0 0 5 5 1 1 1 12 15 5 5 3 CXL1505M Output amplitude (SIN 1MHz, 100mVp-p) –1.8 –0.8 Output amplitude (SIN 100kHz, 100mVp-p) –1.5 –0.4 dB % % % % % CXL1503M/1505M Linearity Lin. Insertion gain difference between channels ∆G Ach → Bch ∆LAB ← Linearity difference between channels Cch → Dch ∆LCD ← Cross talk between channels CRT ∗1 Standerd values are different between CXL1503M and CXL1505M. CXL1503M/1505M Notes) 1. Linearity testing For A channel and B channel, set input bias E1 to ABCN + 0.2 [V] first, and then set it to ABCN [V] and ABCN – 0.2 [V]. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For C channel and D channel, set input bias E1 to ABBL – 0.4 [V] first, and then set it to ABBL – 0.2 [V] and ABBL [V]. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B, C and D channels is taken as Sout max. and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as Lin = Sout max – Sout min × 200 [%] Sout max + Sout min 2. Calculation of insertion gain difference As the max. insertion gain among A, B, C and D channels' is taken as Gmax and the min. as Gmin., the insertion gain difference between channels becomes: ∆G = ABS (1 – 10 ( Gmax – Gmin 20 ) ) × 100 [%] 3. Calculation of linearity difference Define A channel linearity as LA, and B channel linearity as LB. We obtain the difference ∆LAB as follows. ∆LAB =  LA – LB  [%] Similarly we obtain the linearity difference ∆LCD of C channel and D channel as follows. ∆LCD =  LC – LD  [%] 4. Crosstalk calculation We take CRTa as: A channel crosstalk value only during B channel input CRTb as: B channel crosstalk value only during A channel input CRTc as: C channel crosstalk value only during D channel input CRTd as: D channel crosstalk value only during C channel input The crosstalk value of respective channels becomes: CRTa to d = Crosstalk component × 100 [%] Each channel output value –4– CXL1503M/1505M Clock Waveform Timing ∗(140) 210ns ∗(52.5) 87.5ns 10ns 10ns 90% XDL1 50% 10% 90% 50% 10% ∗(52.5) 17.5ns 10ns 87.5ns 10ns ∗( ) is for CXL1505M. 90% XDL2 50% 10% 90% 50% 10% –5– CXL1503M/1505M Electrical Characteristics Test Circuit a SW1 a b a a a V1 1µ 16V c No signal b 100kHz, 100mVp-p sine wave 1MHz, 100mVp-p sine wave 5V 3.3k b b b SW7 SW6 SW5 SW4 V4 XDL1 XDL2 1µ 16V 17 16 15 14 13 5V 3.3k 24 23 22 21 20 19 18 a b c 5V d 3.3k SW3 ×1 LPF 1 2 3 4 5 6 7 8 9 10 11 1µ 16V 12 (NC) 1µ 16V 1µ 16V V5 ×1 5V 3.3k V6 10k 10k 10k 10k E1 V2 A1 VDD 5V V3 a SW2 b Application Circuit 5V Input B Input A VDD XDL XDL 1 2 3.3k Output A 4.7µ 16V 5V 0.1µ 0.1µ 16V 16V 24 23 22 1µ 16V 100p 21 20 19 18 17 16 15 14 1µ 16V 13 3.3k Output B 5V 1 2 0.1µ 1µ 16V 16V 3 4 5 1µ 16V 6 7 8 9 10 11 12 (NC) 0.1µ 16V 100p 4.7µ 16V Input CLP D Input VDD 1µ 16V 5V 100p 4.7µ 16V Input C VDD 3.3k Output D 3.3k Output C Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXL1503M/1505M Frequency response –2 –3 Insertion gain [dB] –4 –5 –6 –7 10k 100k Signal frequency [Hz] 1M 10M Autobias center level vs. Supply voltage 3 3 Autobias black level vs. Supply voltage ABCN – Autobias center level [V] 2 ABBL – Autobias black level [V] 5 VDD – Supply voltage [V] 5.5 2 1 4.5 1 4.5 5 VDD – Supply voltage [V] 5.5 Insertion gain vs. Supply voltage 0 10 Linearity vs. Supply voltage IG – Insertion gain [dB] –2.5 Lin – Linearity [%] 5 VDD – Supply voltage [V] 5.5 5 –5 4.5 0 4.5 5 VDD – Supply voltage [V] 5.5 –7– CXL1503M/1505M Frequency response vs. Supply voltage 0 Autobias center level vs. Ambient temperature 3 ABCN – Autobias center level [V] fG – Frequency response [dB] –1 2 –2 4.5 1 5 VDD – Supply voltage [V] 5.5 0 20 40 60 Ta – Ambient temperature [°C] Autobias black level vs. Ambient temperature 3 0 Insertion gain vs. Ambient temperature ABBL – Autobias black level [V] 2 IG – Insertion gain [dB] –2.5 1 0 20 40 Ta – Ambient temperature [°C] 60 –5 0 20 40 60 Ta – Ambient temperature [°C] Linearity vs. Ambient temperature 10 Frequency response vs. Ambient temperature 0 5 fG – Frequency response [dB] Lin – Linearity [%] –1 0 0 20 40 60 Ta – Ambient temperature [°C] –2 0 20 40 60 Ta – Ambient temperature [°C] –8– CXL1503M/1505M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 24 13 + 0.4 1.85 – 0.15 0.15 + 0.3 5.3 – 0.1 7.9 ± 0.4 + 0.2 0.1 – 0.05 0.24 M PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 SOP024-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.3g –9– 0.5 ± 0.2 1 0.45 ± 0.1 12 6.9 + 0.1 0.2 – 0.05 1.27