CXL1506N

CXL1506M/N CMOS-CCD 1H/2H Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL1506M/N is a CMOS-CCD delay line developed for video signal processing. Usage in conjunction with an external low pass filter provides 1H and 2H delay signals simultaneously (For PAL signals). Features • Single power supply (5V) • Low power consumption • Built-in peripheral circuits • Built-in tripling PLL circuit • For PAL signals • 1 input and 2 outputs (Outputs for both 1H and 2H delays) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL1506M 400 mW CXL1506N 300 mW Recommended Operating Voltage (Ta = 25°C) VDD 5 ± 0.25 CXL1506M 16 pin SOP (Plastic) CXL1506N 20 pin SSOP (Plastic) Blook Diagram CXL1506N CXL1506M V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.) • Input clock frequency fCLK 4.433619 MHz • Input clock waveform sine wave Input Signal Amplitude VSIG 575 (Max.) mVp-p (at internal clamp condition) VSS 16 AB 15 VDD 14 VCO IN 13 PC OUT 12 VSS 11 CLK 10 PLL VDD 9 VSS 20 NC 19 AB 18 VDD 17 VCO IN 16 PC OUT 15 VSS 14 NC 13 CLK 12 PLL VDD 11 Autobias circuit Driver Timing Autobias circuit Driver Timing Clamp circuit CCD (1698bits) 847bits Output circuit S/H 1bit 1698bits Output circuit S/H 1bit Bias circuit Clamp circuit CCD (1698bits) 847bits Output circuit S/H 1bit 1698bits Output circuit S/H 1bit Bias circuit 1 IN 2 VG1 3 VG2 4 OUT1 (1H) 5 VSS 6 7 8 VSS OUT2 VSS (2H) (VCO OUT) 1 NC 2 IN 3 VG1 4 VG2 5 OUT1 (1H) 6 VSS 7 OUT2 (2H) 8 NC 9 10 VSS VSS (VCO OUT) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89X22C78-PS CXL1506M/N Pin Description (CXL1506M) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Note) Symbol IN VG1 VG2 OUT1 VSS OUT2 VSS (VCO OUT) VSS VDD CLK VSS PC OUT VCO IN VDD AB VSS I/O I O I O — O (O) — — I — O I — O — Description Signal input (Non-inverted signal) Gate bias 1 DC output Gate bias 2 DC input 1H signal output (Inverted signal) GND 2H signal output (Inverted signal) GND or VCO output (3fsc) GND Power supply (5V) Clock input (fsc) GND Phase comparator output VCO input Power supply (5V) Autobias DC output GND Impedance [Ω] > 10kΩ (at no clamp) 40 to 500Ω 40 to 500Ω > 10kΩ 600 to 200kΩ Note) Description of VG2 Control of input signal clamp condition 0V … Sync tip clamp condition 5V … Center bias condition The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10k Ω ). In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is at 200mVp-p. –2– CXL1506M/N Pin Description (CXL1506N) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (Note) Symbol NC IN VG1 VG2 OUT1 VSS OUT2 NC VSS (VCO OUT) VSS VDD CLK NC VSS PC OUT VCO IN VDD AB NC VSS I/O — I O I O — O — (O) — — I — — O I — O — — GND GND Description — Signal input (Non-inverted signal) Gate bias 1 DC output Gate bias 2 DC input 1H signal output (Inverted signal) GND 2H signal output (Inverted signal) — GND or VCO output (3fsc) GND Power supply (5V) Clock input (fsc) — Impedance [Ω] > 10kΩ (at no clamp) 40 to 500Ω 40 to 500Ω > 10kΩ Phase comparator output VCO input Power supply (5V) Autobias DC output — 600 to 200kΩ Note) Description of VG2 Control of input signal clamp condition 0V … Sync tip clamp condition 5V … Center bias condition The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10k Ω ). In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is at 200mVp-p. –3– CXL1506M/N Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave) See Electrical Characteristics Test Circuit. Item Supply current Low frequency gain Frequency response Differential gain Symbol IDD GL1 GL2 fR1 fR2 DG1 DG2 DP1 DP2 SN1 SN2 CP1 CP2 Test conditions (Note 1) — 200kHz 500mVp-p sine wave SW conditions 1 a a a 234 baa bab bbb Min. 17 –2 –2 –2.7 –2.8 — — — — 52 52 — — Typ. 27 0 0 –1.7 –1.8 5 5 5 5 56 56 — — Max. 37 2 2 –0.7 –0.8 7 7 7 7 — — 350 350 Unit mA dB Note 2 3 ← 200kHz → 4.434MHz b → c a a b ← 150mVp-p sine wave b → c a b b ← 5 staircase wave d d d d e e e e bac bbc bac bbc bad bbd baa bba dB 4 % 5 Differential phase 5 staircase wave degree 5 S/N ratio No signal input dB 6 S/H pulse coupling No signal input mVp-p 7 –4– Electrical Characteristics Test Circuit (CXL1506M) CLK fSC (4.433619MHz), 400mVp-p sine wave 5V A 0.1µ 1µ a 120 1000P 0.1µ Oscilloscope 16 VSS SW4 b Spectrum analyzer Note 1) 200kHz 500mVp-p sine wave IN 1 2 3 1000P b SW2 1M a b a SW3 7 4 8 1000P 5 6 a 200kHz 150mVp-p sine wave 3.3µ 3.3µ 1000P 82k 13 9 12 15 14 10 11 AB VDD VCO PC VSS CLK VDD IN OUT Vss (VCO VG1 VG2 OUT1 VSS OUT2 OUT) VSS c LPF Vector scope –5– [dB] 0 –3 –50 0 b d BPF Note 2) Noise meter 1µ 4.434MHz 150mVp-p sine wave c SW1 5-staircase wave d e Note 1) LPF frequency response [dB] 0 –3 Note 2) BPF frequency response –50 6M 13.3M f-Frequency [Hz] 0 200 6M 13.3M f-Frequency [Hz] ∗ When using CXL1506N, change the connection terminal only. CXL1506M/N (See the block diagram and pin configuration. For NC pins, ground them.) CXL1506M/N Notes) 1) By switching SW2, input condition turns out as follows. SW2 condition a b Input condition Center bias condition (approx. 2.1V) Approx. 2.1V bias is applied internally to the input signal Sync tip and clamp conditions 2) This is the IC supply current value during clock and signal input. 3) GL is the output gain of pin OUT when a 500mVp-p, 200kHz sine wave is fed to pin IN. GL = 20 log pin OUT output voltage [mVp-p] [dB] 500 [mVp-p] 4) Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at pin OUT when a 150mVp-p, 200kHz sine wave is fed to pin IN, and from the output voltage at pin OUT when a 150mVp-p, 4.434MHz sine wave is fed to same, calculation is made according to the following formula. fR = 20 log pin OUT output voltage (4.434MHz) [mVp-p] [dB] pin OUT output voltage (200kHz) [mVp-p] 5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: 150mV 275mV 500mV 150mV 1H 64µs –6– CXL1506M/N 6) The noise level of the output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap mode at BPF 100kHz to 5MHz. (Vn [Vrms]) The signal component is determined either by testing the output voltage (the same testing system as for noise level) at the input of 350mVp-p, 200kHz, or by utilizing values from GL to calculate according to the following formula. (Vs [Vp-p]) (Example of Vs calculation) GL 20 Vs = 0.35 × 10 (Example of SN ratio calculation) SN = 20 log Vn (noise component) [Vrms] [dB] Vs (signal component) [Vp-p] 7) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Test value [mVp-p] Clock 400mVp-p (typ.) fsc (4.433619MHz) sine wave –7– Application Circuit (CXL1506M) 5V Note) When VCO OUT is required, use the circuit below. 5V 0.1µ 0.1µ 1000P 2SC403 3.3µ 3.3µ 1000P CLK fSC (4.433619MHz), 400mVp-p sine wave ∗ When using CXL1506N, change the connection terminal only. (See the block diagram and pin configuration. For NC pins, ground them.) 1µ 120 82k 3fsc OUT 1.8k 9 7 1.8k 16 11 15 10 14 13 12 CXL1506M 1 2 3 1000P 330k 62P 0.1µ V1 LPF 560k (Inverted signal) Transistor used PNP: 2SA1175 1k Delay time 230ns 470 100 7 4 8 5 6 1µ 1000P 2.2k 5V –8– 330k 470 62P 0.1µ LPF 560k 1k 2.2k 100 2.2k Transistor used PNP: 2SA1175 Delay time 210ns 1M Signal input (Non-inverted signal) 2H Output 2.2k 2.2k Transistor used NPN: 2SC403 (Non-inverted signal) Note) When using Pin 7(VCO OUT), use the circuit as shown below. When not using it, GND. 5V (Inverted signal) 1H Output 2.2k (Non-inverted signal) Transistor used NPN: 2SC403 CXL1506M/N Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL1506M/N Example of Representative Characteristics Supply current vs. Ambient temperature 35 Low frequency gain (1H) vs. Ambient temperature 2 Low frequency gain 1H [dB] 0 20 40 60 80 1 Supply current [mA] 25 0 –1 15 –20 –2 –20 0 20 40 60 80 Ambient temperature [°C] Ambient temperature [°C] Low frequency gain (2H) vs. Ambient temperature 2 Frequency response (1H) vs. Ambient temperature 0 1 Frequency response 1H [dB] 0 20 40 60 80 Low frequency gain 2H [dB] –1 0 –2 –1 –2 –20 –3 –20 0 Ambient temperature [°C] 20 40 60 Ambient temperature [°C] 80 Frequency response (2H) vs. Ambient temperature 0 Differential gain (1H) vs. Ambient temperature 10 Frequency response 2H [dB] 8 –1 Differential gain 1H [%] 6 4 –2 2 –3 –20 0 20 40 60 Ambient temperature [°C] 80 0 –20 0 20 40 60 80 Ambient temperature [°C] –9– CXL1506M/N Differential gain (2H) vs. Ambient temperature 10 35 Supply current vs. Supply voltage 8 Differential gain 2H [%] 6 Supply current [mA] 0 20 40 60 80 25 4 2 0 –20 15 4.75 5 Supply voltage [V] 5.25 Ambient temperature [°C] Low frequency gain (1H) vs. Supply voltage 2 Low frequency gain (2H) vs. Supply voltage 2 Low frequency gain 1H [dB] 1 Low frequency gain 2H [dB] 5 Supply voltage [V] 5.25 1 0 0 –1 –1 –2 4.75 –2 4.75 5 Supply voltage [V] 5.25 Frequency response (1H) vs. Supply voltage 0 Frequency response (2H) vs. Supply voltage 0 Frequency response 1H [dB] Frequency response 2H [dB] 5 Supply voltage [V] 5.25 –1 –1 –2 –2 –3 4.75 –3 4.75 5 Supply voltage [V] 5.25 – 10 – CXL1506M/N Differential gain (1H) vs. Supply voltage 10 10 Differential gain (2H) vs. Supply voltage 8 8 Differential gain 1H [%] 6 Differential gain 2H [%] 5 Supply voltage [V] 5.25 6 4 4 2 2 0 4.75 0 4.75 5 Supply voltage [V] 5.25 Frequency response (1H) 2 0 Gain [dB] –2 –4 –6 10K 100K Frequency [Hz] 1M 10M Frequency response (2H) 2 0 Gain [dB] –2 –4 –6 10K 100K Frequency [Hz] 1M 10M Note) 1H and 2H shown in brackets indicate 1H and 2H outputs. – 11 – CXL1506M/N Package Outline Unit: mm CXL1506M + 0.4 9.9 – 0.1 16PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 16 9 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-16P-L01 SOP016-P-0300 LEAD MATERIAL COPPER ALLOY 0.2g LEAD TREATMENT EPOXY RESIN SOLDER PLATING CXL1506N ∗6.5 ± 0.1 20PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 0.1 20 11 A ∗4.4 ± 0.1 1 10 0.65 + 0.05 0.15 – 0.02 + 0.1 0.22 – 0.05 0.13 M 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L01 SSOP020-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g – 12 – 0.5 ± 0.2 6.4 ± 0.2 0.5 ± 0.2 1 8 6.9