CXL1517

CXL1517N/1518N CMOS-CCD Signal Processor Description The CXL1517N/1518N are CMOS-CCD signal processors developed for CCD camera complementary color filter array processing system. CXL1517N 452.5-bit × 2, 453.5-bit 1H CCD delay line CXL1518N 300.5-bit × 2, 301.5-bit 1H CCD delay line Features • Single 5V power supply • Low power consumption (Typ.) CXL1517N 120mW CXL1518N 75mW • Built-in peripheral circuits • Built-in CDS (Correlated Double Sampling) circuit Functions • Clock driver • Autobias circuit (Center and black) • Pedestal clamp circuit • CDS circuit • Overflow prevention circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 • Operating temperature Topr –10 to +65 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD 350 Recommended Operating Voltage Range (Ta = 25°C) Supply voltage VDD 4.6 to 5.25 24 pin SSOP (Plastic) Structure CMOS-CCD V °C °C mW (SSOP package) V Item Clock voltage Low Clock voltage High Clock frequency CXL1517N CXL1518N Symbol VL VH fCL fCL Min. VSS 0.7 × VDD Typ. Max. 0.3 × VDD VDD Unit V V MHz MHz Remarks 7.16 4.77 NTSC: 455fH CCIR: 454fH NTSC: 910fH/3 CCIR: 908fH/3 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E91778A78-PS CXL1517N/1518N Block Diagram and Pin Configuration (Top View) XDL1 XDL2 VDD VDD VDD VSS 19 18 5 VSS 8 20 1 VSS 16 2 17 TIMING GENERATOR ABBL 4 A.B. BLACK A.B. CENTER DRIVER PRECHARGE DRAIN PG. GEN. IN-A 23 CLP (n bit) DL A PG. GEN. IN-B 3 CLP (n bit) DL B PG. GEN. IN-C 6 CLP (n + 1 bit) DL C CDS OUTPUT CIRCUIT 9 OUT-C CDS OUTPUT CIRCUIT 11 OUT-B CDS OUTPUT CIRCUIT 14 OUT-A ABCN 21 CLP PULSE GEN. OVERFLOW PREVENTION CIRCUIT 22 POTENTIAL CONTROL CDS 7 10 15 ABOVF VSS 1 VSS 2 IN-B 3 ABBL 4 VDD 5 IN-C 6 CLP 7 VDD 8 OUT-C 9 VGG 10 OUT-B 11 NC 12 24 NC 23 IN-A 22 ABOVF 21 ABCN 20 VDD 19 XDL1 18 XDL2 17 VSS 16 VSS 15 CDS 14 OUT-A 13 NC –2– CDS CLP VGG VSS CXL1517N/1518N Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS VSS IN-B ABBL VDD IN-C CLP VDD OUT-C VGG OUT-B NC NC OUT-A CDS VSS VSS XDL2 XDL1 VDD ABCN ABOVF IN-A NC I/O — — I O — I I — O O O — — O O — — I I — O O I — GND Signal input B channel (Y) Autobias DC output for Y signal Power supply Signal input C channel (Y) Clamp pulse input Power supply Signal output C channel Output circuit bias DC output Signal output B channel — — Signal output A channel DC output for CDS GND GND Clock pulse input 2 Clock pulse input 1 Power supply Autobias DC output for C signal Autobias DC output for overflow prevention circuit Signal input A channel (C) — Center level bias at no clamp > 100k Output circuit Timing > 100k > 100k Timing Black level bias Analog Black level bias at no clamp > 100k > 100k Output circuit Analog Description Comment –3– Electrical Characteristics Ta = 25°C, VDD = 5.0V, VSS = 0V SW conditions Ratings Conditions Min. Typ. Max. 4.2 3.9 2.6 1.2 0.3 V1 — — V6 20 log fCL = 7.16MHz (CXL1517N) fCL = 4.77MHz (CXL1518N) Bias conditions E1 4.6 4.3 3.0 2.3 0.8 24 15 –4.5 –3.5 Item SW4 SW1 SW2 SW3 to 6 a a a a a b a a a a a a a a a b a a b a a b a a Test Symbol point V1 V2 V3 V4 V5 A1 4.8 4.5 3.3 3.5 3.0 35 25 — — — 0 5 12 Unit Autobias center level ABCN V V V V V mA Autobias black level ABBL Overflow prevention circuit Autobias level ABOVF CDS source level CDS Output circuit bias level VGG Current ∗ supply b b a A → V1 B, C → V2 + 0.25V ↓ 20 log CXL1517N IDD CXL1518N Output amplitude (mVp-p) Input amplitude (SIN 100kHz, 100mVp-p) –4– V6 b a b ↑ ↓ c b b a Note 1) V6 a to c a to c a to c Note 2) Note 3) V6 b b a to c a ↑ ↓ b A → V1 B, C → V2 + 0.25V Note 4) Insertion gain IG dB Frequency ∗ response CXL1517N fG CXL1518N Output amplitude (SIN 1MHz, 100mVp-p) –1.5 –0.4 Output amplitude (SIN 100kHz, 100mVp-p) –1.8 –0.8 dB Linearity Lin. % The insertion gain difference ∆G between channels 0 0 5 1 12 5 % % Linearity difference between channels Bch ∆LBC → Cch Cross-talk between channels CRT 0 1 3 % CXL1517N/1518N ∗ Standard values are different between CXL1517N and CXL1518N. CXL1517N/1518N Notes) 1) Linearity testing For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as: Lin. = Sout max – Sout min × 200 [%] Sout max + Sout min 2) Calculation of insertion gain difference As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin, the insertion gain difference between channels ∆G as: ∆G = | 1 – 10 – ( Gmax20 Gmin ) | × 100 [%] 3) Calculation of linearity difference Define B channel linearity as LB and C channel linearily as LC we obtain the difference ∆LBC as: ∆LBC = | LB – LC | [%] 4) Cross-talk calculation CRTa : The cross-talk value of A channel when B and C channels are input : The output value of A channel when A channel is input OUTA-a SW3-a, SW4-a, SW5, 6-b OUTA-bc : The output value of A channel when B and C channels are input (Cross-talk component) SW3-a, SW4-b, SW5, 6-a CRTa = OUTA-bc OUTA-a × 100 [%] Clock Waveform Timing (140) ∗ 210ns (52.5) ∗ 87.5ns 10ns 10ns 90% XDL1 50% 10% 90% 50% 10% 17.5ns 10ns (52.5) ∗ 87.5ns 10ns 90% XDL2 50% 10% 90% 50% 10% –5– ∗ The value in brackets is for CXL1517N. CXL1517N/1518N Electrical Characteristics Test Circuit a SW1 a b a a V3 V1 XDL XDL 1 2 V4 1µ 16V VDD 3.3k c No signal (GND) b 100kHz, 100mVp-p sine wave 1MHz, 100mVp-p sine wave b b SW6 SW5 SW4 1µ 1µ 16V 16V (NC) 24 23 22 21 20 19 18 17 16 15 14 (NC) 13 a b VDD c 3.3k SW3 ×1 L.P.F 1 2 3 4 5 6 7 8 9 10 11 1µ 16V 12 (NC) 1µ 16V V5 ×1 VDD 3.3k V6 10k 10k 10k E1 V2 A1 VDD a SW2 b Application Circuit XDL XDL VDD 1 2 4.7µ 16V Input A 0.1µ 16V (NC) 24 VDD 1µ 16V (NC) 3.3k Output A 1µ 1µ 16V 16V 23 22 100p 20 19 18 17 16 15 14 21 13 VDD 1 2 3 1µ 16V 0.1µ 16V Input B 4 5 6 7 8 9 10 11 1µ 16V VDD 3.3k Output C 12 (NC) 3.3k Output B 100p 100p 0.1µ 4.7µ 16V 4.7µ 16V 16V VDD Input CLP VDD C input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXL1517N/1518N Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 0.1 13 24 A 1 + 0.1 0.22 – 0.05 12 + 0.05 0.15 – 0.02 0.65 0.1 ± 0.1 0.13 M ∗5.6 ± 0.1 0° to 10° NOTE: Dimensions “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-24P-L01 SSOP024-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g –7– 0.5 ± 0.2 7.6 ± 0.2