CXL5003

CXL5003M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5003M/P are general-purpose CMOS-CCD delay line ICs that provide 1H delay time for PAL. Features • Low power consumption 110mW (Typ.) • Small size package (8-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal amplitude 180 IRE (= 1.28Vp-p, Max.) • Low input clock amplitude operation 150mVp-p (Min.) • Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions • 848-bit CCD register • Clock drivers • Autobias circuit • Sync tip clamp circuit • Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 11 V • Supply voltage VCL 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5003M 350 mW CXL5003P 480 mW Recommended Operating Conditions Supply voltage VDD 9 ± 5% V VCL 5 ± 5% V Recommended Clock Conditions • Input clock amplitude VCLK 150mVp-p to 1.0Vp-p (250mVp-p typ.) • Clock frequency fCLK 13.300856MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5003M 8 pin SOP (Plastic) CXL5003P 8 pin DIP (Plastic) –1– E51215B79-PS CXL5003M/P Blook Diagram AUTO FEED OUT 5 ref. (1 BIT) CLAMP CIRCUIT 848-BIT SHIFT REGISTER AMP S/H AMP AMP φ1 φ2 DUTY CONTROL CIRCUIT 4 IN 8 7 6 AUTO BIAS CIRCUIT φ1 φ2 CLOCK DRIVERS 1 2 3 VSS VCL Pin Description Pin No. Symbol 1 2 3 4 VSS VCL CLK VDD Description GND 5V power supply Clock input 9V power supply > 100k Impedance [Ω] Pin No. Symbol 5 6 7 8 OUT FEED Description Signal output Impedance [Ω] 600 to 1k CLK Feedback DC output > 100k 10k > 100k AUTO Autobias DC output IN Signal input –2– VDD CXL5003M/P Electrical Characteristics (Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 13.3MHz, VCLK = 250mVp-p sine wave, See "Electrical characteristics test circuit") Item Symbol IDD ICL Measuring condition 250kHz, 1.28Vp-p, sine wave input 250kHz, 1.28Vp-p, sine wave input IG = 20 log (Output voltage [Vp-p] / 1.28 [Vp-p]) Dissipation at 4.43MHz in relation to 250kHz fG = 20 log (V4.43MHz/ V250kHz) (Note 1) 5-staircase wave input Y = 140 IRE (= 1.0Vp-p) Measure S point with vector scope (Note 2) SW conditions Measuring point 1 2 a a A1 A2 Min. — — Typ. Max. Unit 4 14 5 16 mA mA Supply current Insertion gain IG a a V1 –3 0 3 dB Frequency response fG b, c b V1 –3.0 –2.1 — dB Differential gain DG — e a S — — — — — 3 3 — 5 5 % deg Differential phase DP Allowable input amplitude VIN-AC 1.28 Vp-p Noise S/N S: Input = 250kHz, 1.0Vp-p output (Vp-p) N: Input = DC ground output (mVrms) f a V2 55 60 — dB d d a a V2 V3 V4 V5 V6 3.5 3.5 1.3 1.7 5.0 5.0 2.3 2.7 6.5 6.5 3.3 3.7 V V V V VIN-AC Output DC voltage VAUTO-DC VFEED-DC 250kHz, 1.28Vp-p, VOUT-DC sine wave input a a –3– Electrical Characteristics Test Circuit V4 SW1 0.01µF 0.1µF LPF Note 3) SW2 8 7 6 5 V1 V6 BPF Note 4) V2 0.1µF 5.1k V5 9V S Vector scope a. 250kHz, 1.28Vp-p sine wave b. 250kHz, 300mVp-p sine wave c. 4.43MHz, 300mVp-p sine wave d. Ground f. CXL5003M/P 250kHz, 1.0Vp-p sine wave 1MΩ 100k VSS VCL 1 2 3 4 A2 5V CLK A1 9V 0.01µF –4– VDD VBIAS AUTO CLK fCLK = 13.3MHz VCLK = 250mVp-p sine wave FEED OUT e. V3 5-staircase wave IN a b CXL5003M/P CXL5003M/P Note 1) Frequency response measuring condition V4.43MHz (Output signal voltage [Vp-p] at 4.43MHz input) V250kHz (Output signal voltage [Vp-p] at 250kHz input) Set Pin 8 (IN) voltage [V] = VIN-DC + 640mV. [V] 4.43MHz, 300mVp-p sine wave 250kHz, 300mVp-p sine wave 640mV (adjust with VBIAS) VIN-DC Note 2) Differential gain and differential phase measuring condition 5-staircase wave signal Chroma 40 IRE 140 IRE (1.0Vp-p) 40 IRE 1H 64.0µs DG and DP are measured at output S point by vector scope. Note 3) LPF frequency response (Delay time [dB] 0 –3 170ns) Note 4) BPF frequency response [dB] 0 –3 –50 0 5.8 13.3 Frequency [MHz] –50 0 50 200 5.1M 13.3M Frequency [Hz] –5– CXL5003M/P Application Circuit 9V 5.1k 0.01µF 0.1µF Composite video signal input 8 1MΩ 7 6 5 2SA1175 CXL5003M/P 0.1µF L. P. F Delay time 1H delay signal output 170ns 1 0.01µF 47µF 0.01µF 47µF 2 3 4 0.01µF fCLK = 13.3MHz CLK VCLK = 250mVp-p sine wave 5V 9V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Frequency response vs. Ambient temperature 0 Input = 300mVp-p 4.43MHz, sine wave 0 Frequency response vs. Supply voltage Input = 300mVp-p 4.43MHz, sine wave fG – Frequency response [dB] fG – Frequency response [dB] 0 20 40 60 Ta – Ambient temperature [°C] –1 –1 –2 –2 –3 –3 –4 –20 –4 4.7 5.0 5.3 VCL – Supply voltage [V] Frequency response vs. Supply voltage 0 Input = 300mVp-p 4.43MHz, sine wave 1 Insertion gain vs. Ambient temperature Input = 1.28Vp-p 250kHz, sine wave fG – Frequency response [dB] –1 IG – Insertion gain [dB] 9.0 VDD – Supply voltage [V] 9.5 0 –2 –1 –3 –2 –4 8.5 –3 –20 0 20 40 60 Ta – Ambient temperature [°C] –6– CXL5003M/P Insertion gain vs. Supply voltage 1 Input = 1.28Vp-p 250kHz, sine wave 1 Insertion gain vs. Supply voltage Input = 1.28Vp-p 250kHz, sine wave IG – Insertion gain [dB] 0 IG – Insertion gain [dB] 4.7 5.0 5.3 VCL – Supply voltage [V] 0 –1 –1 –2 –2 –3 –3 8.5 9.0 VDD – Supply voltage [V] 9.5 Differential gain vs. Ambient temperature Differential gain vs. Supply voltage DG – Differential gain [%] DG – Differential gain [%] 0 20 40 60 Ta – Ambient temperature [°C] 4 4 3 3 2 2 1 1 0 –20 0 4.7 5.0 5.3 VCL – Supply voltage [V] Differential gain vs. Supply voltage 0 4 –1 Frequency response DG – Differential gain [%] Gain [dB] 3 –2 –3 2 –4 1 10k 100k f – Frequency [Hz] 1M 0 8.5 9.0 VDD – Supply voltage [V] 9.5 –7– CXL5003M/P Package Outline CXL5003M Unit: mm 8PIN SOP (PLASTIC) + 0.4 6.1 – 0.1 + 0.4 1.85 – 0.15 8 5 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 1 0.45 ± 0.1 4 + 0.1 0.2 – 0.05 1.27 6.9 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L01 SOP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.1g CXL5003P 8PIN DIP (PLASTIC) 8 5 7.62 + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g 1 2.54 4 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN 0.5 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 DIP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS –8– 0.5 ± 0.2