CXL5005M

CXL5005M/P CMOS-CCD 1H Delay Line for NTSC with PLL Description The CXL5005M/P are general-purpose CCD delay line ICs which provide 1H delay time of NTSC. Features • Low power consumption 90mW (Typ.) • Small size package (14-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal ampiitude 180 IRE (= 1.28Vp-p, max.) • Low input clock amplitude operation 200mVp-p (Min.) • Built-in triple PLL circuit • Built-in peripheral circuits (clock driver, timing generator, auto-bias and output circuits) Functions • 680-bit CCD register • Clock drivers • Autobias circuit • Sync tip clamp circuit • Sample-and-hold circuit • PLL (triple) Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) 11 V • Supply voltage VDD 6 V • Supply voltage VCL • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5005M 400 mW CXL5005P 800 mW Recommended Operating Conditions Supply voltage VDD 9 ± 5% V 5 ± 5% V VCL Recommended Clock Conditions • Input clock amplitude VCLK 200mVp-p to 1.0Vp-p (300mVp-p typ.) • Clock frequency fCLK 3.579545MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5005M 14 pin SOP (Plastic) CXL5005P 14 pin DIP (Plastic) –1– E88Z40A79-PS CXL5005M/P Blook Diagram and Pin configuration AUTO FEED OUT CLK VCL 8 7 IN 14 13 Auto-bias circuit NC 12 11 Output & S/H (1 BIT) 10 9 Phase comparator Clamp circuit 680 bit shift register φ1 φ2 1/3 counter VCO Clock driver 1 2 3 4 5 6 VCOIN VCL VDD VSS PCOUT NC Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VSS VCL VCOIN VDD PCOUT NC VCOOUT VCL CLK NC OUT FEED AUTO IN Signal output Feedback DC output Autobias DC output Signal input 600 to 1k > 100k ≈ 10k > 100k VCO output 5V power supply Clock input ≈ 5k ≈ 5k GND 5V power supply VCO input 9V power supply Phase comparator output ≈ 5k > 100k Description Impedance [Ω] –2– VCOOUT CXL5005M/P Electrical Characteristics (Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 3.58MHz, VCLK = 300mVp-p sine wave, See "Electrical Characteristics Test Circuit") Item Symbol IDD ICL Test condition 250kHz, 1.28Vp-p, sine wave input 250kHz, 1.28Vp-p, sine wave input IG = 20 log (Output voltage [Vp-p] / 1.28 [Vp-p]) Dissipation at 3.58MHz in relation to 250kHz fG = 20 log (V3.58MHz/ V250kHz) (Note 1) 5-staircase wave input Y = 140 IRE (= 1.0Vp-p) Measure with vector scope (Note 2) SW condition 1 a 2 a Measuring point A1 A2 Min. — — Typ. Max. Unit 4.0 9.0 5.0 12.0 mA mA Supply current Insertion gain IG a a V1 –3.0 0.0 3.0 dB Frequency response fG b, c b V1 –3.0 –2.1 — dB Differential gain DG — e a S — — — — — 3.0 3.0 — 5.0 5.0 % deg Differential phase DP Allowable input amplitude VIN-AC 1.28 Vp-p Noise S/N S: Input = 250kHz, 1.0Vp-p output (Vp-p) N: Input = DC GND output (Vrms) f a V2 55 60 — dB d d a a V3 V4 V5 V6 3.5 3.5 1.3 1.7 5.0 5.0 2.3 2.7 6.5 6.5 3.3 3.7 V V V V VIN-DC DC output voltage VAUTO-DC VFEED-DC 250kHz, 1.28Vp-p, VOUT-DC sine wave input a a –3– Electrical Characteristics Test Circuit CLK fCLK = 3.58MHz VCLK = 300mVp-p sine wave 9V V5 0.01µF 5600 2SA1175 Note 3) SW2 14 12 11 10 8 13 9 V1 V6 LPF BPF Note 4) V2 S Vector scope a. 250kHz, 1.28Vp-p sine wave 0.1µF SW1 b. 250kHz, 300mVp-p sine wave c. 3.58MHz, 300mVp-p sine wave d. Ground NC f. CXL5005M/P 250kHz, 1.0Vp-p sine wave 1M 100k AUTO FEED VDD OUT NC 6 7 56k CLK VCOOUT VCL e. 5-staircase wave V3 IN a b 0.1µF 0.1µF V4 VSS 1500 –4– VBIAS 1 2 3 4 5 A2 5V 0.1µF 9V VCL VCOIN A1 PCOUT CXL5005M/P CXL5005M/P Note 1) Frequency response test condition V3.58MHz (Output signal voltage [Vp-p] at 3.58MHz input) V250kHz (Output signal voltage [Vp-p] at 250kHz input) Set Pin 14 (IN) voltage [V] = VIN-DC + 640mV. [V] 3.58MHz, 300mVp-p sine wave 250kHz, 300mVp-p sine wave 640mV (adjust with VBIAS) VIN-DC Note 2) Differential gain and differential phase test condition 5-staircase wave signal Chroma 40 IRE 140 IRE (1.0Vp-p) 40 IRE 1H 63.5µs DG and DP are measured at output S point by vector scope. Note 3) LPF frequency response (Delay time 140ns) Note 4) BPF frequency response [dB] 0 –3 [dB] 0 –3 –50 0 5.8 Frequency [MHz] 10.7 –50 0 50 200 4.1M 10.7M Frequency [Hz] –5– CXL5005M/P Application Circuit 0.1µF 0.1µF Composite video signal input 14 1M 13 12 11 10 0.1µF fCLK = 3.58MHz CLK VCLK = 300mVp-p sine wave 5600 0.01µF 2SA1175 9 8 5V CXL5005M/P 9V L. P. F Delay time 1H delay signal output 140ns 1 2 3 4 5 6 56k 7 Example of Pin 7 (VCO output) usage +9V 5V 1500 5.6k 9V 7 2SC403 3 × fsc 0.1µF 5.6k Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Example of Representative Characteristics Frequency response vs. Ambient temperature 0 Input = 300mVp-p 3.58MHz, sine wave 0 Frequency response vs. Supply voltage Input = 300mVp-p 3.58MHz, sine wave fG – Frequency response [dB] fG – Frequency response [dB] 0 20 40 60 –1 –1 –2 –2 –3 –3 –4 –20 –4 4.7 5.0 5.3 Ta – Ambient temperature [°C] VCL – Supply voltage [V] Frequency response vs. Supply voltage 0 Input = 300mVp-p 3.58MHz, sine wave 1 Insertion gain vs. Ambient temperature Input = 1.28Vp-p 250kHz, sine wave fG – Frequency response [dB] IG – Insertion gain [dB] 9.0 VDD – Supply voltage [V] 9.5 –1 0 –2 –1 –3 –2 –4 8.5 –3 –20 0 20 40 60 Ta – Ambient temperature [°C] –6– CXL5005M/P Insertion gain vs. Supply voltage 1 Input = 1.28Vp-p 250kHz, sine wave 1 Insertion gain vs. Supply voltage Input = 1.28Vp-p 250kHz, sine wave IG – Insertion gain [dB] 0 IG – Insertion gain [dB] 4.7 5.0 5.3 VCL – Supply voltage [V] 0 –1 –1 –2 –2 –3 –3 8.5 9.0 VDD – Supply voltage [V] 9.5 Differential gain vs. Ambient temperature Differential gain vs. Supply voltage DG – Differential gain [%] 4 4 DG – Differential gain [%] 0 20 40 60 3 3 2 2 1 1 0 –20 0 4.7 5.0 VCL – Supply voltage [V] 5.3 Ta – Ambient temperature [°C] Differential gain vs. Supply voltage 0 Frequency response DG – Differential gain [%] 4 –1 Ta = 25°C Gain [dB] 3 –2 –3 2 –4 1 10k 100k Frequency [Hz] 1M 0 8.5 9.0 VDD – Supply voltage [V] 9.5 –7– CXL5005M/P Package Outline CXL5005M Unit: mm 14PIN SOP (PLASTIC) + 0.4 9.9 – 0.1 + 0.4 1.85 – 0.15 14 8 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-14P-L01 SOP014-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.2g CXL5005P + 0.4 19.2 – 0.1 14PIN DIP (PLASTIC) + 0.1 05 0.25 – 0. 14 8 7.62 + 0.3 6.4 – 0.1 0° to 15° 1 2.54 7 0.5 MIN 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-14P-01 DIP014-P-0300 Similar to MO-001-AH LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.9g –8– 0.5 ± 0.2 1 7 6.9