CXL5502P

CXL5502M/N/P CMOS-CCD 1H Delay Line for NTSC For the availability of this product, please contact the sales office. Description The CXL5502M/N/P are CMOS-CCD delay line ICs that provide 1H delay time for NTSC signals including the external low-pass filter. The ICs contain a PLL circuit (quadruple progression). Features • Single power supply (5V) • Low power consumption 95mW (Typ.) • Built-in peripheral circuits • Clamp level of I/O signal can be selected • Built-in quadruple PLL circuit Functions • 905-bit CCD register • Clock driver • Autobias circuit • Input clamp circuit • Sample and hold circuit • PLL circuit (quadruple progression) Structure CMOS-CCD CXL5502M 14 pin SOP (Plastic) CXL5502N 16 pin SSOP (Plastic) CXL5502P 14 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5502M 400 mW CXL5502N 260 mW CXL5502P 800 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 3.579545 MHz • Input clock waveform Sine wave Input Signal Amplitude VSIG 500mVp-p (Typ.), 572mVp-p (Max.) (at internal clamp condition) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89930E79-PS CXL5502M/N/P Block Diagram and Pin Configuration (Top View) CXL5502M/P VCO IN 11 PC OUT 10 VSS 14 AB 13 VDD 12 VDD 9 CLK 8 PLL Autobias circuit Clock driver CCD (905bit) Output circuit (S/H 1bit) Clamp circuit I/O control Timing circuit Bias circuit (A) Bias circuit (B) 1 IN 2 I/O1 3 I/O2 4 OUT 5 VSS 6 VSS 7 VCO OUT CXL5502N VSS 16 AB 15 VDD 14 VCO OUT 13 PC OUT 12 (N.C) 11 VDD 10 CLK 9 PLL Autobias circuit Clock driver Timing circuit CCD (905bit) Output circuit (S/H 1bit) Clamp circuit I/O control Bias circuit (A) Bias circuit (B) 1 IN 2 I/O1 3 I/O2 4 OUT 5 VSS 6 (N.C) 7 VSS 8 VCO OUT –2– CXL5502M/N/P Pin Description CXL5502M/P Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol IN I/O1 I/O2 OUT VSS VSS VCO OUT CLK VDD PC OUT VCO IN VDD AB VSS I/O I I I O — — O I — O I — O — Description Signal input I/O control 1 I/O control 2 Signal output GND GND VCO output Clock input Power supply (5V) Phase comparator output VCO input Power supply (5V) Autobias DC output GND (SUB) 600 to 200kΩ > 100kΩ 40 to 500Ω Impedance > 10kΩ at no clamp CXL5502N Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol IN I/O1 I/O2 OUT VSS (N.C) VSS VCO OUT CLK VDD (N.C) PC OUT VCO IN VDD AB VSS I/O I I I O — — — O I — — O I — O — Description Signal input I/O contorl 1 I/O contorl 2 Signal output GND — GND VCO output Clock input Power supply (5V) — Phase comparator output VCO input Power supply (5V) Autobias DC output GND (SUB) 600 to 200kΩ > 100kΩ 40 to 500Ω Impedance > 10kΩ at no clamp –3– CXL5502M/N/P Description of Function In the CXL5502M/N/P, the condition of I/O control pins (Pins 2 and 3) control the input signal clamp condition and the mode of the output signal with relation to its input signal. There are 2 modes for the I/O signal. Input waveform Output waveform (1) PN mode (Low level clamp/reverse phase output mode) (2) NP mode (High level clamp/positive phase output mode) Clamp level Clamp level I/O Control Pin (1) I/O1 (Pin 2) Control of the I/O signal condition DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling capacitor of around 1000pF is necessary. GND ............. Input signal is high level clamped and the output signal turns into an inverted signal. (2) I/O2 (Pin 3) Control of the input signal clamp condition 0V ................. Internal clamp condition 5V ................. Non internal clamp condition Center biased to approx. 2.1V by means of the IC internal resistance (several 10kΩ). Usage in this mode is limited to APL 50% signals and in this mode, the maximum input signal amplitude is 200mVp-p. –4– CXL5502M/N/P Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, Sine wave) See "Electrical Characteristics Test Circuit" Bias condition Vbias1 (V) Min. 1234567 (Note 1) Item Supply current Low frequency gain Frequency response Differential gain Differential phase S/H pulse coupling S/N ratio Symbol IDDPN IDDNP GLPN GLNP fPN fNP DGPN DGNP DPPN DPNP CPPN CPNP SNPN SNNP Test condition SW condition Typ. Max. Unit Note — 200kHz, 500mVp-p, sine wave —c b bb aa a— — 10 19 28 mA 2 aab bb aa ab — –2 0 2 dB 3 200kHz ← 3.57MHz, b → bb 150mVp-p, aa bb aa sine wave c ← → 5-staircase wave (See Note 5) 5-staircase wave (See Note 5) No signal input 50% white video signal (See Note 7) 2.1 –2 –1 0 dB 4 d a b a b b bb aa bb aa bb aa bb aa ac — 0 5 7 % 5 d b ac — VINPN + 0.5 0 5 7 degree 5 —c a a b ba VINNP — — — 350 mVp-p 6 e b ad 52 56 — dB 7 Notes (1) VINPN and VINNP are defined as follows. VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync tip level. CXL5502 1 Input (IN) VINPN VINNP Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions. Item VINPN VINNP SW condition 1 — — 2 c c 3 b b 4 b a 5 b a 6 a a 7 — — Test point V1 –5– CXL5502M/N/P (2) This is the IC supply current value during clock and signal input. (3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. (Example of calculation) GLPN = 20 log OUT pin output voltage (PN mode) [mVp-p] 500 [mVp-p] [dB] (4) Indicates the dissipation at 3.57MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made according to the following formula. The input part bias is tested at 2.1V. (Example of calculation) fPN = 20 log OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p] OUT pin output voltage (PN mode, 200kHz) [mVp-p] [dB] (5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is input are tested at the vector scope. 143mV 357mV 500mV 143mV 1H 63.56µs Input waveform (Input waveform of NP mode is the inverted waveform in the figure above) (6) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP modes respectively. Test value (mVp-p) –6– CXL5502M/N/P (7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µs Input waveform (Input waveform of NP mode is the inverted waveform in the figure above) Clock fsc (3.579545MHz) sine wave 0.3Vp-p to 1.0Vp-p (0.5Vp-p typ.) –7– Electrical Characteristics Test Circuit (Using CXL5502M/P) CLK fSC (3.579545MHz) 0.5Vp-p sine wave 3.3µ 0.1µ 1k 82k 0.1µ 1000P 3.3µ 1000P 200kHz 500mVp-p sine wave 1µ a 200kHz 150mVp-p sine wave CXL5502M/P 9V b 2.1k 1 a IN 1 2 3 7 SW7 c 4 b SW2 –1 1µ 1000P 1000P SW5 a b 1M SW4 a b Note 1) [dB] LPF frequency response b a SW6 d b SW3 c a 1k 5 6 I/O1 I/O2 OUT VSS VSS VCO OUT b 14 VSS a 13 AB 9 12 8 11 10 VDD VCO PC VDD CLK IN OUT Oscilloscope Spectrum analyzer Note 1) LPF Note 2) BPF ×3 Noise meter ×3 SW1 –8– A Vbias1 3.57MHz 150mVp-p sine wave c Vector scope d 5-staircase wave 50% white video signal e Note 2) [dB] BPF frequency response 5V 0 –3 0 –3 V1 –50 6M Frequency 14.3M [Hz] –50 200 6M Frequency 14.3M [Hz] CXL5502M/N/P ∗ When using CXL5502N, change the connection terminal only. (See the block diagram and pin configuration. For NC pins, ground them.) Application Circuit (Using CXL5502M/P) fSC 0.5Vp-p sine wave ∗ When using CXL5502N, change the connection terminal only. (See the block diagram and pin configuration. For NC pins, ground them.) 5V 3.3µ 0.1µ 1k 82k 0.1µ 10 8 9 1000P 3.3µ 1000P 1µ 14 11 CXL5502M/P 13 12 1 2 3 7 1000P 2700 1M 330k 33p 1µ 5V LPF (Reverse phase signal) 560k 1k 27p 470 4 5 6 –9– 2SC403 4fSC Transistor used PNP : 2SA1175 Delay time 250ns (Positive phase signal) Input 1µ 5V 2200 Output 2200 2200 (Positive phase signal) Transistor used NPN : 2SC403 (ex. TH356LSM-4303ZED Toukou made) VCO OUT (Pin 7) in use 1.8k 7 1.8k Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5502M/N/P CXL5502M/N/P Example of Representative Characteristics Supply current vs. Ambient temperature 30 Low frequency gain vs. Ambient temperature 1 20 Low frequency gain [dB] 0 20 40 60 80 0 Supply current [mA] –1 –2 10 –20 –3 –20 0 20 40 60 80 Ambient temperature [°C] Ambient temperature [°C] Frequency response vs. Ambient temperature 0 10 Differential gain vs. Ambient temperature 8 Frequency response [dB] –1 Differential gain [%] 0 20 40 60 80 6 4 –2 2 –3 –20 0 –20 0 20 40 60 80 Ambient temperature [°C] Ambient temperature [°C] Supply current vs. Supply voltage 30 1 Low frequency gain vs. Supply voltage 20 Low frequency gain [dB] 5 Supply voltage [V] 5.25 0 Supply current [mA] –1 –2 10 4.75 –3 4.75 5 Supply voltage [V] 5.25 – 10 – CXL5502M/N/P Frequency response vs. Supply voltage 0 10 Differential gain vs. Supply voltage 8 Frequency response [dB] –1 Differential gain [%] 5 Supply voltage [V] 5.25 6 4 –2 2 –3 4.75 0 4.75 5 Supply voltage [V] 5.25 Frequency response 2 0 Gain [dB] –2 –4 –6 10k 100k Frequency [Hz] 1M 10M – 11 – CXL5502M/N/P Package Outline CXL5502M Unit: mm 14PIN SOP (PLASTIC) + 0.4 9.9 – 0.1 + 0.4 1.85 – 0.15 14 8 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-14P-L01 SOP014-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.2g 14PIN SOP (Plastic) 300mil 10.2 ± 0.3 14 8 0.15 5.3 ± 0.3 7.8 ± 0.4 A 1 1.44 MAX 1.27 7 0.4 ± 0.1 0.15 ± 0.05 20 MAX 0.05 MIN 0.13 M DETAIL A 10° MAX PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-14P-L121 ∗SOP014-P-0300-AX LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.2g – 12 – 0.75 ± 0.2 0.5 ± 0.2 1 7 6.9 CXL5502M/N/P CXL5502N ∗5.0 ± 0.1 16PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 0.1 16 9 A ∗4.4 ± 0.1 1 8 0.65 + 0.05 0.15 – 0.02 + 0.1 0.22 – 0.05 0.13 M 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-16P-L01 SSOP016-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g CXL5502P + 0.4 19.2 – 0.1 14PIN DIP (PLASTIC) + 0.1 05 0.25 – 0. 0.5 ± 0.2 14 8 7.62 + 0.3 6.4 – 0.1 6.4 ± 0.2 0° to 15° 1 2.54 7 0.5 MIN 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-14P-01 DIP014-P-0300 Similar to MO-001-AH LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.9g – 13 –