CXL5504P

CXL5504M/P CMOS-CCD 1H Delay Line for NTSC For the availability of this product, please contact the sales office. Description The CXL5504M/P are CMOS-CCD delay line ICs that provide 1H delay time for NTSC signals including the external low-pass filter. Features • Single power supply (5V) • Low power consumption 90mW (Typ.) • Built-in peripheral circuits • Clamp level of I/O signal can be selected Functions • 905-bit CCD register • Clock driver • Autobias circuit • Input clamp circuit • Sample and hold circuit Structure CMOS-CCD CXL5504M 8 pin SOP (Plastic) CXL5504P 8 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5504M 350 mW CXL5504P 480 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.4 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 14.318182 MHz • Input clock waveform Sine wave Input Signal Amplitude VSIG 500mVp-p (Typ.), 572mVp-p (Max.) (at internal clamp condition) Blook Diagram and Pin Configration (Top View) CLK 5 Timing circuit Clock driver Bias circuit (A) Output circuit (S/H 1bit) Clamp circuit I/O control Bias circuit (B) 4 8 7 6 Autobias circuit Bias circuit CCD (905bit) 1 2 3 IN I/O2 OUT I/O1 VDD AB Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– VSS E89931C79-PS CXL5504M/P Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol IN I/O2 OUT VSS CLK I/O1 VDD AB I/O I I O — I I — O Description Signal input I/O control 2 Signal output GND Clock input I/O control 1 Power supply (5V) Autobias DC output 600 to 200kΩ > 100kΩ 40 to 500Ω Impedance > 10kΩ at no clamp Description of Function In the CXL5504M/P, the condition of I/O control pins (Pins 2 and 6) control the input signal clamp condition and the mode of the output signal with relation to its input signal. There are 2 modes for the I/O signal. Input waveform Output waveform (1) PN mode (Low level clamp/reverse phase output mode) (2) NP mode (High level clamp/positive phase output mode) Clamp level Clamp level I/O Control Pin (1) I/O1 (Pin 6) Control of the I/O signal condition DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling capacitor of around 1000pF is necessary. GND ............. Input signal is high level clamped and the output signal turns into an inverted signal. (2) I/O2 (Pin 2) Control of the input signal clamp condition 0V ................. Internal clamp condition 5V ................. Non internal clamp condition Center biased to approx. 2.1V by means of the IC internal resistance (several 10kΩ). Usage in this mode is limited to APL 50% signals and in this mode, the maximum input signal amplitude is 200mVp-p. –2– CXL5504M/P Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 14.318182MHz, VCLK = 500mVp-p, Sine wave) See "Electrical Characteristics Test Circuit" Bias condition Vbias1 (V) Min. 1234567 (Note 1) Item Supply current Low frequency gain Frequency response Differential gain Differential phase S/H pulse coupling S/N ratio Symbol IDDPN IDDNP GLPN GLNP fPN fNP DGPN DGNP DPPN DPNP CPPN CPNP SNPN SNNP Test condition SW condition Typ. Max. Unit Note — 200kHz, 500mVp-p, sine wave —c b bb aa a— — 10 18 28 mA 2 aab bb aa ab — –2 0 2 dB 3 200kHz ← 3.57MHz, b → bb 150mVp-p, aa bb aa sine wave c ← → 5-staircase wave (See Note 5) 5-staircase wave (See Note 5) No signal input 50% white video signal (See Note 7) 2.1 –2 –1 0 dB 4 d a b a b b bb aa bb aa bb aa bb aa ac — 0 5 7 % 5 d b ac — VINPN + 0.5 0 5 7 degree 5 —c a a b ba — — 350 mVp-p 6 VINNP — 52 56 — dB 7 e b ad Notes (1) VINPN and VINNP are defined as follows. VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync tip level. CXL5504 1 Input (IN) VINPN VINNP Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions. Item VINPN VINNP SW condition 1 — — 2 c c 3 b b 4 b a 5 b a 6 a a 7 — — Test point V1 –3– CXL5504M/P (2) This is the IC supply current value during clock and signal input. (3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. (Example of calculation) GLPN = 20 log OUT pin output voltage (PN mode) [mVp-p] 500 [mVp-p] [dB] (4) Indicates the dissipation at 3.57MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made according to the following formula. The input part bias is tested at 2.1V. (Example of calculation) fPN = 20 log OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p] OUT pin output voltage (PN mode, 200kHz) [mVp-p] [dB] (5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is input are tested at the vector scope. 143mV 357mV 500mV 143mV 1H 63.56µs Input waveform (Input waveform of NP mode is the inverted waveform in the figure above) (6) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP modes respectively. Test value (mVp-p) –4– CXL5504M/P (7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µs Input waveform (Input waveform of NP mode is the inverted waveform in the figure above) Clock fsc (14.318182MHz) sine wave 0.4 to 1.0Vp-p (0.5Vp-p typ.) –5– Electrical Characteristics Test Circuit CLK 4fSC (14.318182MHz) 0.5Vp-p sine wave 3.3µ b SW5 a 1000p 1000p 200kHz 500mVp-p sine wave 1µ 8 AB CXL5504M/P 9V b a IN I/O2 2 3 4 2.1k Note 1) SW7 c 1µ c SW3 a a b 1M SW4 a b Note 1) [dB] LPF frequency response Vbias1 1 5V 0 –3 1k b SW6 1000p d BPF LPF Note 2) ×3 ×3 OUT VSS 1 b SW2 –1 1 VDD CLK I/O1 a 7 6 5 0.1µ a 200kHz 150mVp-p sine wave b Osilloscope Spectrum analyzer –6– –50 SW1 3.57MHz 150mVp-p sine wave c Vector scope Noise meter d 5-staircase wave 50% white video signal e Note 2) [dB] BPF frequency response 0 –3 –50 6M Frequency [Hz] 14.3M 200 6M 14.3M Frequency [Hz] CXL5504M/P Application Circuit (Using PN mode) 4fSC 0.5Vp-p sine wave 5V 3.3µ 1000p 1µ 8 12 7 6 10 5 1000p 0.1µ CXL5504M/P 1 2 3 4 –7– 2700 1M 330k 1µ 470 33p LPF (Reverse phase signal) 560k 1k 27p Transistor used PNP: 2SA1175 (Positive phase signal) Input 1µ 5V 2200 Output 2200 2200 (Positive phase signal) Delay time 250ns Transistor used NPN: 2SC403 (ex. TH356LSM-4303ZED Toukou made) CXL5504M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5504M/P Example of Representative Characteristics Supply current vs. Ambient temprature 30 Low frequency gain vs. Ambient temprature 1 20 Low frequency gain [dB] 0 20 40 60 Ambient temprature [°C] 0 Supply current [mA] –1 –2 10 –20 80 –3 –20 0 20 40 60 Ambient temprature [°C] 80 Frequency response vs. Ambient temprature 0 10 Differential gain vs. Ambient temprature 8 Frequency response [dB] –1 Differential gain [%] 0 6 4 –2 2 –3 –20 20 40 60 Ambient temprature [°C] 80 0 –20 0 20 40 60 Ambient temprature [°C] 80 Supply current vs. Supply voltage 30 1 Low frequency gain vs. Supply voltage 20 Low frequency gain [dB] 5 Supply voltage [V] 5.25 0 Supply current [mA] –1 –2 10 4.75 –3 4.75 –8– 5 Supply voltage [V] 5.25 CXL5504M/P Frequency response vs. Supply voltage 0 10 Differential gain vs. Supply voltage 8 Frequency response [dB] –1 Differential gain [%] 6 4 –2 2 –3 4.75 5 Supply voltage [V] 5.25 0 4.75 5 Supply voltage [V] 5.25 Frequency response 2 0 Gain [dB] –2 –4 –6 10k 100k Frequency [Hz] 1M 10M –9– CXL5504M/P Package Outline Unit: mm CXL5504M 8PIN SOP (PLASTIC) + 0.4 6.1 – 0.1 + 0.4 1.85 – 0.15 8 5 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 1 0.45 ± 0.1 4 + 0.1 0.2 – 0.05 1.27 6.9 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L01 SOP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.1g 8PIN SOP (PLASTIC) 6.2 ± 0.3 8 5 S 0.15 S 5.3 ± 0.3 7.8 ± 0.4 A 1 0.4 ± 0.1 4 + 0.05 0.15 – 0.02 1.27 0.05 MIN 0.13 M S 10° MAX DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L121 SOP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.1g – 10 – 0.75 ± 0.2 2.0MAX 0.5 ± 0.2 CXL5504M/P CXL5504P 8PIN DIP (PLASTIC) 8 5 7.62 + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g 1 2.54 4 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN 0.5 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 DIP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 11 –