CXL5505M

CXL5505M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5505M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. Features • Single 5V power supply • Low power consumption 100mW (Typ.) • Built-in peripheral circuits • Built-in quadruple PLL circuit Functions • 1130-bit CCD register • Clock driver • Auto-bias circuit • Input clamp circuit • Sample-and-hold circuit • PLL circuit Structure CMOS-CCD CXL5505M 14 pin SOP (Plastic) CXL5505P 14 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5505M 400 mW CXL5505P 800 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 4.433619 MHz • Input clock waveform Sine wave Input Signal Amplitude VSIG 575mVp-p (Max.) (at internal clamp condition) Blook Diagram and Pin Configuration (Top View) VCO IN PC OUT CLK 8 PLL Timing circuit Bias circuit (A) Output circuit (S/H 1bit) Clamp circuit Bias circuit (B) 7 VDD 14 13 AB 12 11 10 Auto-bias circuit CCD (1130bit) Clock driver 1 2 3 4 5 VG2 VSS IN OUT VG1 VSS VDD 9 6 VSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– VCO OUT E90731B7X-PS CXL5505M/P Pin Description Pin No. 1 2 3∗ 4 5 6 7 8 9 10 11 12 13 14 Symbol IN VG1 VG2 OUT VSS VSS VCO OUT CLK VDD PC OUT VCO IN VDD AB VSS I/O I O I O — — O I — O I — O — Description Signal input Gate bias 1 DC output Gate bias 2 DC input Signal output GND GND VCO output Clock input Power supply (5V) Phase comparator output VCO input Power supply (5V) Auto-bias DC output GND (SUB) 600 to 200kΩ > 10kΩ 40 to 500Ω Impedance > 10kΩ at no clamp ∗ Description of Pin 3 (VG2) Control of input signal clamp condition 0V ........ Sync tip clamp condition 5V ........ Center bias condition Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is 200mVp-p. Input waveform Output waveform Clamp level –2– CXL5505M/P Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" Item Supply current Low frequency gain Symbol IDD GL Test condition — 200kHz, 500mVp-p, sine wave 200kHz ← 4.43MHz, → 150mVp-p, sine wave 5-staircase wave (See Note 4) 5-staircase wave (See Note 4) No signal input 50% white video signal (See Note 6) SW condition 1 a a b ← → 2 a a Min. Typ. Max. Unit Note 3 — b 11 –2 20 0 29 2 mA dB 1 2 Frequency response fR b b –2 –1 0 dB 3 c d d f e a a b a c c a d 0 0 — 52 3 3 — 56 5 5 % degree Differential gain Differential phase S/H pulse coupling S/N ratio DG DP CP SN 4 4 5 6 350 mVp-p — dB Notes (1) This is the IC supply current value during clock and signal input. (2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] (3) Indicates the dissipation at 4.43MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 4.43MHz sine wave is fed to same, calculation is made according to the following formula. fR = 20 log OUT pin otuput voltage (4.43MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p] –3– CXL5505M/P (4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when the 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64µs Input waveform (5) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Test value (mVp-p) (6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64µs Input waveform Clock fsc (4.433619MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p typ.) –4– Electrical Characteristics Test Circuit CLK fSC (4.433619MHz) 0.5Vp-p sine wave 3.3µ 0.1µ 3.3µ 1k 82k 1µ 14 11 8 CLK 9V b 2.1k Note 1) SW3 c 1µ 1M SW2 a b 1000p 1000p d BPF LPF Note 2) ×3 ×3 a VSS AB VDD VCO PC VDD IN OUT 13 12 10 9 0.1µ 1000p 1000p 200kHz 500mVp-p sine wave a 200kHz 150mVp-p sine wave IN 1 VG1 VG2 OUT VSS 5 2 3 4 VSS 6 VCO OUT 7 b Oscilloscope Spectrum analyzer –5– Note 1) 5V 0 –3 –50 SW1 4.43MHz 150mVp-p sine wave c Vector scope Noise meter 5-staircase wave d Note 2) [dB] LPF frequency response [dB] BPF frequency response 0 –3 50% white video signal e f –50 7M Frequency [Hz] 17.7M 200 7M 17.7M Frequency [Hz] CXL5505M/P Application Circuit fSC (4.433619MHz) 0.5Vp-p sine wave 5V 3.3µ 0.1µ 3.3µ 1k 82k 1µ 14 11 8 13 12 10 9 0.1µ 1000p 1000p –6– 1 2 3 4 7 6 5 1000p 1M 330k 1µ 470 LPF (Inverted signal) 560k 1k 27p 4fSC Transistor used PNP: 2SA1175 Delay time 190ns (Non-inverted signal) Input 1µ 5V 2200 5V When VCO OUT (Pin 7) in used. Output 2200 2200 (Non-inverted signal) Transistor used NPN: 2SC2785 (ex. TH328LNLS-2620 Toukou made) 1.8k 2SC403 7 1.8k CXL5505M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5505M/P Example of Representative Characteristics Supply current vs. Ambient temperature 30 Low frequency gain vs. Ambient temperature 2 20 Low frequency gain [dB] 0 20 40 60 Ambient temperature [°C] 1 Supply current [mA] 0 –1 10 –20 80 –2 –20 0 20 40 60 Ambient temperature [°C] 80 Frequency response vs. Ambient temperature 0 10 Differential gain vs. Ambient temperature 8 Frequency response [dB] –1 Differential gain [%] 0 6 4 –2 2 –3 –20 20 40 60 Ambient temperature [°C] 80 0 –20 0 20 40 60 Ambient temperature [°C] 80 Supply current vs. Supply voltage 30 2 Low frequency gain vs. Supply voltage 20 Low frequency gain [dB] 5 Supply voltage [V] 5.25 1 Supply current [mA] 0 –1 10 4.75 –2 4.75 –7– 5 Supply voltage [V] 5.25 CXL5505M/P Frequency response vs. Supply voltage 0 10 Differential gain vs. Supply voltage 8 Frequency response [dB] –1 Differential gain [%] 6 4 –2 2 –3 4.75 5 Supply voltage [V] 5.25 0 4.75 5 Supply voltage [V] 5.25 Frequency response 2 0 Gain [dB] –2 –4 –6 10k 100k Frequency [Hz] 1M 10M –8– CXL5505M/P Package Outline CXL5505M Unit: mm 14PIN SOP (PLASTIC) + 0.4 9.9 – 0.1 + 0.4 1.85 – 0.15 14 8 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-14P-L01 SOP014-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.2g CXL5505P 14PIN DIP (PLASTIC) + 0.4 19.2 – 0.1 14 8 7.62 + 0.3 6.4 – 0.1 + 0.1 05 0.25 – 0. 0° to 15° EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.9g 1 2.54 7 0.5 MIN 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-14P-01 DIP014-P-0300 Similar to MO-001-AH LEAD TREATMENT LEAD MATERIAL PACKAGE MASS –9– 0.5 ± 0.2 1 7 6.9