CXL5507P

CXL5507M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5507M/P are CMOS-CCD delay line ICs that provide 1H delay time for NTSC signals including the external low-pass filter. Features • Single 5V power supply • Low power consumption 50mW (Typ.) • Built-in peripheral circuits Functions • 453-bit CCD register • Clock driver • Auto-bias circuit • Input clamp circuit • Sample-and-hold circuit Structure CMOS-CCD CXL5507M 8 pin SOP (Plastic) CXL5507P 8 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5507M 350 mW CXL5507P 480 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 7.159090 MHz • Input clock waveform Sine wave Blook Diagram and Pin Configuration (Top View) AB VDD Input Signal Amplitude VSIG 500mVp-p (Typ.), 527mVp-p (Max.) (at internal clamp condition) VGA 6 8 7 Auto-bias circuit Bias circuit Timing circuit CCD (453bit) Clock driver Bias circuit (A) Output circuit (S/H 1bit) Bias circuit (B) Clamp circuit 1 2 3 4 VGB OUT Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– VSS IN CLK 5 E90908A7X-PS CXL5507M/P Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol IN VGB OUT VSS CLK VGA VDD AB I/O I I O — I O — O Description Signal input Gate control B Signal output GND Clock input Gate control A Power supply (5V) Auto-bias DC output 600 to 200kΩ > 100kΩ 40 to 500Ω Impedance > 10kΩ at no clamp Description of I/O Signals Input signals are low level clamped and output signals are inverted in relation to the input signals. Also, the clamp condition of input signals are controlled by VGB (Pin 2) conditions. 0V ........ Internal clamp condition 5V ........ Non internal clamp condition Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is 200mVp-p. Input waveform Output waveform Clamp level Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 7.159090MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" Item Supply current Low frequency gain Frequency response S/H pulse coupling S/N ratio Symbol IDD GL fg CP SN LIS Linearity LIL LIC Test condition — SW condition 1 a 2 a a a 3 b b a a a b b b 4 a a b b b a a a 5 — b b a c a a a — 2.1 2.1 Bias condition V1 (V) Min. Typ. Max. Unit Note 5 –2 –2 — 54 37 18 56 10 0 –1 — 56 40 20 60 15 2 0 mA dB dB 1 2 3 4 5 200kHz, a 500mVp-p, sine wave 200kHz ← 2MHz, → b 150mVp-p, sine wave c No signal input No signal input 5-staircase wave (For luminance signals only) —b —b b b b a a a 350 mVp-p — 43 22 64 % dB 6 –2– CXL5507M/P Notes (1) This is the IC supply current value during clock and signal input. (2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] (3) Indicates the dissipation at 2MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, calculation is made according to the following formula. Input bias is tested at 2.1V. fg = 20 log OUT pin otuput voltage (2MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p] (4) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Input bias is tested at 2.1V. Test value (mVp-p) (5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following formula. S/N = –20 • Iog Noise (mVrms) [dB] 0.5 • 10 GL/20 (6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance signals only) and calculated according to the formula below. (However, output signals become inverted with regards to input.) Va 100 IRE Vc Vp Vs 40 IRE 500mV LIS = Vs × 100 [%] Va LIL = Vp × 100 [%] Va LIC = Vc × 100 [%] Va –3– CXL5507M/P Clock 2fsc (7.159090MHz) sine wave (0.5Vp-p typ.) –4– Electrical Characteristics Test Circuit CLK 2fSC (7.159090MHz) 0.5Vp-p sine wave 3.3µ 1000p 1000p 200kHz 500mVp-p sine wave 1µ 8 AB VGA 9V b IN VGB 2 3 4 OUT VSS 1 a SW2 b SW3 a a 1M b 1k b SW4 1000p 1µ 2.1k Note) SW5 c BPF ×3 VDD CLK a 7 6 5 0.1µ a 200kHz 150mVp-p sine wave b Oscilloscope –5– V1 5V Spectrum analyzer SW1 2MHz 150mVp-p sine wave c Noise meter 5-staircase wave (Luminance signals only) d Note) [dB] BPF frequency response 0 –3 –50 10k 3M 7.2M Frequency [Hz] CXL5507M/P Application Circuit 2fSC 0.5Vp-p sine wave 5V 3.3µ 1000p 1µ 1000p 12 7 6 10 5 0.1µ 8 –6– 1 2 3 4 2.2k LPF PNP: 2SA1175 Delay time 140ns Input 1µ 5V 2.2k 1M Output 2.2k 2.2k NPN: 2SC403 CXL5507M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5507M/P Example of Representative Characteristics Supply current vs. Supply voltage 20 1.5 Low frequency gain vs. Supply voltage 10 Low frequency gain [dB] 5 Supply voltage [V] 5.25 15 1 Supply current [mA] 0.5 5 0 0 4.75 –0.5 4.75 5 Supply voltage [V] 5.25 Frequency response vs. Supply voltage 0 44 Linearity (LIS) vs. Supply voltage Frequency response [dB] –0.5 Linearity (LIS) [%] 5 Supply voltage [V] 5.25 40 –1 –1.5 36 –2 4.75 32 4.75 5 Supply voltage [V] 5.25 Linearity (LIL) vs. Supply voltage 30 70 Linearity (LIC) vs. Supply voltage 66 25 Linearity (LIC) [%] 5 Supply voltage [V] 5.25 Linearity (LIL) [%] 62 20 58 15 54 10 4.75 50 4.75 –7– 5 Supply voltage [V] 5.25 CXL5507M/P Supply current vs. Ambient temperature 20 Low frequency gain vs. Ambient temperature 1.5 10 Low frequency gain [dB] 0 10 20 30 40 50 Ambient temperature [°C] 60 70 15 1 Supply current [mA] 0.5 5 0 0 –20 –10 –0.5 –20 –10 0 10 20 30 40 50 Ambient temperature [°C] 60 70 Frequency response vs. Ambient temperature 0 44 Linearity (LIS) vs. Ambient temperature Frequency response [dB] –0.5 Linearity (LIS) [%] 0 10 20 30 40 50 Ambient temperature [°C] 60 70 40 –1 –1.5 36 –2 –20 –10 32 –20 –10 0 10 20 30 40 50 Ambient temperature [°C] 60 70 Linearity (LIL) vs. Ambient temperature 30 70 Linearity (LIC) vs. Ambient temperature 66 25 Linearity (LIC) [%] 0 10 20 30 40 50 Ambient temperature [°C] 60 70 Linearity (LIL) [%] 62 20 58 15 54 10 –20 –10 50 –20 –10 –8– 0 10 20 30 40 50 Ambient temperature [°C] 60 70 CXL5507M/P Package Outline CXL5507M Unit: mm 8PIN SOP (PLASTIC) + 0.4 6.1 – 0.1 + 0.4 1.85 – 0.15 8 5 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 1 0.45 ± 0.1 4 + 0.1 0.2 – 0.05 1.27 6.9 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L01 SOP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.1g CXL5507P 8PIN DIP (PLASTIC) 8 5 7.62 + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g 1 2.54 4 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN 0.5 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 DIP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS –9– 0.5 ± 0.2